JPS5952850B2 - AD conversion device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AD converter that converts an analog signal into a digital signal. Generally, to convert an analog signal to a digital signal, it is necessary to sample the analog signal, quantize the sampled amplitude, and further encode the quantum number. Normally, the code is divided into n-bit codes in steps of . The larger the number of steps, the lower the quantization noise, but the more complex the circuit configuration becomes. Therefore, by dividing the amplitude of the input signal into several ranges,
By quantizing each of these divided ranges in 2n steps and converting them into n-bit codes, it is possible to obtain an effect equivalent to increasing the number of steps without increasing the number of bits used. ing. Furthermore, if the analog signal is an audio signal,
When the amplitude of the audio signal is large, the quantization noise is masked, so the audio signal is
When performing D conversion, it is preferable to make the quantization step coarse when the amplitude of the audio signal is large, and to make the quantization step thin when the amplitude is small. An apparatus that changes the quantization step depending on the amplitude of the analog signal in this way is called a nonlinear AD converter. Figure 1 shows an example of a conventional non-linear AD converter, in which the analog signal from input terminal 1 is sent to sampling hold circuit 2.
The sampling output thereof is supplied to the amplifier 3 and also to the comparator 4. When the amplitude of the analog signal is (0-Vm), the comparator 4 compares the sampling output Vi with the reference voltage, so that the sampling output Vi is (Vm≧Vi>2)c') Range E
7. Range E6 of (T-≧vi>-).・・・・・・
- (N animals≧Vi≧0) It detects which of the seven ranges E1 of Vm 4 64 is in, for example, and generates range bits indicating each range E1 to E7. The gain of the amplifier 3 is switched by this range bit. That is, when the sampling output Vi is in the range E7, the gain of the amplifier 3 is set to 1, and when it is in the range E6, the gain of the amplifier 3 is set to 2. can be switched to 4x, 8x...64x. Therefore, the output of amplifier 3■. is an AD converter (encoding circuit)
5 is converted into an n-bit code and appears at its output terminal 6. This n-bit code and the range bit from the comparator 4 are output. Although not shown, in order to convert a digital signal from such a non-linear AD converter into an analog signal, an n-bit code is given to a DA converter (decoding circuit), and the output analog signal is converted into an analog signal using a range bit. Gain is 1x, 172
The original analog signal can be obtained by supplying the signal to an amplifier that can be switched to multiply by 174 times, 178 times, . . . 1764 times. According to the above-mentioned non-linear AD converter, the smaller the amplitude of the analog signal, the finer the quantization step, which is convenient for converting the audio signal into PCM. However, it has the disadvantage of low accuracy due to errors caused by fluctuations in the reference voltage of the comparator 4, etc. As an example, when (Vm=10V), even though the sampling output Vi is 5.1■, the comparator 4 is 4.
．． If it is determined to be 99V, the gain of amplifier 3 is doubled, and the output of amplifier 3 becomes ■. becomes 10.2V. Therefore, since the AD converter 5 can perform AD conversion only up to 10V, its output is all 1 from the least significant bit (LSB) to the most significant bit (MSB). When this digital signal is subjected to DA conversion using the range bit, the DA conversion output of 10V is 172, so 5.
An analog output is obtained, and the original 5.1V is 0.1V.
This will result in an error of In addition, the gain of amplifier 3 must be switched over a wide range of 7 levels at very high speed, and it is difficult to create an amplifier with good characteristics that has such a function. An error will occur. As other non-linear AD conversion devices, it is possible to perform AD conversion of the sampling output as it is and then digitally perform non-linear processing, but in this case, even if high precision is achieved, AD conversion requires a large number of bits. In addition to this, the configuration of the digital circuit for performing the non-linearization process becomes complicated, resulting in a disadvantage that the device becomes expensive and complicated. The present invention aims to provide a highly accurate and inexpensive AD conversion device. Further, the present invention is a non-linear AD conversion device suitable for use in converting an audio signal into PCM. A device using a VTR has been proposed as a device for converting audio signals into PCM, and the present invention is suitable for such a device, and FIG. 2 shows the entirety of such a device. In FIG. 2, numeral 7 indicates, for example, a rotary two-head type VTR. As is well known, the rotating two-head type VTR 7 modulates the video signal from the video signal input terminal 81 and records it on a magnetic tape as sequentially inclined tracks using a pair of rotating magnetic heads. The signal is demodulated and obtained at the video signal output terminal 80. Further, 9L is a terminal to which the left side signal of the stereo audio signal is supplied, and 9R is a terminal to which the right side signal is supplied. This left signal is supplied to a sampling hold circuit 11L via a low-pass filter IOL, and its sampling output is supplied to an AD converter 12L. The right signal is also supplied to the AD converter 12R via the low pass filter 10R and the sampling hold circuit 11R. The outputs of these AD converters 12L and 12R are parallel codes, which are supplied to the parallel-serial conversion circuit 13 and serialized. The output of this parallel-to-serial conversion circuit 13 is written into the memory device 14. The code read from this memory device 14 is supplied to a synchronization signal mixing circuit 15. The output of this synchronizing signal mixing circuit 15 is supplied to a video signal input terminal 81 of the VTR 7. The above-mentioned memory device 14 compresses the time axis of the code to form a data missing period corresponding to the vertical blanking period of the video signal, and the synchronizing signal mixing circuit 15 compresses the time axis of the code to form a data missing period corresponding to the vertical blanking period of the video signal. The ratio pulse is added to make the PCM signal have the same signal form as the video signal. This is to enable the VTR, which originally records and reproduces video signals, to be used as is. During playback, a PCM signal having the same format as the video signal is obtained from the video signal output terminal 80 and is supplied to the synchronization separation circuit 16. Using the synchronization signal separated by the synchronization separation circuit 16 as a time base, a reproduction system tarok pulse is formed. The PCM signal from which the synchronization signal has been removed is then written into the memory device 17. The memory device 17 expands the time axis of the serial PCM signal to make it a continuous signal with no missing periods. The code read from the memory device 17 is converted into a parallel code by the parallel-to-serial conversion circuit 18, and is supplied to the DA converters 19L and 19R.
It is led to output terminals 21L and 21R via 0R. A stereo left signal appears at the output terminal 21L, and a stereo right signal appears at the output terminal 21R. In this way, by using the VTR7 to perform PCM recording or playback, there is no need to prepare a wideband signal recording and playback device exclusively for PCM, and it is also possible to transmit the PCM signal using television broadcasting and record it on the VTR on the receiving side. High-quality audio signals can be easily obtained by recording using . The present invention is used in the above-mentioned PCM recording and reproducing apparatus for audio signals. FIG. 3 shows an embodiment of the present invention, in which an analog signal from an input terminal 1 is supplied to a sampling and holding circuit 2,
A sampling output Vi is generated, and this sampling output Vi is supplied to amplifiers 30a, 30b, and 30C. The amplifier 30a has a gain of 1, the amplifier 30b has a gain of 4, and the amplifier 30C has a gain of 16. and the output V of this switching circuit 31. is supplied to a 12-bit AD converter 32. Also, the sampling output Vi is the comparator circuit 33, 34, 3
5 and 36, and is compared with reference voltages ±vr1 and VF2. The outputs of these comparison circuits 33, 34, 35, and 36 are applied to an encoder 37, and a 2-bit gain selection code is generated from the encoder 37, and the state of the switching circuit 31 is controlled by this gain selection code. That is, as shown in FIG. 4, for the sampling output Vi expressed as an analog input signal with a peak-to-peak value of Vm to -Vm, the reference voltage -Vrl of the comparator 33 is selected as The reference voltage Vr1 of the comparator 35 is selected to be , the reference voltage -VF6 of the comparator 35 is selected to be , and the reference voltage vr2 of the comparator 36 is selected to be . Comparators 33, 34, 35, and 36 have sampling outputs Vi
When the absolute value of is greater than the reference voltages vr1 and r2, an output of "0" is generated as shown in FIG. The outputs of the comparators 33, 34, 35 and 36 are given to the encoder 37, so that the sampling output Vi becomes (Vm≧Vi≧Vr1.-Vm≦Vi≦-VF1)
When the gain selection code [11] is within the range of
(Vrl>Vi≧Vr2.-vrl<Vi≦-VF6
), a gain selection code [01] is generated, which connects the output terminal of the switching circuit 31 to the input terminal, and the sampling output Vi becomes
(VF6 > Vi > -VF6) (7) When within the range,

A gain selection code [00] is generated, which causes the output terminal of the switching circuit 31 to become the input terminal C.
connected to. In this way, the output vo of the switching circuit 31 controlled by the gain selection code is converted to AD by the AD converter 32.
converted. Here, the output V of the switching circuit 31. Because the reference voltage Vr□ and the voltage Vr2 are selected as described above, this reference voltage may fluctuate slightly or the operation of the comparators 33, 34, 35, and 36 may differ slightly from the normal one. Even if it is, it will always be smaller than Vm and larger than -Vm. Then, the 12-bit outputs D1 to D2 of the AD converter 31
(Dl is MSB, D1□ is LSB) is the output V of the switching circuit 31, as shown in FIG. 5A. becomes all "0" at -Vm, and from this V. The larger the step, the larger D□~D1□ becomes.
All of D1 to D12 are "1" at Vm. The outputs D1 to D12 of the AD converter 32 are supplied to a code conversion circuit 38 to simplify subsequent processing, and are converted into codes R1 to R1□ in the form of folded binary codes. As shown in FIG. 5B, the codes R1 to R1□ correspond to 0, and the output of the AD converter 32 is only the MSB, R1, is '1' and all other bits are '0', on the + side. As R1 becomes larger, the digital output becomes larger sequentially while R1 remains at 1. Conversely, on one side, only R1 is 0, and as the absolute value becomes larger on one side, the digital output becomes larger sequentially. In addition, the + side and the one side are distinguished by R1 (usually called a sign bit), and R2 to R1□ are the same code in terms of absolute value. The AD conversion output R that forms this folded binary code
Of 1 to R1□, R□ is transmitted as is (represented by R1' in the figure), and 8 bits out of 10 bits of R3 to R1□ are selected by the switching circuit 39 and transmitted to R5' to R1□. ’. Furthermore, the three high-order bits R2, R3, and R4 excluding R1 among the AD conversion outputs R1 to R1□ are supplied to the discrimination circuit 40, and the discrimination circuit 40 generates a bit selection code. 39 states can be switched in three ways. This discrimination circuit 40 determines which bit of the AD conversion output
The switching circuit 39 has 10 switches,
Each bit of R3-R1° is applied to each input terminal of this switch, and its output terminals a, b, and c are connected to eight output terminals. The switching states of these 10 switches are commonly controlled by a bit selection code, and the switching state A is in which the input terminal of each switch is connected to the output terminal a,
There are three states: switching state B in which the input terminal of each switch is connected to the output terminal, and switching state C in which the input terminal of each switch is connected to the output terminal C. In switching state A, 8 bits from R3 to R1o are taken out as outputs R5' to R12', and in switching state B, 8 bits from R4 to R1□ are taken out as outputs R5' to R12'.
', and in switching state C, ' is R5-
The 8 bits of R1° are taken out as outputs R5' to R1□'. Note that the switching circuit 39 and the switching circuit 31 described above are digital switching circuits including gate circuits and the like that are controlled according to a bit selection code and a gain selection code, respectively. Furthermore, a range bit encoder 41 is provided with a gain selection code from the encoder 37 and a bit selection code from the discriminator circuit 40, R2' and R3'. A 3-bit range bit of R4' is formed. The operation of the embodiment of the present invention described above will be explained with reference to FIG. 6. In this embodiment, the + side and one side sampling output Vi is subjected to non-linear AD conversion in a range of 7 stages from E1 to E7. Since the + side and the one side are the same except for bit R1, the + side will be explained. First, since the sampling output Vi at a level higher than the reference voltage Vr1 is supplied to the AD converter 32 at the same level, this level V. AD conversion outputs R1 to R12 are generated according to the magnitude of . In the range E7 of this AD conversion output from 1/2Vm to Vm, since °0'' does not exist in the bit of R2, this is determined by the discrimination circuit 40 and is a bit selection code that sets the switching circuit 39 to switching state A. Therefore, in this range, the 8 bits from R3 to R1o are the output R5.
' to R12'. Next, from 1/4Vm to (1/2Vm-ΔV) (Δ■
is the AD conversion output R1 of the range E6 up to 1 quantization step)
~R12 is bit R2 and R3, only R2 is °゛0“
Therefore, this is determined by the discriminating circuit 40, and a bit selection code is generated to set the switching circuit 39 to switching state B, and the 8 bits from R4 to R1□ are outputted to R5'.
~R□2'. Furthermore, the AD conversion output R1~R1° in the range from (1/4Vm-Δ■) to the reference voltage ■r1 (part of R5) is audible.
Since both R2 and R3 become 0, this is the discrimination circuit 4.
A bit selection code that is determined as 0 and sets the switching circuit 39 to switching state C is generated, and R5 to R1□
The 8 bits are outputs R5' to R2'. In addition, since the sampling output Vi which is larger than the reference voltage vr2 and reaches Vr1 is quadrupled, the AD converter 32
A level within a range from rl (in the case of vrl-4vr2) to Vm is supplied. Therefore, a bit selection code is generated in the same way as described above for the AD conversion output of the level range quadrupled, the switching state is changed to A, B, and C, and 8 bits are selected, and the remaining part of the range E5, Outputs R5' to R1□' are generated in the range E4 and part of the range E3, respectively. Furthermore, since the sampling output Vi, which is smaller than the reference voltage vr2, is multiplied by 16, the AD converter 32 is supplied with a level within the range from 0 to Vm, and performs AD conversion in the level range that is set to be 16 times. Similarly to the above, the output R5 in the remainder of the range E3 and the range E2 is
'~R1□' occurs. Furthermore, regarding the range E1, it is detected that the gain selection code indicates 16 times, and the switching state B is maintained. The 8 bits selected and outputted by the switching circuit 39 in this manner are shown surrounded by broken lines in FIG. Also, the bits higher than the transmitted 8-bit code R5' to R1□' are always ``1'' except for the range E1, so they are not transmitted and are changed to ``1'' during DA conversion. In addition, in the range E1, the high-order bits are set to 0. As shown in Fig. 6, the gain information necessary for DA conversion is 732 times in ranges E1 and E2), (1716 times) in range E3, (178 times) in range E4, and (178 times) in range E4.
5 (174x), range E6 (172x), range E7 (1x), and ranges E1 and E2:
It is necessary to distinguish whether to add 1 or 0 to the high order, and in the end, range bits R2', R3', and R
4' is required in seven ways, and is determined as shown in FIG. 6, for example. The 3-bit range bit R2 by this AD converter
For example, the 12-bit PCM signal including ', R3', and R4' is serialized as described above, and is recorded by the VTR 7 in the same format as the television signal. The PCM signal reproduced from the VTR 7 is time-axis expanded and then DA converted. An example of a DA converter will be described with reference to FIG. 7. First, MSB R1' indicating positive and negative polarity and range bits R2' and R3'. R4' is applied to a coder 42, converted into a 7-bit output code, and supplied to a 7-bit ODA converter 43. The output of this DA converter 43 includes a range bit R2',
Six types of positive and negative reference voltages are generated by R3' and R4'. Further, R5' to R1°' are supplied to a 1-bit addition circuit 44. The 1-bit addition circuit 44 is placed at a higher level than the highest level of R5' to R1'. 1" is added, but it operates to add "0" to those corresponding to the range E1. Therefore, the range bits R2', R3', and R4' are added to the detection circuit 4.
5, and the output of the detection circuit 45 is °1" or "0".
It is determined whether to add ``. Then, the 9-bit output from the 1-bit addition circuit 44 is D.
A converter 46 is supplied. This DA converter 46 is a ladder-type resistance circuit, and a reference voltage is formed by the DA converter 43 described above and applied to its terminal 47. An analog signal appears at the output of this DA converter 46. Instead of using multiple amplifiers with different gains or amplifiers with switchable gains, the Gagaru DA converter uses
1) The reference voltage supplied to the DA converter 46 by the DA converter 43 is varied depending on the range bit. Therefore, there is no error in the amplifier and it is highly accurate. The AD converter according to the present invention described above is highly accurate and inexpensive. That is, in the above-mentioned embodiment, level discrimination is performed at the reference voltage terminals r1 and r2, but fluctuations in the reference voltage,
For example, 1/4Vm and 1/4Vm due to errors in the comparator circuit.
Even if the discrimination level fluctuates between 8Vm and the level of the sampling output Vi is quadrupled even though it should not be quadrupled, the voltage applied to the AD converter 32 will not exceed Vm. The output of the converter 32 indicates the true value, and when DA conversion is performed, the true value can be obtained. However, the required number of bits of the AD converter 32 can be reduced compared to the case where processing is performed only digitally. Generally, the price of an AD converter increases as the number of bits increases, so reducing the number of bits is advantageous in terms of making the device inexpensive. Of course, the AD converter according to the present invention has the features as the non-linear AD converter mentioned at the beginning.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional non-linear AD conversion device, FIG. 2 is a PCM audio signal recording and reproducing device to which the present invention can be applied, and FIG. 3 is a block diagram of an embodiment of the present invention. 4 to 6 are waveform charts and diagrams used to explain the operation, and FIG. 7 is a block diagram of an example of the DA converter. 1 is an input terminal, 2 is a sampling hold circuit, 30a
, 30b, 30C are amplifiers, 32 are AD converters, 33,
34, 35, and 36 are comparison circuits.

Claims (1)

[Claims] 1. An AD converter that generates an output of a predetermined number of bits,
At least an analog signal and a signal amplified by 2 times the analog signal are selected and supplied to this AD converter, and this selection is made within the range of 2 to 21□ to the above-mentioned analog signal and its maximum amplitude. This is done by comparing the output with a reference level selected in An AD conversion device configured to digitally output a certain number of adjacent high-order bits smaller than the predetermined number of bits and a plurality of range bits determined by the comparison output and the state of the high-order bits.