JPS59501232A - I/O channel bus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] TECHNICAL FIELD The present invention relates generally to data processing devices, and more particularly to data processing devices. through which multiple peripheral controllers communicate with other functional units within the overall system. The present invention relates to a sub-bus device such as this.

Background of the invention A typical computer system performs a large amount of storage for the system, Several peripherals that allow communication outside the system (hereafter referred to as "peripherals") devices). However, periph rals typically operate on time scales that are at least an order of magnitude longer than the operation of other functional units in the system. Operate. Interfacing peripheral controllers directly to the main system bus This requires a large amount of information associated with each peripheral control. typically requires an overhead of

Therefore, the peripheral Nt! Connect the I-goki to the peripheral subhas and its Intelligent I1 to control the communication between the sub-bus and the main system bus. It is known to constitute a 0-channel processor'+J (hereinafter referred to as [xocpJ)]. This is the method of To simplify terminology, we simply refer to the peripheral sub-bus. Often referred to as a "bus". Communication from 1ocp about the direction on the bus ``send'' and ``outward,'' which refer to Let us denote it with terms such as inward j for l0CP.

When a bus is dedicated to a peripheral device, the bus resources are fully utilized and all peripherals are For example, to allow reasonable bus access to Noeral 9, bus resources The main concern is to allocate the information between the various peripherals. Prior technology is bus Several schemes are used with the intention of dividing resources. the easiest Simple prior art schemes perform sequential allocation. In that sequential allocation, request Full use of the bus is allocated to each device that has next request for that bus. Before yielding to the device, set the maximum bus speed or maximum device speed, whichever is slower. is allowed to complete the data transfer in any way. Next steps in complex operations The process can be used to prioritize certain devices or In the case of a bus that is generally long, this involves grouping bus tram hinges according to their orientation. Yo Advanced and sophisticated prior art systems provide time slots to requesting devices. This takes the form of time sharing. In such a system, a given device of a timeslot, even if the device does not complete its transfer. The bus is no longer available at the end, so the transfer continues at a later timeslot. It is necessary to do so. The transfer will eventually be completed, but such Unreasonable restrictions are placed on the effective device size because the bus can be used for .

Addressing schemes are a necessary feature of any PANU system. However, such schemes may unduly increase bus costs or unduly reduce bus speeds. Considerable care must be taken to ensure that it does not deteriorate. -Special for throwing of a data destination that includes both the specified device and the actual data location within it. Addresses play a role in identification.

The most common prior art system is 1, which adds another address line to the bus and connects them to Assign addressing functions. This increases the cost of bus media.2. The ability to select individual addresses for bus operations is provided.

Other systems send address information on a data bus in a time-sharing manner. For this purpose, data In order to avoid reducing the overall bus speed even if an extra load is placed on the data section, the There is usually a need to exercise control. Reduce the burden imposed by time-sharing the data bus One way to minimize the If the transfer is completed, the next cycle is to request that the entire transfer be completed. death However, this tends to lock out short transfers while long transfers are being completed. Ru. Furthermore, if the device is slower than the bus, then the bus can use its own (faster) speed. be prevented from operating at a certain degree.

Another set of problems arises when the bus is operated bidirectionally. The data bus is whether they can transfer data in one direction (slmplex) or when they are different Is it possible to transfer data in both directions at any time (half duplex)? Or is it possible to transfer data in both directions at the same time (full duplex)? x))). True full confidence operation requires two separate data This can only be accomplished with tabas (one in each direction) and requires two sets of control lines. another The method is to create a single piece of bidirectional data whose properties are controlled so that it appears to be the perfect center of gravity. bus, but with multiple intersecting movements in different directions. 1interleaved operations) to appear at the same time. and require a control system to handle those operations. However, mixed movements Address information must also be interlaced for buses with this ability to perform operations. As a result, time division becomes increasingly complex.

Therefore, we try to make bus resource allocation flexible and efficient. This increases overhead, which is undesirable.

Summary of the invention The present invention provides an extremely efficient use of both bus medium and bandwidth. It is a tortoise that provides a high speed bi-directional data bus system.

Broadly speaking, the present invention provides the following steps to configure a system of logical transfer channels. Another set of tag lines is used from the bidirectional data lines. Data flow details In order to meet the requirements, it is attached by l0CP and is a relatively small number (for example, 4) of transfers that can be separated (datach) Channel exists. A system of logical transfer channels provides high data rates (long distances). (even if the distance is far), and performs error detection well. The basic functionality of a transport channel is , allows you to temporarily allocate the lotus resource storage portion to a specific device. , then address that device by delegating to that channel By making it easy and quick to do so.

In order for a transfer to occur between l0CP and a device, X0CP must An ``belong'' operation is first performed to allocate a transfer channel to a device while it is in use.

100p can then be assigned to the current group according to any allocation scheme desired. Allocate bus cycles to the transfer channel that is currently being used. The assignment is A device on a transfer channel can be ready to send or receive data. One implementation In the example, all devices have multiple "channels" corresponding to multiple transfer channels. Nell Reddy” line. 10CP is used for direct addressing of devices. Perform the 5-group operation, give it a channel number, and sequentially access the addresses within that device. Set the pace address for access. The device then switches to the appropriate Request a bus cycle by sending to Nell Lady Gentleman. rocp the requesting device's transfer channel. By placing a binary code corresponding to that channel on the tag line, which means respond. The device is transmitting data at or above the bus data rate. A device can be assumed to be always ready if it can operate at speed; . Once a transmission channel is assigned to such a device, it cannot send or receive data. As long as rocp knows that communication is always possible, There is no need to connect to the "Nell Ready" line.

Data transfer is performed in units of a predetermined number of bus words (e.g. four 16-bit words) "burst"). Maximum bus speed of those 4 words regardless of device speed Each bus interface can be transferred or not transferred on the bus at The chair contains a staging area that contains, or receives, the words in sequence.

The device has 4 words in its staging register and therefore cannot transmit. or its staging area is empty and you cannot receive When ready, the device asserts the channel ready line.

During bus operations defined by previous tags for data transmission, the four words Moves can be made to or from the device at the maximum speed of that bus. 4 A data transfer longer than a word data unit consists of a series of such four-cycle bursts. occur over a period of time. Generally, other transfer channels have four cycle blocks for the time being. can be assigned. Once the data transfer is finished, the channel separates from the device. and make it available to other devices.

A system of logical transfer channels must allow the bus to operate at its highest speed. while allowing each device to operate at its own speed during the transfer.

Since the direction of the data is set during the belonging operation, the direction is set by issuing a tag of 10CP. , indicating that the control overhead is further reduced. The system Easier precedence with ξ which allows channel tags to be given in any order scheme and use the same mechanism to provide the necessary flexibility and time-sharing Have them do it. By using a transfer channel, addresses can be interleaved. b) Many simultaneous transfers can easily be exchanged without the need for complex overhead. It's confusing.

Therefore, the present invention provides an ROCP with a tag that can be used by all controllers. operates according to the synchronous pipeline control sequence initiated by the next cycle. Determines the operation of the door. It performs the exchange of information and monitors the progress of that exchange. The most common type relies on the exchange of "handshake" signals on the bus to This is different from the asynchronous bus structure. The series of handshakes in an asynchronous system Monitoring the output signal is a simple task, but many such systems Unable to distinguish between one unit and multiple units. This is because a series of handshakes This is because the wake signal appears correctly in either case.

The present invention allows the l0CP to determine whether an operation is proceeding properly. The present invention provides a selection circuit for The selection circuit is a signal at each device. a signal source, a monitor at l0CP, and a common selection line to which the signal source and monitor are coupled. have The signal source is connected to an element responsive to tag and timing signals and to a select line. and a constant power source to be connected. The monitor in 10CP is a tag decoder and a voltage reference. including. At the beginning of each bus transaction, all devices examine the tag information. to determine whether a given tag is unique to an individual device. do.

Suppose a device determines that it has only one address. The device then adjusts its current source to control the select line. Therefore A certain amount of current is applied, the controller is not selectable, and one controller is selected. 10CP handles the situation where many controllers are selected and Be identifiable. When l0CP puts a tag on the tag line, l0CP sends a selection signal. Maintain a pipeline of predictable responses. Actual state and prediction of selection line The fact that the states that can be expressed do not match indicates an error in selection.

Multiple selections can be used to determine which device on the bus is selected or how many devices are selected. Since the selection circuit does not convey information about whether the It further includes a history shift register.

When a device decides how to regulate its current source, The device also stores a code representing this decision in its history shift register. put. When a l0CP detects an error condition, the l0CP is called a "lock" tag. Generates wide-area tags. The lock tag allows the IOCP to determine the source of the error. Freeze the state of their selected history registers on all controls to let The history register contains denominations (the true selection history of the chair) for tags on the bus. The history register is readable so that the history can be started again. And it can be canceled.

To provide a further understanding of the nature and advantages of the invention, the remainder of this specification and the accompanying drawings are incorporated herein by reference. See.

FIG. 1 is an overall block diagram of a computer system showing an I10 channel bus; FIG. 2A is a block diagram of one side of the ferrule controller front end; Figure 2B shows how to couple the controller front end to the I10 channel path. Block diagram, Figure 3 is a timing diagram of the clock signal in l0CP, Figure 4 is a schematic diagram of the clock input circuit in the ferry controller boat; Figure 5 is a timing diagram of the clock signal in the boat. Figure 6A is a schematic diagram of the input and output staging circuitry within the boat; Figure 6B is a schematic diagram of the output circuit inside the boat, and Figure 7 is a diagram of the tag decoding circuit inside the boat. , FIG. 8 is a schematic diagram of the circuitry within the boat for identifying register operations; Figure 9 is a timing diagram of the register write signal, Figure 10 is the attention of the boat. ・Schematic diagram of register, Schematic diagram, Schematic diagram with control register, Fig. 14 Schematic diagram of the circuit inside the boat for driving the chopper and depass; Figure 15 is a schematic diagram of the circuit inside the boat for driving the selection line, and Figure 16 is the status report of the boat. Fig. 17 is a schematic diagram of the circuit in the boat for driving the error line, Fig. 18 is a schematic diagram of the circuit in the boat for driving the error line. Figure 19 is a schematic diagram of the circuitry within the boat for decoding the board; Figure 20 is a schematic diagram of the boat's lap register, Figure @21 is the boat's side control. Schematic diagram of the registers, @22 diagram is in the boat to initiate extended mode operation. Schematic diagram of the circuit, Figure 23 shows maintenance that can be shared between two boats at the front end of the controller. Schematic diagram of the nonce control circuit, Figure 24 is a block diagram of SBA, Figures 25A and 25B show a series of signals between the SBA and the ALU of l0cP. timing diagram, Figure 26 is a schematic diagram of the clock distribution circuit in SBA K, and Figure 27 is a schematic diagram of the clock distribution circuit in SBA K. timing diagram of the clock signal, FIG. 28 is a schematic diagram of the clock drive circuit within the SBA subbus interface; Figure 29 shows the data and tag output circuit in the SBA length bus interface. Schematic diagram, Figure 30 is a schematic diagram of the input circuit within the SBA sub-bus interface; Figure 31 shows 5BA-! for selection line detection. 7-Circuit in bus interface This is a schematic diagram.

DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1 is a block diagram of a typical computer system that can configure the present invention. Ru. To put it simply, this computer system has a central processing unit (CPU) 1. 0, service processor (SVP) 12, and memory controller (MC) 13 and an I10 channel processor 15. All of those devices are system Communication is performed using a path control unit (BCU) 1B, and path assignment is performed by a path controller (BCU) 1B.

CP [JI Q is cache/TLB () Lancerion Look Asa contains an arithmetic and logic unit (ALU), and a floating point accelerator (FP). Communicate with A). Service Processor v12B’: First of 17 viewer system Perform period setting and reconfiguration. Memory controller 13 communicates with the storage device. l0CP15 is cache/TLB20, ALU22, and subpath adapter (SBA) 23.

5BA23 is coupled to two I10 subbuses 25 and 27, and the Communicate with multiple peripherals through one or both. The picture shows the beriferal 3. 0a and 30b are shown. Those peripherals are empty over large areas. Because they are distributed in between, sub-buses 25 and 27 are relatively long (probably 5σ( 15,2 m) or 100' (30,5yn)), each terminal device 31 ．． Extends to 32. Each peripheral has a device 33 (this is a tape drive, a disk drive, etc.), an appropriate device controller 34, and a set of data A controller front end (sometimes includes [referred to as CFEJ].

In this preferred embodiment, controller front end 35 includes two boats 37. (sometimes called A-boat and B-boat). Each of those boats to the sub-bus. In the case of the peripheral 30a, the boat 37 is the sub-bus 25 and 27, but this is not necessary. To demonstrate this, let's use the perif One boat of Geral 3Qb is connected to Subnox 25, the other boat is connected to another It is shown that it is connected to the sub-bus 2γ' from the Iocp (not shown). There is. In this preferred embodiment, a given V hvasni can contain up to 16 buttons. can be combined. Each boat has a switchboard so that the equipment can be numbered. A switch is provided.

Figure 2A is a block diagram showing the main parts and communication paths inside the controller 70 and end 35. be. Only one boat is shown in the figure. As shown in the diagram, each boat includes a clock receiving circuit, a data processing circuit, a control circuit, and various registers. nothing. The controller front end also includes control circuitry common to both boats. controller The front end consists of TTL logic. The structure and operation of these various parts are , will be described in detail below with reference to various circuit diagrams. The schematic diagram has been simplified somewhat. It is depicted in the form of Part numbers are indicated by abbreviations and similar designations [7 An apostrophe is added to indicate that 4sJ has been omitted.

Also, many parallel devices are presented as a single device.

The nature of each device controller 34 determines the nature of the device or devices with which it communicates. Depending on the nature of the It is the same. The controller 34 has sufficient intelligence and appropriate It is assumed that an interface circuit is included.

The present invention provides that the path cycles on the sub-buses 25 and 27 optimize path utilization. It concerns how the information is distributed among the devices. For the explanation below D. sub-buses 25 and 27 are almost the same, and furthermore, for a given controller front The two boats within the end 35 can be considered the same. Therefore, below Most of the discussion given here focuses on a single sub-bus and single sub-bus within the controller front end 35. It concerns a boat. Furthermore, the given sub-bus is converted into a 7-stem bus 1T. A given subbus is simply referred to as a ``bus'' unless it is necessary to distinguish it from I will usually call it.

FIG. 2B is a schematic diagram of the signal path on which 5BA23 and the controller Data, control signals, and timing signals are communicated with the client end 35. It will be done. For simplicity, sub-bus 25 (i.e. bus 25) and a single boat 37 is shown.

The bus 25 includes a data bus 40, a ready bus 41, a tag path 42, and a selection line 4. 3, the interrupt line 44, the first clock line 45 (TCLK), and the second clock line 45. line 47 (RCLIO), the first frame line 50 (TFRM), and the second frame line 47 (RCLIO) RFRM and an error line 53. All signals on bus 25 (select (excluding 26S10 open collector quad bus transceivers can be driven and received.

Data bus 40 has 16 data bits and 2 parity bits. include. The harness bit consists of two data bit groups (one data bit group consists of 8 bits). used to maintain odd numbered bits in each group (containing data bits). Ru. In general, the data bus parity is correct, but the ball activity described below In situations where parity cannot be properly controlled, such as during the parity data response cycle, Certain conditions exist.

Ready bus 41 includes four lines corresponding to four logical transfer channels. Block A device operating in network transfer mode can be connected to any one of four transfer channels. It can be done by belonging to the organization. If the device to which it belongs belongs to four consecutive When a four-word burst is transmitted in one cycle, the device is in the appropriate ready state. Make the line work. I OCP generates the appropriate tag in response to the request and allow that transfer channel for four consecutive bus cycles, sufficient for the transfer. bus Devices that can move data faster than their speed use readybus 41 It is not necessary and can instead be assumed to be ready due to l0CP.

Bus 42 has four tag lines, two I10 status lines, and a parity line. and is used to define the behavior of the bus. tag field ha next nova sai It is primarily used to define the It also has extensive uses.

Select line 43 is controlled by any unit in which the bus cycle is included; Therefore, either no units were selected, one unit was selected, or or provides an indication as to whether one or more units have been selected.

The activity bit is set and based on the previously distributed mask Interrupt line 44 can be driven by any device that is allowed to issue interrupts. can. The interrupt line is used for data transfer (which is the function of ready bus 41). It is not used to initiate communication, i.e., to initiate transfer. It is used for The state of that line indicates that a device requires service. Inform the IOCP. l0CP uses poll activity tags to determine which device.

The error line 53 can be connected at any time to notify the CP that something has failed. driven by any device. Preventing some hardware from functioning properly When a controller detects that its hardware has experienced a failure that causes The controller always signals the error line and records the error information in its own status register. give information. In response to the error signal, l0CP reads each device's status register. By taking the following steps, you can determine which device on the path has the problem.

Since the data bus 40 is a bidirectional path, the 5BA23 spanning board 37 I can drive. On the other hand, Tagbus 42 is only driven by 8BA23. It is. The ready bus 41, the selection line 43, the interrupt line 44, and the error line 53 are: You can take a drive by boat. Those terminals are resistively terminated in the terminator 31. Ru.

TCLK line 45 and TFRM line 50 are driven by 5BA23 and are connected to terminator 3. 1 and terminated with a resistor there.

RCLK line 47 has a pair of segments 47 (out) and 47 (in). Them The segments are connected to a terminator 31. RCLK signal is on segment 47 (out) The drive is cut off by the SBA 23, and the signal propagates from the SBA toward the terminator 31. Turn back here and follow segment 47 (in) to S B A 23″″-same. and propagate backwards.

Segment 47 (in) is resistively terminated at 5BA23. Boat 37 is Connected to RCLK segment 47 (in), but connected to segment 47 (out) Not matched.

Ft1M line 52 similarly has a pair of segments 52 (out) and 52 (in).

The segments are connected to a boat 37 at a terminator 31. boat 37 is coupled to RFRM segment 52 (in).

Since the main function of peripheral devices is to move data, the most basic operating mode is mode is block data transfer mode. Four intersecting data transfers (four (corresponding to a logical transfer channel) is performed on each sub-bus. to a certain device, or from a device, once the data transfer has started, that device activates the appropriate ready wires so that it can transfer data. Show that. The state of tough hash 42 determines what will happen on subsequent bus cycles. The device is translated and ready by the control front end as Tell the chair when the bus cycle will be stopped.

Data transfer on the bus is performed in units of four words, or in bursts. valley berth occupies the bus for four consecutive bus cycles. system bus 17 is 6 It handles 4-bit words, except that the subbus handles 16-bit words. The above numbers have no specific meaning.

The other basic mode is register transfer, in which I OCP is Write to or read from one of the device's several registers or I'll explain what that particular register means later, but for now: It is sufficient to note that these registers provide various control and state information. It's a minute. The operation of various registers is performed before a transfer channel is assigned to a device. I have to get up.

The basic timing and CFE clock receiver circuit in Figure 3 is from the 5BA23 The generated signals TFRM, TCLK.

It is a timing diagram of RFRM and RCLK. In this preferred embodiment, the support bus cycle is 250ns (by comparison, system bus 11 is 25ns (operates in cycles of s).

TCLK is a continuous pulse stream with leading edge spacing of 250 ns and bus service and the time of transfer from l0CP to device i. TCLK pulse The duration is 1 oona. For accuracy, cycle N, N+1 ．． N+2. Let us consider the data transfer that occurs at N+3. TFRM pulse is the TCL of the bus cycle (N-1) immediately before the first cycle of 4v cycle transfer. It almost coincides with the K pulse! The developer of 0On8 is born. RFRM missing from bus TFRM will not be generated again (indicating a new bus operation) until ). TCLK occurs continuously from l0CP to the time of transfer to the device.

SBi23 places data on the bus on the leading edge of TCLK and transfers it to the boat loader. SICK holds data on the bus at the trailing edge of TCLK (points A, B, C, D) do. SBA is a TCLK pulse width of 100 ns for a certain amount of time (e.g. 5 0n@) Keep data on the bus for a certain length of time.

RCLK is continuous at the same rate as TCLK until the time of transfer from device to l0CP. is generated. The leading edge of the RCLK pulse is 10 times smaller than the trailing edge of the TCLK pulse. Delayed by 0ns. RFRM follows the occurrence of TFRM and the next RCLK Hals The development of 10'On++ is possible with the same agreement.

Relative timing between (TCLK, TFRM) and (RCLK, RFRM) The configuration is different for devices distributed along the bus. The reason is that faith Although the signals TFRM and TCLK are given directly to the device, the signals RFRM and R , CLK must take a detour at the terminator 31. More details In other words, relative timing for devices placed near the terminator. is almost as shown in the figure, but for the device placed between the 10CP and the terminator. This is because the relative delay becomes large. Trailing edge of TCLK and RCLKO A delay of 100 ns (or more) between the leading edges is farthest from the I OCP. A remote device must place data on the bus and generate the appropriate control signals. It is necessary to have sufficient time to make sure that boat logic is Place the first data word on the bus at the RFRMO leading edge (point A') and the fourth R cLK.

Remove the last data word a little later than the trailing edge (point y). 5BA23 is RC Trailing edge of LK (points r, HII, Cr.

The data is held in H').

The timing of register transfer is based on two buses, for example cycles N and N+1. data bar 2 during the cycle The timing is similar to that of a data transfer, except that it only occupies space.

Cycle N-1 is a tag cycle. This tag cycle is followed by two subsequent tag cycles. indicates that the cycle should be dedicated to bus operations. Cycle N is an ID book In Le. This ID cycle A contains the unit number, register number, and register transfer. The same transmission is placed on the data bus.

Cycle N+1 is a booter from a pre-identified register during that cycle. There are cycles for reading data from and writing data to that register.

From what has been explained with reference to some assumed configurations, the signals TCLK, TFRM , RCLK, and RFRM.

As explained in the beginning of this uArA book, TCLKl (one corresponding clock) A lock signal has a signal propagation time that is comparable to or longer than the bus cycle time. As such, if it were not for the fact that bus 25 is physically long, there would be no data on data bus 40. is sufficient to time the movement of data in both directions. first clock At a given point during the cycle, the device clocks the data buffer, and then returns the response data at another predetermined point during the next bus cycle. Consider the simple case of placing it on a bus. I OCP uses this response data. It is expected that the data will be latched at a scheduled time during the next pass cycle mentioned above.

However, if the bus is physically long, the data may be lost during subsequent bus cycles before the response. l0CP can know that the data has propagated backwards to l0CP. Each device The device holds the bus data at a predetermined time (trailing edge) relative to TCLK and RCL The K signal solves part of this problem.

Propagation delays may even result in confusion in vehicle identification. 1 piece Regarding the situation where the above clock signal is transmitted on both the RCLK line and the TCLK line I'll think about it. to the device at the far end of the bus (near terminator 31) For the other hand, TCLK and RCLK are the same as in l0CP (−hill and It is in the same phase correlation school. Those signals are simply delayed by the one-way propagation time 7 along the bus. Because of this, confusion should not arise.

However, for devices closer to l0CP, TCLK appears earlier and RCL The reason why K appears late is because RCLK has to take a detour. ).

This relative delay of RCT, K is due to the fact that RCLK and TCLK support more than one cycle. This is not a serious problem until the cycle causes skew. To be so Then, following TCLK (RCLK is actually still running along the own RCLK line) The RCLK of the previous cycle is progressing as follows. This problem is due to clock speed or by lowering the speed of each device on the bus. This can be solved by incorporating a force mechanism that takes into account the position of the deer However, neither method is desirable.

Signals TFRM and RFRM are provided in a manner that avoids the undesirable practices described above. This solves the problem of incorrect identification of the vehicle. As mentioned above, the signals TFRM and RF RM prevents more than one frame from being on the bus at any one time. The frame cycle is controlled in two ways. At the same time, Fixed clock cycles are used to move data. This system is complete (all timing and reference elements are 10CP) It is sourced from the main clock and is therefore referenced to that main clock. This is it changes in the data as it is being sampled or evaluated. This helps prevent any metastable data states caused by.

FIG. 4 is a schematic circuit diagram of the clock signal circuit 58 in the boat 37. TCLK, TFRM, RCLK, and RFRI4 are each sent to the receiver 60. Receiving Outputs of signals TCLK, FCLK, RFRM are inverted and non-inverted buffer 62 and gives positive and negative local signals Sat TC, Sat RC, and Sat RF. receiver TF The outputs of RM and TCLK are given to AND and NAND gates 63, and ±T A local signal ±TF that is more closely synchronized with the C signal is provided. TCLK receiver output is also delayed by the delay circuit 65 to generate the delayed local clock signal -TC. It becomes D. The signal -TF is a local frame gated and delayed by -TCD. TFD on the system signal. Figure 5 is a timing diagram of the above local timing signal. be. Even if a positive signal and a negative signal are given, this diagram shows only the positive signal. It's fully shown.

1 shows a logic diagram of a data handling circuit.

This circuit includes an input circuit 80, an input data staging circuit 82, and an output data staging circuit 80. includes a data staging circuit 85 and an output circuit 87. Same 75: Against IQCP The general rules shown in ``Manpower-(.

It should be noted that the term "output" is used backwards. More details below As explained, for data transfer, the tag decoding circuit uses the signals -XW, -XR. The data transfer takes four cycles (4 words) (93) and (95) including. Lines shared with other boats are marked with an asterisk (*).

Data input circuit 80 includes receiver 100, latch 102, and parity check. circuit 103. Lunch 102 is an internal data port 105 (indicated by LDIN). Ili is controlled by the +TC signal in order to place data on the signal →-The launch 102 is continuous up to the trailing edge of the TC. At that point, LDIN line 10 05 Kurka on the line: Can be held for as long as it lasts. Transparent force 1 etc., register Incoming data can be sent to a control circuit for operation (described below), and This gives the ffl control circuit an additional amount of time to decode the data. DIN l 105K is coupled, and its data output terminal is connected to the XDATA line 90. be combined.

The mink is taken. The control circuit includes a counter 115, the output of which is a register file. Control the file address. The data on LDIN is at the trailing edge of +TC. is held in the register file, and the number: p? i - increased at the trailing edge of TCD Canada? be given The counter 115 is reset and incremented by a flip-flop 117,1. 18. The data input terminal of clip 70 and tube 117 has tag decoding. Given the control signal generated by the circuit, the flip 70 tube is -TF. The clock is clocked by the DO trailing edge. In this way, TFRM (actually −T FD) is combined with the appropriate tag to load the register file 110. during which TCLK times its loading. register The transfer of data from file i10 to the controller is performed under the control of the controller; What sequence and speed is appropriate for the controller? and at any speed. Therefore, one of the lines 93 is a register. Controls the ``awatogood'' enable of file 11Q so that address line 92 is Control the dress.

Output data staging circuit 85 includes an array 120 of 4x4 register files. include. Its data input terminal is coupled to the XDATA line 90, and its data output terminal is coupled to the XDATA line 90. The terminal is coupled to line 122. Those lines 122 are DOUT.

It is indicated by POUT.

Data is transferred from the controller to the register file 120 using the register file 11. Similar to the data transfer from 0 to the controller, the control is performed by the controller via connections 92 and 93. I can control it.

Addressing of the output of register file 120 is obtained from RCLK and RFRM. It can be controlled and timed by the signal. This control circuit includes a counter 12 Contains 5. This counter 125 is incremented by +RCO trailing edge. ) to be awned. The reset operation of the counter 125 is performed by the Noritsubu flop 127. You can control it. This flip-flop receives a control signal -X at its data input terminal. R and is clocked by the leading edge of →-RF. Same clock input and same device Frisoffuron 1128, which is subject to all human power, occurs on the +HOLD 'M' . This signal appears at the leading edge of the RF, and the counter 125 registers 4+j cycles. is removed when counting.

The output on line 122 is output to output circuit 87. (shown in Figure @6B).

Its output circuit includes an output latch 130 and a bus driver 132. One set of output data The data line 133 (denoted as RDATA) carries the output data. Send to Latte 130. Several control registers (collectively designated 134) ) It can be coupled to the MorDATA line 133. These registers are explained below. I will clarify. The control and timing of its output is better than the linear case of input latch 102. is also somewhat complicated. More specifically, if transfer is in progress (+HOLD is asserted) ), the latch 130 remains open. Clip flop 135, 13 1 gates the bus driver 132. Click Flop 135 is gated at the leading edge of +RF and remains dry during the 94 cycle transfer. 132 is kept enabled. 10 HOLD signal resets flip 70 togg 13γ but when +HOLD is removed, the next trailing edge of -RC will have 7 lips. Can set 70 knobs 137. The gate to the driver is then closed.

Therefore, at the trailing edge of +RCO (actually delayed by a certain delay time of the gate) ) the last data word is removed from the bus. Therefore, slightly earlier RCLKO At the trailing edge, the data on 5BA23 are relevant and briefly mentioned above. Determine which bass larvae to perform in the next cycle or group of cycles. The state of the tag bus 42 is used for this purpose. Definition of tags and various types of tag buses Control i No. o=Humoex for the hexadecimal state is shown in the table below.

Hexadecimal code Tag definition Control signal 0 No action 1 Mask Cent -8M 2 McTivity Ball - POLL3 Register operation - REGOP 4 Lock -L OCK 5-B Not assigned C-F Data transfer -XR, -XW IOS bits to further define how the controller uses the tag bits. is used. Butterfly in normal operating mode, both IOS bits are zero ( high level on actual bus lines). In this case, the tag tag is usually attached to the upper garment. field is interpreted. IQS i performs two extensions. in their extension In addition, the tag field conveys the affected unit address of the peripheral controller.

1 to put 1 in the unit control register of the controller front end. Two extended modes are used to enable the receiver and disable the driver. (i.e. to have the boat "removed" from the sub-bus) is used. The tag field in expanded mode will be used in subsequent cycles. Unlike normal operation, where the tag defines the activity that should occur on the current bus. Describe the activities that should occur during the cycle.

FIG. 7 shows a circuit 150 that decodes the tags and IO3 signals present on the tag bus 42. Illustrated in a schematic diagram. This circuit includes a receiver 152, a parity check circuit 155, and the original decoding circuit. When comparator 157 and decoder 160 are in normal mode, The tag information is decoded and the result is sent to flip-flop 165. 70 flips Block 165 is clocked at the trailing edge of -TF and outputs the control signals shown in the previous table. give. This shows how to use the TFRM signal to verify the tag signal It is something. The IO8 line can specify extended modes for a particular unit. Comparator 166 provides a control signal +OSO indicating that. For this, please refer to the shared This is discussed below in connection with the maintenance controller.

Register operation (tag = 3) transfers control information on the data bus to one of the boat's registers. transfer to or from that one register. A certain register operation is , occupies the two bus cycles immediately following the cycle in which the tag is generated. those rhinos The cycle includes an explanation (tefinition) cycle and a register transfer cycle. You can give it a name. The data bus is connected to the boat's unit identification field. , describes the register identification fields and orientation flags of the associated registers. Communicate during the cycle. The data bus transfers register data during register transfer cycles. convey.

Figure 8 shows how to decode the information placed on the bus during the explanation cycle to determine what to do. 1 is a schematic diagram of a circuit that determines the register operation of the circuit. This circuit uses the registers shown in the table below. can be operated to read from the boat to the bus. The table below shows the results caused by this table. Also shown are the corresponding control signal mnemonics.

Register control signal Lamp others - RDWRAP, THEM themselves clamp - RDWRAP , US type -RDTYP] 1m Pointer -RDPTR Status -RDERR The circuit of FIG. 8 can also be operated to load the following registers from the bus.

Register control signal DMA Address and Control -XLDLO/-XLDHI Attention -WA TTN End state - WESTAT Side control - WCTL During the description cycle, all devices on the bus scan the data lines to determine which device determines whether the device is the target of a register operation. The comparator 170 4-bit unit identification field, 4-bit UNIT command from switch Compare with the code. Gating circuitry 172 detects the orientation flag on the data bus. and reads the register from l0CP during the subsequent (register data) cycle. Determine whether to write by 10CP or 10CP. each decoder 1 75 and 180 detect the register identification field on the data bus and identify the register. generates appropriate control signals for reading and writing data.

The timing of the register operation control signals requires some explanation. First, the register During operation, i.e. during the tag cycle and again during the explanation cycle, TFRM is Note that it will be aborted twice. Read register during explanation cycle A signal from gate network 172 specifying -TF is clocked at the trailing edge of -TF. , - a signal that remains operational until the next trailing edge of the TF (i.e., until the next scraping motion). No.-Hcp is generated.

Certain register read control signals remain asserted for similar periods of time .

The timing of register write control signal failure is also complex. – Transmitted at the trailing edge of the TF. No. -RGW is asserted and the start of the register transfer cycle occurs next to +TC. At the leading edge of the signal -RGW is clocked to gate 182. Gate 182 is also controlled by -TCD, so the leading edge of -TCD (after 50na) , the output of that gate becomes higher. As a result, the flip-flop 185 Clock the error signal 10DPE to full L and low level. is allowed to enable decoder 180 on the next trailing edge of the TC. So A specific register write control signal is asserted from 50n8. It can continue until -']'CD is removed afterwards. Figure 9 shows those control signals. This indicates the timing for

CFE - Register and Tag Description The tags that are generated and the logical transfer channels between the l0CP and subordinate boats are described below. Describes the registers that are accessed to initiate and conduct communication through . The explanation concerns the circuitry within the controller front end (mainly within the slave boat). and assume that l0CP has sufficient intelligence to perform the actions described. do. The basic sequence of tag 2 and bus operations can be outlined as follows.

1, l0CP sets the active channel word to the port address in register operation. Transfer to tension register. Active channel words should communicate It carries information that tells the controller what to do.

2. When the controller decides that communication should take place, it sends a 64-bit mini Compose a message, remember it, and write the 15-bit address of that mini-message. into the boat's pointer register. An interrupt is made for this purpose. "Cha Mini messages that can be specified as ``receive on funnel'' or ``receive on funnel'' are Contains the 24-bit address of the tsage space and the sofa length.

3. To determine which device is driving the interrupt line, use l0C P generates a ball tag. The ball tag specifies wide area channel operation.

In its channel operation, all controllers respond during the same bus cycle and Provide activity status information to IOCP.

4.10CP may communicate with a particular boat according to any preferred type it desires. Decided to set the pointer of that boat in the register operation. ・Read register. This eliminates interrupts.

5. In order to read the mini-message, l0CP uses the boat's DMA address and A transfer channel is assigned by writing to the control register. while doing that , l0CP assigns a transfer channel ID, and the transfer uses the address previously read by l0CP. You should start at address 2 and transfer from the controller to the pointer register. Specify the location.

6. The controller loads the address that l0CP loads into the DMA address register. Staging register file 120K row outputs 4 words starting at (i.e. it loads the mini-message). Once this is done the controller sends the ready line corresponding to the assigned transfer channel to the boat. Make it assert.

7. l0CP generates a data transfer tag corresponding to the transfer channel to which it belongs. Ru. During the next four cycles, the controller controls the parts associated with the data handling circuitry. As explained above, the contents of register file 120 are clocked into the data buffer. put it on the bus.

8. The 10CP that received the mini-message separates the transfer channel and sets the mini-message. continue to operate based on the page.

9. Assuming that block data transfer is performed, l0CP is the available transfer Any transfer channel (used first for mini-message transfer) A broken transfer channel may not necessarily belong). New transfer channel At point 4, start from the address given in the mini-message. to specify that the transfer should be made to the controller.

In order to receive 10 consecutive communications, the controller inputs an input staging register file 11. Clears 0, drives the ready line, and transfers the 4 words of communication to the bus during 4 cycles. Indicates that the transfer is a monkey.

11. In response to the ready signal, the l0CP responds to the transfer channel to which it belongs. 4 words of data (“burst”) during the next 4 cycles. (named) on the bus.

12 Repeat steps 10 and 11 as necessary to ensure a complete data transfer. I'll give it back. The transfer channel remains attached, but other bus operations are blocked by 4 cycles. Commonly occurs among Tsuku.

13. When the entire transfer is finished, the IOCP writes the termination code to the end status register of the boat. data, and removes the transfer channel from belonging to the transfer channel.

The various registers and support circuits are then operated in sequence A outlined above. They are explained in the order in which they are called. In some situations (debug instead of l0CP) Under circumstances in which the transfer can be initiated by the The sequences may vary, but the above sequence illustrates all the relevant principles. . The sequence of events that occur before a transfer channel is attached is - apparently: Although it seems to represent sufficient overhead, one page of data (typical system (in systems) there are 256 8-byte words or 1024 bus words. It should be remembered. Therefore, there are 66 1024 paths taken in the transfer. Compared to long cycle (256 burst), set amp cost is relatively negligible. No.

FIG. 10 is a schematic diagram of attention register circuit 200. Broadly speaking, that The circuit registers the 05 upper register on the LDIN line 10 in response to the -WATTN signal. Data is sent to the data vehicle A to the control line 205 of the li (to the controller). for that, The circuit includes a clip-flop 207 whose data input is The power terminal can be connected to the LDIN line 205, and the data output terminal can be connected to the control line 205. It will be done. Flip-flop 207 is clocked at the -WA TT NO trailing edge. Ru. This =WATTN signal also sets the flip-flop 208, and the signal ATTN Send N INT to the controller. The output buffer of the clip-flop 207 is It can be enabled by the signal RD ATTN from the controller. flip flop 208 can be reset by the signal INT CLR from the controller. control line 20 The actual meaning of the active channel word with a clock point on top of the It is related to the architecture of the data system and is not part of this invention. l0 Is the CP a bad message from the controller? and hope to establish full communication It is sufficient to note that the active channel word contains information representing It is.

FIG. 11 shows the pointer register circuit 210 and the circuit for driving the interrupt line 44. 2 is a schematic diagram of the associated circuit 212. Broadly speaking, circuit 210 is -RDPT Sends information on control line 205 to RDATA line 133 in response to R no assertion. , the interrupt drive circuit 212 is operated. This circuit is a flip-flop 213 The data input terminal of this seven lip-flop is coupled to a control line 205, The data output terminal is coupled to the RDATA line 133. Is the information on line 205 a controller? The output voltage of the flip-flop 213 is clocked by the signal LDPTH from the flip-flop 213. The 7a is enabled by an abduction of -RDPTR. by the controller The assertion of LDPTH is made by also resetting the slip-flop 215. Take one length of No.-RKQINT. The Noritsubu flop is set and − -REQINT is removed by RDPTR.

- The state of REQJNT is confirmed by the 7-rip 7O-ring 217 at the trailing edge of -RC. It is pressed and forms a port activation bint. the activity is the signal generated by the mask circuit (explained later) - (NTA) gated by The interrupt signal is connected to a flip-flop at the leading edge of +RF. It is clocked by loop 220 and returned to path driver 222. that password The output terminal of the driver is coupled to an interrupt line 44 .

Figure 12 shows how the IOC is used to determine which device drives the interrupt line. 2 is a schematic diagram of an activity register circuit 230 that provides the information needed by P. . The activity registers are actually pseudo-registers, and each port has a Controls only one fixed data line. The specific data line controlled is a 4-bit Determined by unit code. The unit code is - Acuna I Bi Te As long as bits are set, the corresponding one of n (6 bits + S) As an address input to a read-only memory that generates an active level on a bit. Given. The read-only memory is enabled by assertion of -POLL. be bullied. -POLL is the activity ball tag ( tag-2). Ball tag is a wide area channel operation that The activity of all controls changes according to their focus state. By controlling these dedicated bits, those controllers can be respond.

FIG. 13 shows the lower DMA address register circuit 240 and the upper DMA address register circuit 240. 24 is a schematic diagram of a control register circuit 242 and a common multiplex circuit 245. . Broadly speaking, DMA! The li control and address registers have two register writes. Can be loaded while loading. As a result, the transfer channel belongs to some 24-bit address for controller hardware as well as control signals give.

During the first register operation of the two register operations, the lower DMA address information is loaded into counter array 250. This force is applied to the load input of the input array 25a. The power goes low when -XLDLO is asserted and the LDIN line 105 is -XL　D'L　O The trailing edge cherry is loaded. -The trailing edge of the XLDLO is It also forces the code input high, but only after a flip 70 x 12520 delay ( Go to Nine. After that, 1, the 'signal a part JB [' +, (power) of the control temple Assertion l: ・Niku 9 Kara, Nto 1'6B increased by 710 , I can beg.

During the second of the two register operations, the 8 bits of upper and lower address information are , is loaded into counter array 255 in a manner similar to that described a moment ago. . Similarly, 8 bits of control information are clocked by flip-flop 257. (Actually, this embodiment requires only 5 bits of information). So These are determined by the 2-bit transfer channel code XID, tag decoding circuit and controller. The two signals used are XIN, X0UT and the transfer channel is active. This includes a signal CHACT indicating that the -By WESTAT's Abduction 7 lip-flop 257 is reset to read XID and CHAC, among other things. Make T zero. A control signal is sent when the upper address and control # information is loaded. Since a signal is generated, the lower information is loaded in the first register operation, and the upper It is unavoidable to have the information loaded during the second register operation.

The 16-bit output from the counter 250 and the 8-bit output from the counter 255 are , to one set of input terminals of the multiplexer circuit 245, and outputs from other boats. Force is applied to another set of input terminals. Therefore, from which boat the controller is The 4-bit addresses 1, 2, 1, 1, and 1 are used selectively.

Once a transfer channel is affiliated, 4.2: its affiliated channel The controller decides whether to assert the ready line 'fi(', r) corresponding to VrlD of FIG. 14 is a schematic diagram of one circuit for driving the ready bus 41. Ru. 4 consecutive passthroughs with appropriate staging registers transmit 4 words After confirming that reception is possible, the controller sends the signal BRBQ ( burst request). Controller operates asynchronously with respect to path timing BREQ can be asserted at any time relative to the pass clock signal. 2 BREQ is sent to reset 1, 2, and 62 of the 7 lip 70 knob 2 field. It will be done. When the flip-flop 260 is reset, the flip-flop 265 and The signal BRDY applied to the input terminal of the gate 267 performs a one-length operation. . The output of flip 7 tip 265 is also sent to gate 267. That gate The output of enables selector 268. That selector is Readypass 41 Give the signal to drive the appropriate line. Those signals are connected to the output flip-flop 271Jh is sent to the ready bus driver 272. flip flop 26 5 is screwed at the trailing edge of -RCO, and the output flip 70 knob 210 is connected to +R Front edge of F. I get pricked. Therefore, the +BRDY signal follows the −RC transition. Even if the signal is unstable, the slip 70 knob 265 will be removed by the next leading edge of +RF. The readybus driver is enabled until BRDY becomes stable. will not be ignored. Similarly, when +BRDY is removed, wait until the trailing edge of -RCO. Without need, the ready bus reflects this at the next leading edge of the ten RF.

The l0CP response to the ready line being driven is the data transfer tag (tag - C, D, E or F). The tag decoding circuit 150 is a data transfer circuit. Controls data staging circuitry in response to sending tags - Assigns XR or Ichiran start. Assertion of either of those two signals causes a flip-flop 260 is clocked, thereby providing the signal BSTART to the controller, +B Remove RDY. Similarly, if -XW or -XR is removed, 7lips 70 Tube 262 is clocked to provide signal BEND to the controller.

FIG. 15 is a schematic diagram of the circuit for driving select line 43. a certain button The signal from the tag decoding circuit indicating the granting of a bus cycle to the -J and sent to flip 70 tube 280.

Its Noritz flop 280 is clocked at the leading edge of +RF and the signal -0U Assert RBUS. Current source 282 is coupled to select line 43 via a diode. be done.

-0URBUS is input to pants 7285. This back 7285 is -0 Sinks current from power supply 282 when URBUS is not asserted. -0U Assertion of RBUS directs the current source to the select line.

Data transfers and register operations are unique to one port on the bus. Since there is only one boat current source for data transfer tag or register operation. In response, select line 43 should be driven. For multiple selections, 10CP is determined. This means an error condition that can occur.

FIG. 16 is a schematic diagram of status register circuit 290.

This circuit 290U has an 8-bit history shift register 292 and an 8-bit history shift register 292. Error buffer 293 is included. This buffer 293 is used for register operation. It can be read by asserting RDERR. History register 2 92 receives 100URBUS at the data input terminal and clocks at the trailing edge of -RF. It will be done. When the tag decoding circuit asserts -LOCK, 7 lips 70 tubes 295 Avoid setting and freeze the shift register 292. Lock tag (tag-4 ) is a global tag that does not use the data bus, but rather all boards on the bus. Freeze each history shift register. This allows you to continue In register operations, l0CP is not allowed to read the state of all boats. Which boat drives the select line when it should not have driven the select line? Decide on the amount. In a given boat - RDERR cuff - can be placed , the history shift register of that boat is "unfrozen".

FIG. 17 is a schematic diagram of a circuit 300 for driving error line 53. This is The controller asserts any one of the four unit error signals (UE1 to UE4). This occurs when the tag parity check circuit 155 starts the signal -LTPE. (Latched tag parity error) or The parity error check circuit 103 outputs the signal -LDPK (parity of latched data). error), or at that time the output circuit asserts the signal -LIPE. internal parity error). These various signals are It can also be input to the buffer 293 in the star circuit 290.

FIG. 18 shows whether the boat should be allowed to drive the interrupt patcher 44. 3 is a schematic diagram of a circuit 310 that makes decisions based on distributed masks. set mask master tag (tag-1) specifies overall channel operation. In that case, this tag All controllers are accessed during the same subsequent bus cycle. Each boat has a data line One predetermined data line determined by the UNIT code is read. Each boat is , its activity mask bit is determined by the relevant bit on the data bus. set and thus used by circuit 212 to assert -INTA. to determine whether it is appropriate to drive the interrupt line. .

! FIG. 19 is a schematic diagram of the edge status register circuit 320. Broadly speaking, circuit 32 0 controls the LDIN line 10 and 05 in response to the -WFSTAT assertion. Send to line 205. This circuit includes a Noritub flop 322. this flip Flop 322 has its data input terminal coupled to LDIN line 105 and its data input terminal coupled to LDIN line 105. A data output terminal is coupled to control line 205 . Noritsub 70 Tube 322 is -WE It is closed at the trailing edge of S'rAT. - WIESTA, T signal has a flicker. Flop 325 is also set to send signal DONE to the controller. flip 7 The output cover sofa of 0 knob 322 is enabled by the signal RDESTAT from the controller. Fall into a bull. The signal is passed through flip-flop 325. -WaST By resetting the Noritsu flop 257 to the AT signal, the transfer channel is Also performs separation. The specific completion code written to the end status register is Give relevant information.

In addition to the registers and control circuitry described above, the controller front end includes additional registers and Contains control circuit. Their additional registers and control circuitry are generally Since they are not used in this field, detailed explanations about them will be omitted.

Figure 20 shows the flow through one boat or through another boat in the front end. Therefore, l0CP can read the lower DMA address written to the certain boat. The WRAP registers 330 and 332 are shown to enable the data processing.

Figure 21 shows that various parity values can be set by writing to the control register during register operation. Schematic diagram of side control register 335 that allows l0CP to clear the error signal. It is.

Figure 22 shows how to decode IO8 in each boat and use special functions (extended mode). 1 is a schematic diagram of a circuit for asserting signals -Fl, -F2 indicating . IO8 line is connected to decoder 336. The output terminal of the decoder 336 has signals -Fl, -F2 appears. One extended mode (maintenance write to -F2, or or “removal” for -Fl) is performed only under special conditions, and Particularly profound consequences arise because of this.

Therefore, for example, during a power transition, both -Fl and -F2 are falsely activated. A specially timed protocol is given to prevent It will be done. For that purpose, TFRM (signal that is not actually gated + RAWTF) decoder 336 is enabled until Not be left behind. The counter row 337 counts +TC pulses (at 250 ng intervals). 1m11 intervals every 12 bits. +RAWTF assertion The counter clear is released (as long as +O8O is asserted), + Once RAWT F becomes active for 1ms, the output of the counter is gated by +RAWTF, enabling decoder 336. correspondence After a time delay, the output of the counter changes, thereby hitting -F1 and -F2. erase. Data IO8 and tags are invalidated during this transition due to maintenance writing. It has to be true. As explained below, the signal -THIS allows selection.

FIG. 8g23 is a schematic diagram of the shared maintenance control wholesale circuit 340. This circuit is l "Removing" a boat from a sub-bus with 0 CP or maintenance Extended mode signal - Fl, from both boats to allow operation to be performed. -F2 (indicated by -F1, A, -F2.A for boat A, and -F2.A for boat B; and μ-F1. B.

-F2. (denoted as B). Circuit 340 includes a receiver control flip-flop. Including drops 342a and 342b. Those 7 lip-flops are each To control the receiver in the boat, each signal pair ±IN, A and SatIN, Give B. This circuit includes driver control slip-flops 345a, 345 Also includes b. :FNia'L et al.'s 70 units are dry in each boat. To control the bar, give respective signal pairs ±OUT, A, ±OUT, B. I can do it.

- 10 CPUs, 2 due to assertion of F2 (F2.A or F2.B) send maintenance commands using one of the data subbuses of the flip-flop 342a-b and 345a-b. both twos The input data line from the bus is connected to multiplexer 350 at the $1 level and to the second level multiplexer 350. The signal is passed to the level multiplexer 352. Multiplexer 350 is one Make a selection from one sub-bus or the other sub-bus and make a multibreak 352 Allow to influence the desired boat. The need to perform two levels of multiplexing is Which sub-bus in the boat to be controlled is on?1. /' Do I　O The CP knows which boat in the controller front end is connected to its subbus. This problem arises from the fact that the IOCP does not know what is happening. Maru In the selection of the multiplexer, the A boat car's signal -THIS (-THIS, A) It is done more.

For maintenance writes, bits (0-2) control the input and bits (4 ~6) controls the output. Bit (8-1?) written to flip-flop 355 be caught.

The flip-flop 355 is a maintainer that provides the control signal for the controller itself. form an ence register. Bit (0) active indicates that the input function should be performed. and not: Specify. Focus() active is a receiving boat〃: its own input machine bit (2) active indicates that no other boat can enter it. Specifies what a power function should do. Output functions are treated similarly to . -Clocking of the clip-flop occurs when F2 is removed.

The assertion of -Fl (-Fl, A or -Fi, B) indicates that the boat should be removed. It means to come. This mode does not use a data bus and uses flip-flops. Use the -F1 signal for direct control. To be more specific, -Fl's 7th operation of the driver coupled to the subbus is disabled. , force the receiver to be enabled.

10CP - Overall operation The above description of the controller front end is used to transfer data blocks. About the logic required to support a system of logical transfer channels That's what I did. As explained above, what is shown as a "mini-message" The peripheral controller communicates with l0CP15' by passing a configured message. believe l0CP　U, by using the above block transfer mechanism Which page reads the page and requires the controller to be executed by the IOCP? Determine whether the behavior is as follows. Once the requested action is completed, the appropriate stylized By writing a status word to the end status register 320, the IOCP tells the controller that Let me know.

The above command order should be issued, and the subbus should be driven and its subpath l0 with sufficient intelligence to decide to have equipment for detecting earth signals. The explanation given makes no assumptions about l0CP except that CP15 has I haven't. As outlined earlier, l0CP15 is a cache/TLB 20 and ALU22. Cache/TLB20 and ALU22 are both C Configure PU. This CPU has peripherals coupled to the sub-bus that Monitoring operations and messages that allow communication with devices connected to the system bus. Able to perform paper handling tasks. I　Details about the structure and embodiment of CPH of OCP The details are outside the scope of this invention. In this preferred embodiment, the CP of the I OCP U is a 64-bit ECL microprogram with a cycle time of 50 ng. It is enough to note that it is a high quality processor.

cBA23 is more directly related to the present invention and is not detailed in detail. This will be explained next.

The 5BA23 uses a 64-bit interface to communicate with the 10CP CPU. connected to the chair. Broadly speaking, SBA23 uses 64-bit words from l0CP. When received, the 64-bit word is combined with 16-bit data to be sent to the sub-bus. and accompanying control information. When receiving 16-bit data from the sub bus, SBA The ALU assembles 16-bit data into 64-bit words and searches the data. signal.

FIG. 24 is a block diagram of 5BA23. 5BA23 has each subbar. connected to sub-buses 25 and 27 via bus interfaces 350 and 352. , a 64-bit word (72 bits with parity) from the ALU is input to the Latte 355. 64-bit word (no word) input, output latch and multiplexer 357 72 bits with an ID). The SBA has local storage 360 and control storage. 362 included. Information from the ALU can be loaded into those storage devices.

The local storage device 360 provides eight transfer channels that can support EliBA. 2-word data buffer for each channel of the bus (4 channels on each of 2 subbuses). transfer channel on each of the two subbuses. and a table giving the preferred regime for length-visibility. Two for each transfer channel The problem is that the byte alignment from the sub-bus is what the ALU is aiming for. This is because it does not need to match.

The sub-bus interfaces 350 and 352 have respective sequence v310 , 372 and their respective control storage data registers 375, 377 are combined. I will be forgotten. The basic functionality of the sequencer is to retrieve the appropriate Transfer 2 bytes to each subbus interface, or Place the two bytes from the subbus interface in the appropriate location in local storage. It is to transfer to. Sequencers 370 and 372 are specified by the ALU. Handles a limited number of instructions and is related to the movement of timing data to and from subbuses Frees the ALU from any work it does.

The bits in the word from control store 362 are used by the sequencer and subbus interface. Provides the necessary force control signal for the movement of the ace. Control storage data register 375 , 377 from the control storage 362 to store such control signals. give. The local storage device 360 and the control storage device 362 are out of phase with each other. With two sequencers operating in a state of . The sequencer 370 and sub-bus interface 350 are referred to as the "A side". The sequencer 372 and sub-bus interface 352 are called the 1B side. Bu. Their names correspond to the A boat and B boat in the controller front end. do not have to.

SBA has 8-deep channel FIFO tack 380, in which the forwarding channel number is Writing can be done in the order in which the screws are removed. Subbus interface 350°352 section Except for 3BA, 3BA can be configured with ECL logic because relatively high speed is required. It will be done.

The flow of data and the overall operation of the SBA is, firstly, the transfer from the ALTJ to the subbus. (for example, to write from memory to disk) and the second transfers from the subbus to the ALU (for example, reading from disk to memory) This can be understood by considering the action of Nodame.

When the ALU decides to start a transfer, it determines the orientation, transfer channel address, Inform the SBA of the response and offset. ALU is its cache holds the first 64-bit word from the input latch 355 and makes it available at the input latch so that ALU writes channel address and first word to peripheral controller This first word gives the SBA an opcode: , two locations in local storage 360 that are dedicated to this transfer channel. channel address all channels PIF038 0 to alert the transfer channel ready flag to the ALU. (at this time Note that the first word is not transferred to the sub-bus. ) The ALU checks the transfer channel reso flag and reads the channel address. Then, use this channel address to specify the location of data that is multiplexed in the transfer. index the channel control word to be used. The ALU receives the next fetch the word, make it available in latch 355, and check the SBA. channel address and an opcode that specifies the write to the peripheral controller. e).

The SBA dedicates one of two local storage locations (3600) for its transfer channel. Store the second word in the second location. SBA is the sequence described above. 8 packets to the subbus in four consecutive subbus cycles according to A) is sent to 1.

Depending on the byte offset, the 8 bytes are the first of two local storage locations. Part or all can come from one place. After 8 bytes have been transferred, SBA places the channel address on the instep of channel PIF0380 and transfers the Assert Nell Lady Flag.

As mentioned above, when the ALU examines the transfer ready 7 rasog, the channel address Read the channel control word, index the channel control word, and search the next word from that word. and sends this word along with accompanying control information to the SBA. SBA is next store the word in the first local storage location and transfer the 8 bytes as above. . On subsequent transfers, it alternately scans words from the ALU into the first and second locations. Toa.

In order to transfer from peripheral to IOCP, ALU goes to SBA and transfers to Such transfers can be performed by informing the channel address, byte offset. and specify the transfer channel address and read from the peripheral controller. code to the SBA.

The SBA transfers 8 bytes from the controller on the subbus to four subsequent subbus sizes. store the 8 bytes in the first local storage location, and Put the channel address into the channel FIFO and set the transfer channel ready flag. assert.

ALU examines transfer channel ready flag and reads channel address index the channel control word, transfer channel address, and peripheral controller An opcode specifying reading from the SBA is given to the SBA.

Then SBA transfers 8 more bytes and stores those 8 bytes locally. Store the channel address in a second location in storage 360 and write the channel address 380 and asserts the transfer channel ready flag.

The SBA that looks up the channel address at the head of the FIFO will Read the appropriate 8 bytes from two locations for Transfer to multiplexer 357. The ALU reads the channel address and sets it to indexing the channel control word using Give it to its cache. Then, the ALU transfers the transfer channel address and an opcode specifying readout from the controller to SBAK, and perform the above operation. Repeat the work. SBA, as in the case of l0CP to controller transfer , stores 8 bytes from the subbus alternately in the first and second locations.

Figures 25A and 25N are timing diagrams of control signals passing between ALU and SBA. This shows a series of events for the two transfer directions described above. Them The gap shown in the event indicates that a 64-bit data transfer on the subbus will occur within that time. Show what happens in

l0CP-Clock generation FIG. 26 shows how various clock signals are connected to the sequencer 370, 372 and the sub-bus interface. 3 is a schematic diagram of the circuitry within 5BA23 that feeds interfaces 350 and 352. this The circuit uses various 50NA, 250NA clocks that define sub-bus timing. Operates to generate a signal. Those clock signals are system-wide clock signals. The basic 25n that defines timing is also derived from the clock signal.

Complementary system clock signals +5YSCLK and -8YSCLK is gated in circuitry 400 to provide a complementary 25 ns clock signal. Generates GCLK, -GCI, and K. +GCLK is sent to counter 402.

This counter is a frequency-divided signal, specifically a 250ns signal + REF 0 and a 5Qns clock signal +(A/B). those signals are It is sent to two sets of circuits corresponding to the 5BAOA side and B side. Here, we will consider one set of circuits. I'll just explain. The subscript ",A" indicates the timing signal on the A side, and the subscript ",B" Let us show the signal on the B side.

REFO is sent to a series of cascaded flip-flop stages 405. the The series of flip-flop stages is clocked by a signal derived from -GCLK. A clock signal group 401 of 250 ns is generated. The signal 401 has four subgroups (+ TO1,A, +TO2,A, +TO3,A), +R1,A, (+T21.A.

+T22. A, +T23. A), and 10R3,A. Those subgroups are , 25nI+ increments. Timing of signal group 407 A diagram is shown in FIG.

The signal + (A/B) of 50n8 is inverted and becomes the signal - (A/B) 1, A. Ru. This signal is clocked by the same GCLK signal and 50n8 The clock signal 10T, (A/B)1.

AI-T(A7B'g,!,+T(A,/B)3.A group 4QgQ occurs . The signal + (A/B) is used in an uninverted state, and used to form an intersoy signal group (not shown).

Figure 28 shows the sub-bus interface for generating outward clock signals. 350 is a schematic diagram of the circuitry within 350; Its timing is shown in FIG.

250m5 signal 1 R3 is 7 lips 70 tubes 430, 431 data input terminal sent to. For 50ns due to their flip 70+T(A/B)1 clocked at intervals.

The outputs of the flip-flops 430 and 431 are sent to the ECU and /TT L converter 432. are sent to the respective bus drivers 435 and 437, and the TCLK line 45 and TF RM line 5o all 5o eve.

As mentioned above, TCLK operates continuously and TFRM operates in conjunction with the generation of tags. It just asserts.

TFRM is controlled by a signal 10 ETF (enable TFRM). That belief No. 10 ETF is one of the bits from control storage data register 375. child This means that ten ETFs clocked through Flip 70 tab 438 This is done by controlling the reset input of knob 431.

Similarly, the 250na signal 1R1 is the data of 7 lip 70 knobs 440, 431. data input terminal. The output of those 7 lip 70 amplifiers is ECL/TTL variable. through the converter 432 to the bus drivers 445 and 447, respectively, and the outward R Drive CLX line segment 47 (output) and outward P, F RM gland segment 52 (output).

rtFRM is clocked through flip-flops 448 and 449. Controlled by ERF (Enable RFRM). extra 7 lipflops (for +ETF) has a delay of 250 ns, so +R1 is 550 ns lower than +R3. 0 ns, but RFRM lags behind TFRM by 200 ng.

l0CP-Data movement FIG. 29 shows the sub-bus interface for data bus 40 and tag bus 42. A schematic diagram of the circuit inside the system is shown. The four tag bits are connected to the ECL/TTL converter 460. The entire lip 7a amplifier 462 is passed through, and the OS bit is passed through the converter 460. Engineering O The S pits and tag bits are sent to a parity generator 467, resulting in Seven bits are sent to bus driver 468 to drive tag bus 42.

The data bit is processed by an ECL/TTL converter 460 and two flip-flops. Passed through stages 472 and 475 to bus driver 477. flip 70 tube Stage 472 delays the data bits by 250 na compared to the tag bits. Furi Flip-flop 472.475 (and flip-flop 462) is +T O3 The clock can be read by the leading edge of the clock.

The output enable of the data bus driver 47γ is +gD in the first (7) case. It can be controlled by ATA (enable data). This +EDATA is control memory One of the device data register bits. ←EDATA has two flip-flops clocked through drop stages 480 and 482 to control the same timing as the data. Set. +T23 and +Tf)1 are combined in gate network 485.

The complement of this output from network 485 is shown in FIG. There are stones. This signal is further delayed by another gate stage, but the gate When gated by +EDATA clocked at 487, the subbus - Define basic output timing for the interface. That is, this The output driver is enabled for the main part of the 250ns cycle, Overall, it starts near the leading edge of TCLK (+R3), and starts near the trailing edge of TCLK. Extends beyond. Therefore, at the trailing edge of TCLK, the port's input latch 1 The data is valid when latched by 02.

FIG. 30 shows the data bus 40, ready bus 41, interrupt line 44, and error line 53. 3 is a schematic diagram of circuitry within the sub-bus interface for receiving the above signals; FIG.

RCT, RCLK signal on K line section 47 (in), of course, those signals are , sent to latch 502 via bus receiver 50o, trailing edge of RCLK (in) I can smell one bite. The output of the latch is sent to flip 70 knob 505.

The flip 70 knob 505 receives the TTL signal obtained from +T22 → -TT2. is clocked by the TT L/E CL converter 507 and available to the SBA. It will be done like this.

A certain amount of time has elapsed since the tag was issued indicating that there is more incoming data to read. Incoming data is not valid until this time has elapsed. Therefore, related to this behavior When incoming data is present, the SBA sends the signal →-RECV (control storage data one of the pinpoints in the data register). +RECV is 7 lip 70 lip 515 and then a set of cascaded flips. The signal is passed through a flop stage 517. The number of flip stages is 70. can be adjusted accordingly. Incoming data must be inverted at the subbus terminator. Since the timing is measured relative to RFRM and RCLK, which must be It becomes dependent on length. From the cascaded flip-flop stages 517 The output of is clocked by signal +721 at flip 70 knob 520. Once the RFRM turns, the signal data is valid (DATAVALID). occurs.

FIG. 31 shows the sub-bus interface used to determine the state of select line 43. is a schematic diagram of the circuit inside.

As mentioned above, the signal -0URBUS which adjusts the current source 282 of the selection line is , RFRM (+RF in the controller boat).

Each end of select wire 43 is terminated to ground by a 10t) ohm. This selection The selection line connects the positive input terminal of the first comparator 525 and the negative input terminal of the second comparator 527. given to.

The negative input terminal of comparator 525 is held at +1 volt and the positive input terminal of comparator 527 is held at +1 volt. It is kept at +4v. Those voltages are generated by voltage dividers. in the controller boat Each current source energizes a 50m1i 't' line, so one power source energizing the line is 2 ．． A 5 volt signal is generated, and multiple power supplies generate signals of 5 volts or more. Output of comparator The power is clocked by the incoming signal RFRM in flip-flop 530. . The output from flip-flop 330 is output as a signal at flip-flop 532. +TT2 (obtained from +T22) further increases the clock field. this signal 10TT2 takes timing from the sequencer rather than the incoming data. those beliefs The signal passes through the TT L/KCI, converter 535, and connects the signal +5 to MULTIPLK. Generates INOLE. In this way, many controllers regulate their respective power supplies. to drive the select line, the SBA can determine whether an error condition exists. Wear.

As with data, allow the RFRM signal to rotate the state of the select line. Must be checked at the time relative to the tag. Therefore, 7 lip 70 lip 54 Signal clocked at 0 and passed through cascaded flip-flop stage 542 The SBA asserts R8EL (one of the control store bits). pretend that The number of flip-flop stages is adjusted according to the length of the sub-bus (as described above). It will be done. The output from stage 542 is passed through +T21 in flip-flop 545. is clocked, and once the RFRM turns, the signal +CHECK 8ELEC Generate T.

Conclusion In summary, the present invention provides a circuit for configuring a system of logical transfer channels. I understand that it will be provided.

Minimal overhead (tag generation) once a transport channel is attached Data transfer takes place in I acknowledge it. This allows various intertwined movements to continue at their own speeds. Meanwhile, the bus is running at full speed.

Although the preferred embodiments of the present invention have been fully and completely disclosed, various modifications and alternative constructions may occur. Structures and equivalents may be employed without departing from the spirit of the invention. for example, The system shown can interact with up to 16 devices connected to subbuses. uses four transport channels, but their number is not fundamental. Must The number of tag lines required increases simply logarithmically with the number of transfer channels, but The number of lines increases linearly. There are still 1 non-required steps to request transfer channel affiliation. Using interrupt lines is in line with the idea of minimizing the actual bus medium. However, the cost of 7 It will rise.

Therefore, a system of transfer channels can jam the bus medium and provide a set of This can be realized in connection with the Al interrupt line.

Accordingly, the foregoing description and illustrations reflect the invention as defined by the appended claims. shall not be construed as limiting the scope of.

Rθ-1 FIG, 3゜ FIG, 5° F/G, 6B.

FIG. 3゜ FIo, 29° FIo, 3θ 1 →UV FIo, 3/.

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Claims (1)

[Claims] 1. Up to N devices can be combined onto a common data bus, allowing channel A processor can set up communication with any one of said devices on said data bus. In data communication systems, a data bus consisting of a first line group; ゛A tag pattern consisting of p is formed by a second group of lines that can form any one of a plurality of n digital codes. and The channel processor and the respective devices are connected to the respective data buses and the respective devices. a means for joining to the tag path; means for sending a request signal from the device to the channel processor; be programmed into each device to store any code among the n digital codes. registers to be matched, The digital code appearing on the tag path is converted to the data stored in the register. a comparator associated with each device for comparing digital codes; one of said n digital codes to said device in response to a request signal from said device; to the channel processor for temporary assignment to the designated one. and the means by which , wherein the channel processor temporarily assigns a channel to the designated device. Digital code 6 By placing a code on the tag path, the subsequent pass period is set to the specified device. the register associated with the comparator and the specified device. the specified device crab, the data by the channel processor; A data communication system that allows for determining the permissible use of TAVAS improvements. 2. The means for sending the request signal includes a common interrupt line; Hands associated with each device to assert the request signal on this common interrupt line. Step by step. To send an activity bit indicating that the request signal is asserted. means associated with each device; In response to a ball signal from the channel processor, the activity bit is and means associated with each device for sending the status of the device. The invention described in item 1 within the scope of 3. The means for sending the state of the activity bit is coupling a signal representing the state of the data line to a given one of the data lines; certain data lines are determined by the unit number of each device. , all said devices enter said activity pit state during one ball movement. The invention according to claim 2 of the appended claims. 4. related to the assignment of the one digital code among the n digital codes; to send the start address for data transfer to the specified device. as claimed in claim 1, further comprising means associated with said channel processor. The invention described in paragraph 1. 5. Common selection line and a current source associated with each device; features associated with each device to selectively direct this current source to the selected line. combined with a controller and said channel processor, and driven on said selection line. In response to the total current being applied, there is no device directing a current source to the selected line. And one device is the one! Conditions for directing the L accent source toward the selection line, and 1 Minimize the condition in which more than one device directs its power source to the selected line. a means by which the person can be identified; The invention according to claim 1, further comprising: 6. It further includes a shift register that matches each device, and A shift register associated with the select line drives the select line during operation of the current path. As a data signal representing whether the current source is directed to Recited in claim 5, which is received and clocked by subsequent bus operations. invention of. 7. Combination break in each shift register, generated from the channel processor The state of the shift register is frozen when receiving a broken clock signal. 7. The invention as claimed in claim 6, further comprising means for operating. 8. a ready bus consisting of a third line group including n lines; The channel processor and each device are connected to all lines in the ready bus. means for coupling to each device; and a means for coupling to each device; In response to the state of a register, the state of the register associated with the device is changed. Align the channel ready signal on the corresponding ready bus line, and then means for instructing the chair to be in a ready state during a permitted bus period; The invention according to claim 1, further comprising: 9. Further comprising a staging means combined with each device, the staging means being combined with each device; The buffer location and A plurality of corresponding bus words are transmitted between the data bus and the buffer. means for transferring over consecutive bus cycles of The invention according to claim 1, which includes: 10. Data communication between up to N devices and channel processors in the system, being associated with each of the devices and sending data to the bus; , and the channel processor indicates a desire to receive data on the bus. means for instructing the A trick to uniquely assigning a unique transport channel ID to any one of said devices step by step, and subsequent communication with that device without requiring the full address. A data communication system that can be carried out by providing its transfer channel to improvements. 11. A data communication system in which multiple devices can communicate with a channel processor. In the controller front end for the lζth device used in the system, The controller front end is now coupled to the data bus having the first line group. and means for connecting the front end of the controller to a plurality of n lines having a second group of lines. Connected to a tag bus that can configure any one of the digital codes means adapted to match, a register for storing any one of the n digital codes; a digital code appearing on said means adapted to couple to said tag bus; means for comparing the digital code stored in the register, and a request signal. means to send a signal and indicate a ready status as an acceptable bus period. , wherein the comparison means and the register are configured such that the controller front end The controller front end determines when it is allowed to use the data bus. A control front end for devices used in data communication systems. . 12. said means adapted to send a request signal to said controller front end; means adapted to couple the lines to a common interrupt line; means for asserting a request signal on the interrupt line; Sets an activity bit to indicate that a certain request signal is asserted. and means for detecting the state of the activity bit in response to a polling signal. A means of sending it, The invention according to claim 11, comprising: 13. The means for sending the status of the activity bit is coupling a signal representing the state of a bit bit to a given line of said data bus; means adapted to enable a particular data line to connect to said controller front end. A large number of similarly configured control front ends, determined by the unit number of the The command provides the state of the activity bit during one ball operation. The invention according to claim 12 allows 14. a current source; current steering means adapted to selectively direct the current source to a common selection line; further comprising: all the electric currents being driven on the common selection line are There are no, one, or more than one device that connects the source to the selection line; According to claim 11, it is possible to determine whether invention. 15. said current source is directed to drive said select line during a current pass operation; It receives as data input a signal indicating whether the bus is being Claim 14 further comprising a shift register clocked at The invention described. 16. When combined with the shift register and receiving a lock signal, the shift register Claims further comprising means operable to freeze the state of the register. The invention described in item 15. 17. Coupling the controller front end to a ready bus consisting of a group of n wires. and the means to get into the vagina, In response to the state of the register, the ready bar corresponds to the state of the register. Asserts the channel ready signal on the bus line and states the ready state for the allowed bus period. a means for instructing; The invention according to claim 11, further comprising: 18. further comprising staging means, the means comprising a plurality of buffer locations; a plurality of corresponding bus words between said data bus and said buffer; means for transferring over successive bus cycles; The invention according to claim 11, which includes: