JPS5949620B2 - Storage device clear method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for clearing a storage device of an inventory control machine, etc., and in particular, a clear command signal is composed of a combination of input signals known only to a specific operator, and a third party This relates to a clearing method that prevents the stored contents from being easily cleared.

Conventional methods for clearing the memory contents of data processing equipment, etc. have been provided with a dedicated clear key, and the memory contents can be cleared by pressing the key once whenever necessary. However, in digital processing equipment used for special purposes such as inventory management machines and bank account number indexing machines, the memory contents may be cleared carelessly or intentionally by someone unfamiliar with the operation or by a third party. If this happened, a huge amount of data would have to be re-registered, creating an inconvenience. In view of the above-mentioned difficulties, an object of the present invention is to encrypt a clear command signal to a device using a combination of a plurality of input signals, so that only a specific operator who remembers the code can clear the stored contents. It is constructed in such a way that it is not possible to do so.

Another object of the present invention is to provide a clear method in which a clear command signal is composed of a combination of a plurality of key input signals on a keyboard.

Yet another object of the present invention is to provide a preferred clearing method for forms that allow interaction with machines using natural language.

Still another object of the present invention is to provide a clearing method that allows an administrator to appropriately change and set the clear command signal.

Still another object of the present invention is to provide a clear method in which the clear command signal is a combination of a plurality of dial input signals and a plurality of key input signals.

In other words, in the present invention, a clear command cipher text freely selected by the administrator is registered, and only the administrator who knows the cipher text can execute the clear command, making it possible to completely protect the memory. It is possible. In order to carry out the clearing method of this embodiment, it is sufficient to register a clear command ciphertext in the searched data and to register contents meaning clear in the address attached to the searched data.

More specifically, it is as follows.

1. Register the clear command ciphertext appropriately determined by the administrator in the searched data.

2. Register the meaning and content that causes clearing to be performed at the attached address X of the searched data.

3 Questions are input from the keyboard.

4. If a corresponding sentence exists and a match is found, clear the specific address in the storage device according to the meaning of the attached address x.

Therefore, the attached address X mainly stores a coded signal having a meaning for specifying and clearing a specific address in the storage device.

With this configuration, the encrypted clear command can be appropriately changed and set every month, etc., and memory protection can be dramatically ensured, which is preferable.

Furthermore, when the present invention is applied to an information retrieval device, the clear command cipher text may be appropriately registered in the address currently occupied within the information retrieval device, so the overall configuration can be simplified. This will be explained below with reference to the drawings. 1st
The figure is an explanatory diagram when the clear method of the present invention is used in an information retrieval device.

Now, suppose that D1, SD2, and D3 are registered and stored as searched ciphertext data in the file memory of the information retrieval device. Also, immediately after the searched data D1, D2, D3,
It is assumed that different clear command contents are registered and stored as 2 and X3. Now, the contents of each code are as shown in the figure, D1=
"Himawarisakeba Akari Hairanaiyo", d2="
``Sunflower Salmon'', D3 = ``Sunflower l month'', question text Q
Assume that 1 = "Himawarisakeba Akari" is input.
Then, when a short search instruction is given, since the record of data D1 corresponds, X1 is output as a search answer.

This means that the answer X1 can be obtained without the operator having to input the following question sentence ``Hairanayo'' and that a specific memory, for example, memory M1 can be cleared. In order to achieve this purpose, a signal QE1 indicating the final data position of the question text and a short search command signal Short are required.
It is sufficient to prepare an AND gate GS1 to which is applied, and configure the output of the comparator circuit to be controlled by the output of this gate GS1. Also, if you enter a question such as Q2 = "sunflower" and give a short search instruction, as shown in the figure, AND gate GS2 generates the output when all data D1, D2, and D3 are compared, and the comparison circuit is activated. Since all are output, all of the answers X1, X2, and X3 are output. This means, for example, that certain memories M1, M2, M3 are cleared. Also, if you enter Q3 = "Sunflower Salmon" and perform a short search, the answer will be X1, X with the same operation as above.
2 is output. This clears memories M1 and M2. In addition, if you enter a question up to Q3 = "Sunflower Salmon" and give a full search instruction, in this case, the question text data end signal QE3 and the searched data end signal (data D
1, D2, and D3 respectively)
Since the AND gate GF is prepared to which the full search instruction signal Ful1 is applied, the output of the gate GF is generated only when the number of characters of the question sentence and the data to be searched are equal, and X2 is output as the answer, and the specific memory M2 is cleared. That is, the information retrieval device according to this embodiment is configured not only to compare the contents of data, but also to appropriately control the output of the comparison circuit using the output that detects the length of each data.

More specifically, in the case of a short search, the output of the comparison circuit is controlled by the final output of the number of characters in the question sentence, and in the case of a full search, in addition to that, the output when the number of characters in the searched data is equal to the number of characters in the question sentence. The output of the comparison circuit is controlled by the following. As mentioned above, the clear method of the present invention is extremely useful not only for information retrieval devices but also for various data processing devices. FIG. 2 is a file organization diagram using variable length records, with A1, A2, B.
C1... is the data to be searched, and the current data contents are A1 = "Violet", A2 = "Sunflower salmon", B = "Sunflower salmon", C =
Assuming that "Sunflower" is registered and stored, A1 and A2 are stored in the first record, the answer AX is attached at the end, and the execution contents of the clear command are stored.

B1C is also stored in a separate record different from the above. BX,. CX is the answer content corresponding to the searched data B1C, and different clear command content is stored therein. a1, a2, b1 C is a part indicating the number of characters in each searched data, and the actual number -1, that is, a1=2, a2=
16, b=5, c=3 are stored. Figure 3 is an example of a specific implementation circuit for performing a search. In Figure 3, CC
1 is an overall control circuit which inputs a question text and control instructions such as full search, short search, etc. from the outside, and when a match is found, performs control to execute the contents, that is, to clear a specific memory.

The FD is a part where searched data is stored as shown in Figure 2, and memories M1 and M2 where data to be protected is stored.
, M3, etc. (hereinafter referred to as file), D
C is a decoding circuit that creates the necessary timing signal from the data to be searched from the file FD, its output TB is the basic timing pulse, RE is the record end signal, which is the end signal of one record, and EFT is the signal for the end of one record. During the output period of search data...This is a signal indicating the time to be searched at the level. The IC is a counter to know the end of the searched data in each item in one record, and after receiving and storing character number information a1, a2, etc. of each item from the searched data, it counts down at a fixed cycle (TB). When the content of the counter reaches a certain value (for example, 0), output 1 is generated from the NOR gate NR, and the searched data end signal D
Use as E. Flip-flop JF is a flip-flop that is set by the first TB pulse of each item and reset by the searched data end signal DE.
When the searched data is not read out, it is in a reset state. DF is a D for receiving the output signal of the JK type flip-flop JF and generating a signal delayed by the ITB pulse time.
It is a type flip-flop. AG is an AND gate that generates a comparison start command CS for the first ITB pulse time of the searched data in each item, and the above two flips
Flop JF. ．． The time difference set by the DF is gated and output. QM is a memory that stores the question text and can output it from the beginning at any time in combination with the address counter MC described below. The address counter MC is for the address of the memory QM, and is also used as a counter for counting the number of characters in the data to be searched. CM is a circuit that compares the searched data and the question text, and the comparison start command C
The comparison process is started by S, and the comparison process is stopped by the comparison result output command CE from the OR gate OR, and the comparison result signal CO is output. Furthermore, if the comparison start command SS is applied again before the comparison result output command CE, the comparison circuit has a function of invalidating the processing up to that point and starting the processing again. CI is a matching circuit that checks the match between the number of characters in the question text and the number of characters in the searched data, and checks the match between the character number counter MC of the searched data and the output of the question text character number latch circuit QL. The latch circuit QL stores a value equal to the number of characters in the question text minus 1, and the output of the matching circuit CI becomes the question text end signal QE. GS is a short search, and the comparison result output command C is sent by the question end signal QE.
This is an AND gate that outputs E. GF is an AND gate that outputs a comparison result output command CE when the question text end signal QE and the searched data end signal DE are received in the case of a full search, that is, when the number of characters of the searched data and the question text match. . The DB is a buffer memory that stores one record of searched data. This buffer has a capacity greater than the longest record length. IS is a circuit for extracting any one item from the one record of the buffer DB, and operates upon receiving an answer retrieval command from the control circuit CC, and sends the contents of the instructed one item to the answer memory XM. The memory XM is a memory that stores the one item retrieved from the buffer DB by the retrieval circuit IS. FF
is set by a set command from the control circuit CC in the flip-flop used to determine whether there are multiple answers when processing is performed without classification in the case of a short search, and when this flip-flop FF is set. If there is one item to answer, and there are more items to answer in subsequent processing, the lamp lights up. Next, to explain the operation in Figure 3, first, the file FD
The operator (questioner) inputs the question text into the control circuit CC and instructs full/short search and classification.

The control circuit CC in FIG. 3 first stores the question text in the question text storage memory QM from the first address, stores the value of the number of characters in the question text minus 1 in the latch QL, and also sends a full or short search command to the AND gate. Send to GF or GS.

Next, a command is given to read the first record to the file FD. Then, all the retrieved data of the read file record is compared in the comparison circuit CM, and also in the control circuit CC.
After receiving the record end signal RE from the decoding circuit DC, it knows from the comparison result signal CO from the comparison circuit CM whether or not there is an item in the record that has just been read that satisfies the condition. If it does not exist, control circuit C
C issues a command to read the next record to the file FD and continues until the next file completion signal is received.

If the control circuit Cc is notified of the establishment of the condition by the comparison result signal CO in a certain record, the control circuit CC receives the contents from the memory XM and sends the memory clear signal C to the file FD, Accordingly, memory M1,
Selectively clear M2, M3, etc. FIGS. 4 and 5 are diagrams showing the power switch section of the present device, and memory protection is further ensured by making the clearing operation even more difficult and complicated.

That is, the key a shown in FIG. 5 is loaded into the insertion portion S of the main unit shown in FIG. 4. Then, when the key a is turned from the standby position to the ON position, the device is powered on and ready for use.
When you want to clear some or all of the memory of the device you are using, turn key a from the ON position to the CLEAR position, the one-shot multi MM will operate, and the clip-flop F1 shown in Figure 1 will be set. Thereafter, a clear signal is generated in the same manner as described above by encrypted key input to clear the desired stored contents. In this embodiment, by using a key separate from the main unit as a part of the clearing means, the clearing operation can only be performed by a specific operator, and careless memory destruction and erasure are reliably prevented. It is something that can be done. Also, part of the clearing means separated from this main body is key a.
However, any other means that can be separated from the main body, such as a code secret medium or special equipment, can be used. As described above, the present invention is extremely preferable because it can reliably prevent inadvertent clearing operations and also reduce the number of key operations required for clearing.

[Brief Description of the Drawings] Fig. 1 is an explanatory diagram of the basic principle of the present invention, Fig. 2 is an example of the organization of variable-length records, Fig. 3 is an example of a specific implementation circuit of the invention, and Fig. 4 is an illustration of the basic principle of the present invention. The diagram shows the power supply for the main unit! FIG. 5 is a diagram illustrating the key part, and FIG. 5 is a diagram showing the key used in FIG. 4. CC...Control circuit, FD...File, DC...Decoding circuit, IC, . MC...
・Counter, QM... Question storage memo 18CM
... Comparison circuit, CI ... Matching circuit, Q
L...Question character count is low, GF1GS...
...and gate.

Claims (1)

[Claims] 1. The storage device has multiple pieces of encrypted search data, and each piece of search data corresponds to a clear command, and when a question is input, all clear commands corresponding to the search data that match from the beginning are output. A storage device clearing method characterized by: