JPS5948591B2 - Image display device that displays a mixed image signal as an interlaced television image - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a picture tube for displaying an interlaced television image by providing a horizontal and vertical deflection circuit for deflecting at least one electron beam generated in the picture tube. The present invention relates to an image display device configured to display a mixed image signal including a digital drawing information signal and a digital drawing information signal.

Image display devices of this type having an image display surface capable of displaying a mixed image signal are known, which can be used to display a standard television image, e.g. It is possible to superimpose and display a group of characters, a group of figures, etc. that are generated manually.

However, with conventional image display devices of this type, it is known that the displayed image moves up and down extremely rapidly at the change in vertical deflection between a portion of the displayed image that does not include characters and the like and a portion that does. In particular, when the contrast between the two parts is strong, this phenomenon becomes extremely bothersome.

This is especially likely to occur when horizontal straight lines are displayed. Such "jitsuta" means that images containing text, etc.
This is based on the fact that identical field images are alternately displayed on the display surface, the height differing between each by one scan line interval. the vertical resolution of the image signal generated by the television camera is poorer than the vertical resolution of the image signal generated by the digital character signal generator;
Furthermore, since horizontal straight lines do not appear in the image signals generated by television cameras, as a general rule, such phenomena do not occur in images from television broadcasters.

Conventionally, a circuit for eliminating the above-mentioned phenomenon has been provided in a character signal generator, for example, a text image decoding circuit, or in a portion of a television receiver that processes image signals before supplying them to the control electrodes of the picture tube. Proposed.

Although the proposed circuits affected the details contained in the image displayed in the transition area to such an extent that the above-mentioned phenomenon was no longer noticeable, these circuits had the drawback of being too complex. An object of the present invention is to provide an image display device in which the conspicuousness of the above-mentioned jitter phenomenon is reduced. The present invention is characterized in that it includes a circuit that generates an additional deflection signal that is additionally deflected in the vertical direction to substantially eliminate interlace in a portion of a displayed image in which a digital document information signal is superimposed and displayed.

That is, in the present invention, as a circuit to be provided to reduce the conspicuousness of the above-mentioned jitter phenomenon, a circuit added to the deflection circuit portion of the image display device has a more structured structure than a circuit added to the image signal processing circuit portion. It is based on the recognition of the fact that it is simple.

The present invention eliminates the root cause of the above-mentioned troublesome phenomenon, that is, interlacing, and is made to be realized only in the part of the displayed image where this phenomenon occurs, that is, in accordance with the content of the displayed image. . Although this deinterlacing causes a slight decrease in vertical resolution in the relevant portion, it is less disturbing to the viewer than the jitter phenomenon, which is almost eliminated by deinterlacing. In other words, deinterlacing according to the present invention only has a very slight effect on the image quality of the television image in the portion where characters etc. are superimposed, and does not affect other portions of the displayed image. The selected number of image scan lines are displayed as they are. The image display device of the present invention is also characterized in that the above-mentioned additional deflection signal is a frame frequency signal that causes horizontal scanning lines displayed on the image display surface of the picture tube to substantially overlap. In addition, the above-mentioned additional deflection signal is characterized in that it is an additional current flowing through the vertical deflection coil with an amplitude and direction such that the horizontal scanning lines displayed on the image display surface substantially overlap.

Furthermore, the image display device of the present invention is characterized in that the above-mentioned additional current flows in every other field period and has an amplitude approximately corresponding to the interval between two adjacent scanning lines in the image. It is.

In a preferred embodiment of the image display device of the present invention, the amplitude of the above-mentioned additional current corresponds approximately to half the spacing between two adjacent scan lines in the image, and the direction of the additional current is changed every field period. It is characterized by being reversed.

Further, the image display device of the present invention equipped with a vertical deflection amplifier that generates a deflection current flowing through a vertical deflection coil is provided with a current source that generates the above-mentioned additional current, and the current source is connected to the negative feedback of the vertical deflection amplifier. It is characterized by being connected to a vertical deflection amplifier in such a way that it has almost no effect on its operation. Furthermore, the image display device of the present invention, which is equipped with a picture/paper decoding circuit that generates a still image signal, is characterized in that the image fitting frame signal generated by the picture/paper decoding circuit is used as information indicating the presence of a digital picture/paper information signal. It is said that

The invention will be explained in more detail below by way of non-limiting examples with reference to the drawings, in which: FIG.

First, a configuration example of the main parts of the image display device of the present invention will be described in the first section.
As shown in the figure.

In the circuit arrangement shown, 1 designates a vertical deflection amplifier of known type, connecting two power amplification transistors 2 and 3. A vertical deflection coil 4 for vertically deflecting an electron beam generated in a picture tube (not shown) is connected to the interconnected emitters of the power amplifying transistors 2 and 3, and the other end of the vertical deflection coil 4 is It is connected to a series connection circuit of a capacitor 5 and a negative feedback resistor 6. During operation, a sawtooth waveform deflection current with a field frequency of, for example, 50 Hz (European standard system) flows through the vertical deflection coil 4, and the voltage developed across the resistor 6 passes through the negative feedback circuit 14 to the vertical deflection current. Negative feedback is provided to the inverting input terminal 1b of the deflection amplifier 1 and compared with the input sawtooth voltage from the sawtooth generator, so that the above-mentioned deflection current is applied to the input sawtooth waveform supplied to the input terminal 1a. It has the same waveform as the voltage.

Therefore, an image display device including the circuit shown in the first diagram as a main part,
For example, if a television receiver is used for displaying standard television images, an interlaced image appears on the image display surface. This is caused by the fact that the horizontal synchronizing pulse train in the next field period is shifted by one horizontal scanning period. Note that in the circuit configuration shown in the first diagram, many well-known components are omitted for the sake of simplicity as they are not important to the present invention. There is a vertical position adjustment circuit that allows direct current to flow through the deflection coil 4. Therefore, the total current flowing through the vertical deflection coil 4 is a sawtooth waveform current in which the direct current component is slightly shifted in the positive or negative direction. Become. Therefore, according to the present invention, between the collector emitter of the first Npn transistor 7, the resistor 8, and the second Npn
A series connection circuit between the collector and emitter of the pn transistor 9 is connected to the connection point between the vertical deflection coil 4 and the capacitor 5, and a series connection circuit between the emitter of the second Npn transistor 9 and the capacitor 5 of the negative feedback resistor 6 is connected to the connection point between the vertical deflection coil 4 and the capacitor 5. The terminal that is not connected to the terminal is grounded.

Also, the first and second Npn transistors 7 and 9
Each base is connected to a document and image decoding circuit 10 that processes a document and image information signal supplied from a receiving circuit section (not shown) of a television receiver in a well-known manner.
The calligraphy information signal supplied to the base of the transistor 7 is the one supplied from the output terminal 11 of the calligraphy decoding circuit 10, while the image frequency, that is, the square wave of 2511z, is supplied to the base of the second Npn transistor 9. The signal is supplied from the output terminal 12 of the document/picture decoding circuit 10. Figure 1 shows an example of each signal waveform appearing at the output terminals 11 and 12, and the signal waveform appearing at the output terminal 11 reaches the logic level "o" during a part of one field period. During the period of Q part,
No graphical information is applied to the control electrodes of the picture tube and the standard television signal received by the television receiver is unaffected.

Therefore, when the signal waveform appearing at the output terminal 11 at a predetermined time reaches the logic level "1", the logic level "1"
by supplying graphical information, e.g. subtitles that do not change over several field periods, to the control electrodes of the picture tube, during which time the brightness and/or contrast of the received television image is limited. shows. Furthermore, after a certain period of time has elapsed, the signal waveform appearing at the output terminal 11 becomes the logic level "o" again. In such a state, the image displayed on the display surface of the picture tube becomes a so-called mixed image, in other words, a part of the image display surface, for example, the upper part, displays a standard television image, and the other part of the image display surface displays a standard television image. For example, in the lower part, calligraphic information is displayed, and further below that, the standard television image is displayed again. Therefore, a sharp change in brightness in the vertical direction is noticeable at the periphery of the portion where the calligraphic information is displayed, and unless the measures according to the present invention are taken, the above-mentioned troublesome jitter phenomenon will occur. As a result, the signal waveforms appearing at the output terminals 11 and 12 become 1 as shown in FIG.
If this occurs in one field period, it will not occur in the next period, but during the period when the logic level is "1" at the same time, the first and second Npn transistors T and 9 become conductive.

Therefore, these transistors 7 and 9 perform an AND operation to flow a current with a frequency of 25 Hz, and this current flows to the power amplification transistor 2 or 3. This current also flows into the vertical deflection coil 4 and shifts the horizontal scanning line displayed on the display screen in the vertical direction like the position adjustment current described above, but unlike the position adjustment current described above, the horizontal scanning line The vertical shift of does not occur over the entire screen, but only over a portion of the screen. The resistance value of the resistor 8 is thus selected such that the above-mentioned current causes the above-mentioned vertical shift of a value equal to the spacing between two adjacent scanning lines.
For example, if an image is displayed on approximately 600 scanning lines out of 625 scanning lines per image in the European standard system, and the amplitude of the vertical deflection current is 3A, and the strength of the above-mentioned current is approximately 5mA. The resistance value of the resistor 8 varies depending on the power supply voltage, but is several kilohms, and therefore, the current value is not determined depending on the vertical deflection coil. That is, the first and second Npn transistors T and 9 operate as current sources that have almost no effect on the output voltage of the power amplification stage constituted by transistors 2 and 3, and the current eventually flows to the negative feedback resistor 6. It has almost no effect on the current, and therefore its negative feedback does not prevent the generation of additional current flowing through the vertical deflection coil 4, which increases the deflection current. Depending on the direction, it is sometimes subtracted from the deflection current,
In some cases, it will be added to the deflection current. During the period in which the above-mentioned current is occurring, for example, during the period for two horizontal lines in calligraphy information, that is, for 20 standard image scanning lines, the image display scanning line in one field period and the image displaying in the next field period. The scanning lines overlap because they are not shifted.

Therefore, the number of scanning lines used to display the image is reduced by 50% in the corresponding area, but the jitter described above is almost completely eliminated, and this is not the case in other areas of the displayed image. On the other hand, interlacing is preserved as is. It is thus clear that in the circuit configuration shown in the first figure, the current sources are included in two parallel branches, and in such a circuit configuration the additional current mentioned above can be introduced in different ways. For example, negative feedback resistor 6
A circuit network can be provided in the negative feedback circuit inserted between the input terminal Ib and the inverting input terminal Ib, and a square wave voltage with a frequency of 25 Hz can be applied to the circuit network in a superimposed manner. Also, non-inverting input terminal 1
It is also possible to add a square wave voltage with a frequency of 25z to the sawtooth wave voltage supplied to a. In the case outlined above, it is first necessary to generate a signal with an appropriate waveform using the signal waveform appearing at the output terminals 11 and 12 and the AND gate circuit. Therefore, in the above-mentioned case, the predetermined number of scanning lines in one field period are shifted in the vertical direction by one scanning line interval. However, for some types of images, for example, images with many vertical luminance changes, the above-mentioned scan line shift of one scan line interval is too large. Therefore, if the scan lines of one field period are shifted downward by half the scan line spacing in that part of the displayed image, the scan lines of the next field period are shifted upward by half the scan line spacing, resulting in interlacing. It is preferable to eliminate this, and such a scanning line shift can be realized by the circuit configuration shown in FIG. In the circuit configuration shown in the second figure, components 1 to 6 are the same as the circuit configuration shown in the first figure, but the collector of the Pnp transistor 7' and the collector of the NDn transistor 9' are connected to the vertical deflection coil 4 and the capacitor 5.
Also, a resistor 8' is inserted between the emitter of the Pnp transistor 7' and the positive power supply voltage line, and a resistor 8I is connected between the emitter of the Npn transistor 9' and the ground potential. It is placed between. However,
Output terminal 1 is connected to the bases of transistors 7' and 9'.
During the field period, except for the period in which the local vertical erase signal appearing at output terminal 12 is at logic level 7'5, the same switching signal is applied which shuts off those transistors 71 and 97, so that the signal appearing at output terminal 12 is at logic level 7'5. level 11
In period I, when the level of the switching signal exceeds the average level in a certain field period, the level of the switching signal falls below the average level in the next field period.

Such a switching signal is formed by the signals appearing at output terminals 11 and 12 and is connected to P via resistor 13'.
It is supplied to the base of the np transistor 7', and
It is supplied to the base of Npn transistor 9/ via resistor 13'. When the level of the switching signal supplied to the bases of transistors 7' and 9' exceeds the average level, Npn transistor 9' becomes conductive, and Pnp transistor 7' remains non-conductive. Moreover, when the level of the above-mentioned switching signal is negative, that is, below its average value level, P
While np transistor 7' becomes conductive, Npn transistor 9' remains non-conductive.

In this way, the collector currents that alternately flow through the transistors 7' and 9' flow in opposite directions to the vertical deflection coil 4, so that when one collector current causes an upward shift in the image display surface, the other collector current will cause a downward shift. Note that the resistors 8' and 8'2 have approximately the same resistance value, that is, a resistance value that causes a scanning line shift of, for example, half the scanning line interval, and
For the above-mentioned numerical example, the current value of the above-mentioned shift current is 2.5 mA. Next, with the circuit configuration shown in FIG. 3, the same results as described above with the circuit configuration shown in FIG. 2 can be obtained.

In the circuit configuration shown in FIG. 3, the components 1 to 6 and 14 are configured similarly to those shown in FIGS. 1 and 2, but the connection point between the vertical deflection coil 4 and the capacitor 5 is
The anode of the diode 14' and the cathode of the diode 15' are connected to each other, and the anode of the diode 15' and the anode of the other diode 14'' are connected to the collector of a Pnp transistor 16/. ' is connected to the positive power supply voltage through a resistor 171. Similarly, the emitter of diode 1
The cathode of 4' and the cathode of another diode 15'' are connected to the collector of Npn transistor 16'O.
The Npn transistor 16'O emitter is connected to the resistor 17
'5, it is connected to ground potential. Note that resistance 17'
and the resistor 17'' have almost the same resistance value.Furthermore, the cathode of the diode 14'' and the diode 15'O
The connection point with the anode is connected to a resistor 19 whose other end is connected to a positive power supply voltage, and also connected to a resistor 20 whose other end is connected to the collector of the Npn transistor 18.

Note that the emitter of the Npn transistor 18 is connected to the ground potential. Further, the base of the Pnp transistor 16' is connected to the collector of the Npn transistor 21, and the collector resistor 22' and emitter resistor 22'5 of the Npn transistor 21 have substantially the same resistance value. Thus, if a square wave voltage at the image frequency appearing at output terminal 12 is supplied to the base of Npn transistor 18, and a local vertical erase signal appearing at output terminal 11 is supplied to the base of Npn transistor 21, the latter local Transistor 21 in response to application of vertical erase signal
, 16' and 16th<=conducting during a certain portion of the field period, and the Npn transistor 18 becomes non-conducting during one field period and conducting during the subsequent field period, thereby making the Npn transistor 18 conductive. A non-conducting state change cycle occurs at the frame frequency. Therefore, when the Npn transistor 18 is in a non-conductive state and the transistors 21, 16' and 15' are in a conductive state, the collector current of the Npn transistor 16'' flows through the resistor 19 and the diode 15'9, and the Pnp transistor 16'' flows through the resistor 19 and the diode 15'9. The collector current of ' flows through the diode 15', the vertical deflection coil 4, and the power amplification transistor 2 or 3.The resistance value of the resistor 19 is such that the voltage appearing at the collector of the Npn transistor 16' flows into the collector of the Pnp transistor 16'. Diode 14' is chosen to exceed the voltage that appears.
and 14'' become non-conductive. Also, during the corresponding portion of the next field period, transistors 16', 16'', 18 and 21 become conductive, and this time, N
The collector current of pn transistor 16' is diode 1
4' and the Npn transistor 18.
The collector current of the Npn transistor 16'' flows through the vertical deflection coil 4 and the power amplification transistor 2 or 3, so that the diodes 15' and 16'' become non-conducting.

During the remainder of the field period, transistors 21, 16' and 16nt)s are non-conducting, so no shift current occurs even though Npn transistor 18 is conducting. Note that the degree of overlapping of the image display scanning lines is adjusted by a potentiometer 23 introduced to the base connection line of the Npn transistor 21. Next, the figure shown in the left half of Figure 4 shows a part of the original standard system image, and the figure shown in the right half of the same figure shows the result of the circuit configuration shown in Figure 1. A portion of the resulting image is shown. Here, a solid line represents an image display scanning line in one field period, and a broken line represents an image display scanning line in the next field period. In FIG. 4, the second, third and fourth
The solid line is shifted downward by one scan line interval H.
Next, the figure shown in the right half of FIG. 5 shows a part of the image resulting from taking the measures using the circuit configuration shown in FIG. 2 or 3, and the figure shown in the right half of FIG. The lines are shifted downward, but now by half the scan line spacing, NH, while the scan lines indicated by the second, third, and fourth dashed lines are shifted upward by the same distance. There is. From these figures, it can be seen that the slight luminance error introduced by the means according to the present invention is of the same magnitude at both the upper and lower ends of the horizontal line shift portion in the case shown in Fig. 5, whereas in the case shown in Fig. 4 In , the width of the inter-scan line dark area that occurred after the first scan line indicated by the dashed line is 2 H, while the width of the inter-scan line dark area that occurred after the fourth scan line indicated by the dashed line 4' is 2H. The width of the dark area is equal to one scanning line interval H. On the other hand, in the case shown in FIG. 5, the widths between the corresponding upper and lower scanning lines are both 1iH, and the brightness and darkness are approximately the same. Despite this theoretical difference, the visual impression of brightness is somewhat different from that described above with respect to Figures 4 and 5, so Figures 2 and 3 The circuit configuration shown in the figure should be more suitable. Furthermore, deinterlacing by the above-mentioned scanning line shift according to the present invention is not limited to the case where it is performed over the entire length of the scanning line displaying calligraphy information, but, for example, when characters, etc. are displayed from any position on the scanning line. In such a case, the above-mentioned scanning line shift can be applied only to that part, and in such a case, for example, an image fitting frame signal for displaying document information is used to generate the scanning line shift signal. be able to.

However, the scan line shift current must be able to vary at high frequencies, and since the frequency bandwidth of the vertical deflection amplifier including the vertical deflection coil is limited, It may be difficult to generate a scan line shift current that is practical, and in practice there are limits to partial implementation of scan line shifts. One of the solutions to this problem is to use an auxiliary deflection coil with an extremely small inductance value in addition to the vertical deflection coil 4, or to use a picture tube electrode that applies a scanning line shift voltage instead of a scanning line shift current. The use of For example, the point where the weight of calligraphy information is displayed starts a certain distance from the left edge of the image display surface, ends a certain distance from the right edge of the image display surface, and has a height of several scanning lines. Applicable if you have.

For example, when the display part of such calligraphy information where a subtitle is displayed is superimposed on a television image from a broadcasting device, during the corresponding number of scanning line periods, the display area corresponding to the output terminal 11 of the calligraphy and picture decoding circuit 10 The appearing signal changes from logic level "1" to //O" before the end of one scan line period and to logic level "O'5" after the start of the next scan line period.
This results in a rectangular waveform signal with a horizontal scanning frequency that changes from
The base of the n-transistor 7, the bases of the transistors 7/91 in the circuit configuration shown in the second diagram, or
This can be achieved by supplying the logic level I/1'5 to the terminal shown at the top of the diagram of the potentiometer 23 in the circuit configuration shown in FIG. 3 during the period between the logic level changes described above. can. Furthermore, such logical level/
'11 is supplied to the output terminal 11 of the document/picture decoding circuit 10,
Each base of the above-mentioned transistors 7, 7' and 9',
Alternatively, as shown in FIG. 3, for example, as shown in FIG. This can be realized by inserting a monostable multivibrator 24 or the like designed to maintain the voltage level of . can be resolved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of essential parts of the image display device of the present invention, FIG. 2 is a circuit diagram showing another example of the configuration, and FIG. 3 is a circuit diagram showing still another example of the configuration. , FIG. 4 is a diagram schematically showing the difference in the displayed image depending on the presence or absence of the circuit shown in the first drawing, and FIG. 5 is a diagram schematically showing the difference in the displayed image depending on the presence or absence of the circuit shown in the second or third drawing. It is a diagram schematically shown. 1... Vertical deflection amplifier, 1a... Non-inverting input terminal,
1b... Inverting input terminal, 2, 3... Power amplification transistor, 4... Vertical deflection coil, 5... Capacitance,
6... Negative feedback resistance, 7, 9, 9', 16'', 18, 2
1...Npn transistor, 71,16t...PnP
Transistor, 8, 8', 8'', 13', 13I, 17
', 17'', 19, 20, 22', 22I...resistance,
10... Document and image decoding circuit, 11, 12... Output terminal,
14... Negative feedback circuit, 14', 14I, 15/, 15
″--Diode, 23... Potentiometer, 2
4... Monostable multivibrator.

Claims (1)

[Scope of Claims] 1. The picture tube is equipped with a horizontal/vertical deflection circuit that deflects at least one electron beam generated in the picture tube in the horizontal and vertical directions, and the picture tube displays an interlaced television image. In an image display device configured to display a mixed image signal including a digital image signal and a digital drawing information signal, the electron beam is additionally deflected in a vertical direction when displaying the digital drawing information signal. an auxiliary deflection circuit that generates an additional deflection signal that substantially eliminates interlacing in a portion of the display image in which the digital document information signal is displayed; An image display device characterized in that the signal is used to cause horizontal scanning lines displayed on an image display surface to substantially overlap each other. 2. The image display device according to claim 1, wherein the auxiliary deflection signal is a current source that forms an additional current flowing through the vertical deflection coil in every other field period, and the additional current is An image display device characterized by having an amplitude approximately corresponding to a current required for deflecting an interval between adjacent scanning lines in an image. 3. The image display device according to claim 1, wherein the auxiliary deflection circuit is a current source that generates an additional current flowing through a vertical deflection coil, and the additional current deflects half the distance between adjacent scanning lines in the image. An image display device characterized in that the additional current has an amplitude substantially corresponding to the current required for the additional current, and the direction of the additional current is reversed every field period. 4. The image display device according to claim 2 or 3, which is equipped with a vertical deflection amplifier that is equipped with a negative feedback circuit and generates a vertical deflection current flowing through the vertical deflection coil.
An image display device characterized in that the current source is connected to the vertical deflection amplifier in such a manner that it hardly affects the negative feedback effect of the vertical deflection amplifier. 5. In the image display device according to claim 2, the current source is provided with first and second transistors arranged in series between their collectors and emitters, and the control signal for making the first transistor conductive is transmitted to the current source. An image display device characterized in that a digital drawing information signal is applied during a display period, and the control signal of the second transistor is a rectangular symmetrical waveform signal of a frame frequency. 6. The image display device according to claim 3, wherein the first coil is connected to the vertical deflection coil so that a collector current flows through the vertical deflection coil during a period in which the digital drawing information signal is displayed on the current source. and a second transistor, the first transistor is provided in one field period.
The collector current of the transistor flows in a predetermined direction in the vertical deflection coil, and the collector current of the second transistor flows in the resistor, and in the next field period, the collector current of the second transistor flows in the vertical deflection coil. The collector current of the first transistor flows in a direction opposite to the predetermined direction through the third transistor to which a control signal having a rectangular symmetrical waveform of a frame frequency is applied. Image display device. 7. The image display device according to claim 1, wherein the auxiliary deflection circuit is a voltage source connected to an electrode of the picture tube. 8. The image display device according to claim 1, comprising a picture decoding circuit for generating a digital picture information signal, wherein the picture decoding circuit is connected to the base of a transistor forming a part of the auxiliary deflection circuit, and An image fitting frame signal generated by a calligraphy/picture decoding circuit is used as information indicating the presence of the digital calligraphy/picture information signal, and the transistor is made conductive at a frame frequency during a period in which the digital calligraphy/picture information signal is displayed. image display device.