JPS5945264B2 - counter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a counter circuit that counts a predetermined number of clock pulse signals and measures a time corresponding to the counted number.

A so-called ripple counter circuit in which multiple stages of binary counters are connected in cascade has the advantage that it requires fewer elements than a synchronous counter circuit.

FIG. 1 is a block diagram showing an example of a conventional counter circuit that counts clock pulse signals and measures a time 512 times as long as the clock pulse signal.

In FIG. 1, reference numerals 1 to 10 indicate flip-flops (hereinafter abbreviated as F and F) sequentially connected in multi-stage cascade so that the Q output signal of the previous stage becomes the synchronization signal of the latter stage.

The output signals of each F, F1-10 are fed back to the D (data) input terminals of each F, F1-10.
10 has a function as a binary counter.

Further, a preset signal S2.8 is supplied in parallel to the R (IJ set signal) input terminals of each of the F and F1 to F10.

Furthermore, this preset signal S2.8 is supplied to one of the NOR gates 11 of the NOR gates N1 and 12, whose input and output ends are crossed and connected as flip-flops so that the output signal of one becomes the input signal of the other.

Further, the other NOR gate 12 is supplied with the Q output signals of F and Flo at the last stage of the multi-stage cascade connection.

The preset signal SP, 8 is a clock pulse signal S.
is supplied via an inverter 14 to an AND gate 13 connected thereto, and the output signal of this AND gate 13 becomes a synchronization signal for F and Fl in the first stage of the multi-stage cascade connection.

Then, the preset signal S is changed from the level ``l'' to ``0''.
By changing the level, each F-Fl-10 is reset and the Q output signals Q1-Q1o become 1101 lvl.

Also, is the preset signal 5p-s +? From 11 Lebel
By changing to 101 rubel, AND gate 13
is opened, and the clock pulse signal S is output from the AND gate 13.

, P are input to the first stage F-Fl.

When each F, F1 to F10 counts 512 clock pulse signals, the Q output signal Qto of the last stage F, Flo is inverted from "0" to "°1".

When the Q output signal Qto of F and Flo is inverted, a signal of "1" level is input to the NOR gate 12, and the output signal of the NOR gate 11 becomes the "'l" level, and it is detected that a predetermined time has been measured. .

By the way, in the ripple counter, it is inevitable that a transmission delay time occurs between the synchronization signals of F and Fl at the first stage and the synchronization signals of F and Flo at the last stage.

For example, in the case of a 10-bit counter circuit in which F, F are cascaded in 10 stages as shown in FIG.
10 output signals are Qt = Q2 = Q3 = Q4 =
Q5 = Q6 = Q? = Qs = Q9 =
"l" level, Qlo = nOty level (however, Q□
~Q1o are the Q output signals of F and F1~~10, respectively), then count the clock pulse signals and immediately output Q.
1=Q2=Qs=Q4=Q5=Q6=Q7
=Q8=Q9="O" level, Qto-"'1" level should be achieved.

However, due to the above transmission delay time, before the Q output signal QIO of the last stage F, Flo reaches the tlljl level, the F, F near the first stage has already counted several times of the next clock pulse signal. Q1=Q2=Q3
= Q4 = Q5 =Qa -Q? = Qs =
Qo = “O” level, Q, o=== @+ i
77 level, for example, Qr = Q3 = Q10-"
l” level, Q2 = Q4 = Q5 = Qa =
Q? = Qs = Q9 = “0” level.

In this way, in the conventional counter circuit, in order to measure the time that is, for example, 512 times the clock pulse signal, the state in which the Q output signal Q+o of the last stage F, Flo changes from the ``0'' level to the 1'' level is detected. If you do so, you will end up measuring a larger amount of time than the correct time.

That is, the conventional counter circuit has a drawback that it cannot accurately measure time.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to calculate the internal state of a plurality of binary counters that are cascaded with multiple inputs before counting rank pulse signals and measuring a predetermined time. It is possible to accurately measure time by setting the initial state of multiple binary counters by counting clock pulse signals corresponding to the delay time from the first binary counter to the last binary counter when the binary counter is continuously inverted. The purpose of this invention is to provide a counter circuit that can

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the counter circuit of the present invention.

Here, a counter circuit for measuring a time corresponding to 512 times the clock pulse signal as in the conventional case will be described.

In Fig. 2, 10' to 1G are F, F, which are successively connected in multi-stage cascade so that the Q output signal of the previous stage becomes the synchronization signal of the latter stage.
(flip-flop).

The silkworm output signal gold of each of these F, F10' to F19'.

- Silkworm, 9 is fed back to each D (data) input terminal.

That is, each of the above F and F10' to F19' has a function as a binary counter.

Further, a preset signal 5P-8 is supplied in parallel to the S (set signal) input terminals of each of F and F1σ to 18'.

That is, the Q output signal Q to of each F, F1σ to 1g
-Q t s all go to the 'l' level after the preset signal 5P-8 supplied to the S input terminal goes to the 'l' level.

Also, OR gate 2 is connected to the S input terminal of F and F19' in the last stage.
0 is supplied with the preset signal 5P-8, and the Q output signal Q19 of F and F19' is supplied with the preset signal S
After P and s reach the nl'' level, the level becomes t11$.

Also, through the OR gate 20, the F of the last stage, the S of F19'
A measurement start signal ssg is supplied to the input terminal, and F, Fl9
Q output signal Q19 of this measurement start signal SSU is "1"
After rising to the "In" level, the "In" level is reached.

The preset signal 5P-8 is also supplied to an AND gate 22 via an inverter 21.

This AND gate 22 includes the plurality of F, F1σ~1
Q output signal Qt9 of the last stage F of 9', F19'
is supplied, and clock pulse signals Sc and P are also supplied.

Furthermore, the output signal of the AND gate is
, F10' to F19 at the first stage, and is supplied to the φ (synchronizing signal) input terminal of F1σ as a synchronizing signal Sφ.

Next, the operation of the circuit configured as described above will be explained with reference to the time chart shown in FIG.

First, as shown in FIG. 3, a clock pulse signal 5o-P of a constant period is input to the AND gate 22.

At this time, the preset signal Sp-s, the measurement start signal SS
B is "In level", ""0"0, respectively, as shown in Figure 3.
″ level.

Since the preset signal 5P-8 is "1" level, each F and F1σ to 1g are all set.

That is, all Q output signals Q1o-Q19 are at active level (n11 level).

Furthermore, since the output signal of the inverter 21 is at the f'□n level at this time, the logic of the AND gate 22 is not established and its output signal is at the et(Tt level).

Next, the preset signal 5P-8 is inverted to 0'' level.

After this, the output signal of the inverter 21 becomes "1" level.

At this time, the Q output signal Q19 of F and F19' is already "1".
99 level, the AND gate 22 outputs the synchronizing signal Sφ having the same phase as the supplied clock pulse signal 5o-P.

Before this, the internal states of each F, F10' to F19' are all at the "°1" level, that is, the counter is in a full count state, so the first synchronization signal Sφ from the AND gate 22 is sent to the first stage F, F1σ. When inputted to the φ input terminal, the internal states of each F, F10 to F19' are continuously inverted and all become ''0° level.

However, in reality, there is a propagation delay time in each F, F10' to F19', so the last stage does not start until the time has elapsed for several more synchronizing signals Sφ to be input to the φ input terminals of F and F10' in the first stage. The Q output signal Q19 of F, F19' is inverted to "O" level.

If, for example, there are four synchronizing signals Sφ input to the φ input terminals of F and F1σ in the first stage before the signal Qto is inverted to "0" level, the synchronizing signal Sφ is as shown in FIG.
Q output signal Q19 of F, F19' at the time after the fourth shot of
is inverted to "0" level.

At this time, each F, F10' to 19' niha, each F, F1o'
~19' F, F of the first stage when the internal state is continuously inverted
The number of synchronizing signals Sφ corresponding to the transmission delay time from 10' to the last stage F and F19' (four) is counted.

In other words, only the Q output signals of F and F12' are at "L" level, and all the Q output signals of other F and F are "0".
level.

As a result, the initial value (4 in this case) of the counter circuit is set in consideration of the transmission delay time in each of F and F1σ to F19'.

Next, when actually measuring a time 512 times that of the digital pulse signal 5o-P, the measurement start signal SsR is set to the 1'' level as shown in FIG.

After this, through the OR gate 20, the last stage F, F19'
The measurement start signal SsR of "L" level is input to the S input terminal of F, F19', and the Q output signal Qt9 of F, F19' becomes "L" level again.

After the Q output signal Q19 of F, F19' becomes L'' level, the AND gate 22 outputs the synchronization signal Sφ having the same phase as the clock pulse signal 5O-P.

After that, each F, F10' to F19' sequentially counts the synchronizing signal Sφ input from the AND gate 22, and after counting 508 synchronizing signals Sφ, which is 512 minus the initial value 4, the last stage F, Q output signal Q of F19'
19 will be inverted to "0" level.

Now, when 507 synchronization signals Sφ are counted, F, F
The Q output signals of 1σ to 18' are all at the "°1" level.

Also, since the Q output signals of F and F19' at the last stage are already at the level of °1''1'', at this time F and F1σ~19
' is in full count state.

Next, when the 508th 0 synchronization signal Sφ is input to the first stage F and F1σ, the internal states of F and F1σ to 19' are successively inverted.

The time from when the states of F and F1σ in the first stage are reversed until the state of F and F19' in the last stage is reversed corresponds to the transmission delay time, which corresponds to four shots of the signal Sφ. Therefore, when the Q output signals of the last stage F and F19' actually invert to the "0" level, a total of 508th + 4th = 512th synchronization signal Sφ will be input to the first stage F and F1σ. Become.

In other words, from the full count state, the next Q of F, F19'
The transmission delay time until the output signal Q19 is set to the "0" level is corrected by the set initial value of the counter circuit.

Therefore, after the measurement start signal SSR reaches the "1" level, the Q output signal Q19 of F and F19' reaches the 0" level in exactly 512 times the clock pulse signal, excluding the inversion quantization error. Become.

Then, after the time of l clock pulse signal x 512 (
After T1), the logic of the AND gate 22 is not established, and the supply of the synchronizing signal Sφ to the first stage F and F10' is stopped.

Furthermore, at this time, since the transmission delay time corresponding to the clock pulse signal within the period T0 is counted as a digital quantity in F and F1σ to 19', the measurement start signal SsR is only input when measuring the next time. Then, the time 512 times the clock pulse signal can be accurately measured again.

Furthermore, since it is not necessary to know the transmission delay time of each F and F10' to 1g in advance, there is no need to design each F and F1σ to 19' to minimize the transmission delay time.

Moreover, since the period for setting the initial state of each F, F10' to F19' and the period for measuring time need only be under the same environmental conditions, there is almost no error in measurement time due to transmission delay time due to temperature changes and aging. becomes negligibly small.

The present invention is not limited to the above-mentioned embodiment. For example, in the above-mentioned embodiment, a case has been described in which F and F are connected in cascade in 10 stages to measure a time 512 times as long as the clock pulse signal. The number of F may be limited to 10 stages, and in short, it is sufficient as long as it measures the time of an integer power of 2 of the clock pulse signal.

As explained above, according to the present invention, before measuring a predetermined time, when the internal states of a plurality of binary counters connected in cascade in advance are continuously inverted, from the first stage binary counter to the last stage binary counter Provided is a counter circuit that can accurately measure time by counting clock pulse signals according to the delay time leading to the delay time and setting the initial state of a plurality of binary counters, and then counting a predetermined time. can.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional counter circuit, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a time chart for explaining the above embodiment. 10'~19'...Flip-flop, 20.
...or gate, 21...inverter,
22...and gate.

Claims (1)

[Claims] 1. The first to first stages are connected in cascade in multiple stages so that the output signal of the previous stage becomes the synchronization signal of the subsequent stage, and the internal state is made active by supplying a preset signal.
, -1)th stage binary counter, and the above (n-1)th stage binary counter.
an nth stage binary counter whose internal state is activated by supplying the output signal of the stage binary counter as a synchronization signal and supplying the preset signal or the measurement start signal; a gate circuit that controls supply of a clock pulse as a synchronization signal to the first stage binary counter according to the logic state of the output signal of the nth stage binary counter;
The number of clock pulses corresponding to the signal delay time from the first stage binary counter to the nth stage binary counter when the internal states of the first to nth stage binary counters are continuously inverted. A counter circuit characterized in that the initial states of the first to n-th stage binary counters are set by counting by each of the binary counters.