JPS5945262B2 - Frequency divider circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency divider circuit, and particularly to a frequency divider circuit that has a small number of elements, can operate at high speed, and is suitable for being configured in an analog integrated circuit.

A frequency divider circuit is a circuit device that obtains from an input (clock) of a certain frequency an output of a frequency that is an integer fraction of the input (clock).

This consists of a J, type or T type flip-flop.

In addition, the configuration of the logic circuit that realizes these flip-flops is DCTL, DT, etc. in the case of bipolar integrated circuits.
There are L, TTL, ECL (CML), etc.

On the other hand, with advances in digital technology and integrated circuit technology, digital technology is increasingly being used in conventional analog signal integrated circuits.

Examples include synchronization circuits in color television receivers and video tape recorders.

These include synchronization circuits for vertical synchronization, horizontal synchronization, color synchronization, etc., and these synchronization signals are synchronized with each other at a certain frequency ratio.

Therefore, if digital processing technology is introduced into the synchronization circuit, each synchronization signal can be obtained using the clock of one source oscillation circuit, or in the case of a VTR, the PLL loop may be doubled to eliminate time axis fluctuations (speed deviations, etc.) during tape running. This makes it possible to increase the ability to remove the effects of wow and flutter.

When attempting to add a digital circuit to an analog signal processing integrated circuit such as a synchronous circuit integrated circuit, there are actually various constraints resulting from the manufacturing process, unlike digital integrated circuits.

When applying digital technology to integrated circuits typically used for synchronization signals, frequency divider circuits play an important role.

As an application example of a frequency dividing circuit, if we take the color subcarrier regeneration circuit of a color television receiver as an example, the color subcarrier (3, 5
Color subcarriers with a phase difference of 90° are obtained from the original oscillation of four times the frequency (8MHz) through a quarter frequency divider circuit (14.3MHz).

Taking a video tape recorder as an example, the original oscillation (2,
The color subcarrier that is reduced from 75 MHz) by a 1/4 frequency divider circuit is also reduced to 15 MHz by a 1/175 frequency divider circuit.
．． By obtaining 75 KHz (horizontal synchronization frequency), it is possible to double the PLL loop and improve performance.

However, since these frequency divider circuits are constructed on analog integrated circuits, if the power consumption and the proportion of the chip area are not sufficiently small compared to the analog part, this will cause a reduction in functionality and an increase in cost.

Furthermore, the configuration of the logic circuit is limited to a bipolar type.

In addition, digital bipolar integrated circuits are non-saturated EC
With the exception of L, gold diffusion is performed to reduce the carrier accumulation effect and eliminate parasitic element effects, but this is not preferred in analog integrated circuits because it reduces the current amplification factor in the low current region of the transistor.

Without gold diffusion, TTL structures have many problems.

On the other hand, DCTL and DTL have no structural problems, but because they do not diffuse gold, they have a long carrier life and a considerably long storage time.

On the other hand, ECL does not have such problems, but it inherently has a large number of elements and is limited to one or two stages of binary counters.

When trying to realize a higher number of stages, DCTL, D
It has no choice but to use TL or other circuits, but since both methods use transistors in saturated state, the integration time is quite long in analog integrated circuits that do not use gold diffusion.
The maximum frequency of the frequency divider circuit is limited to about 1 to 5 MHz,
What can be easily realized is IMHz or less.

An object of the present invention is to provide a frequency divider circuit which has a small number of elements, is capable of high-speed operation, and is suitable for being configured in an analog integrated circuit.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of a frequency dividing circuit according to the present invention.

In the figure, transistor Q1. Q2 constitutes a self-holding circuit, whose common electrodes, emitters, are connected in common, output electrodes, collectors, are connected to the power supply VS through resistors R8, and furthermore, the base, which is a control electrode, and the collectors are connected together. Cross-connected.

This transistor Q1. A transistor Q3 controlled to operate complementary to Q2 as described below.
, Q4 are provided.

The emitters of these transistors Q3, Q4 are commonly connected, the collectors are interconnected to the collectors of the transistors Q, , Q2, and the bases are connected to the transistors Q8, . Interconnected to the collector of Q9.

The transistor Q1. Transistors Q5 and Q6 are provided to operate Q2 and Qa and Q4 in a complementary manner.

This transistor Q5. Q6 has its emitters connected in common to transistors Q7. are connected to a current source consisting of a resistor RE, and whose collectors are connected to the common emitters of the transistors Q1, Q2 and the transistors Q3, . Connected to the common emitter of Q4.

Then, an input voltage v1 is applied between the bases to operate differentially.

Note that it is desirable to insert a normal resistor γ into the emitter of the transistor Q6 as described later.

The base of the transistor Q7 constituting the current source is connected to the power supply Vs via a resistor RB, and two diodes D1. : D2 is provided, and the cathode of the diode D20 is grounded.

These resistors RB diode D1. D2 constitutes a bias circuit.

On the other hand, a completely similar circuit is constructed symmetrically to the circuit configuration described above.

That is, a self-holding circuit is formed by the transistor Q8゜Q, and the transistor pair Q1 operates in a complementary manner to the self-holding circuit.
o y Qll is provided.

However, this transistor Q1o. The bases of Qll are each interconnected to the collectors of said transistors QLjQ2.

These transistors Q8. Transistor Q12 operates differentially according to input voltage v1 to operate Q9 and transistors Qlo and Qll in a complementary manner.
, Qls are provided.

Incidentally, a current source constituted by a transistor Q14 and a resistor E is connected to the emitters of the transistors Q12 and Qlg.

This current source is provided in parallel with the current source constituted by the transistor Q7 and the resistor RE.

Furthermore, a resistor γ is provided at the base of the transistor Q12 in the same manner as described above.

Next, the operation of the present invention will be explained with reference to FIG.

Time t.

Since v, (input) is positive in , transistor Q5
, Qa and Q125 Q12 of the differential amplifier constituted by Qla are conductive.

Therefore, transistor Q5, Qa y Q12 y Q
Of the transistor pairs with common emitters connected to the collector of la, only Q15Q2, Qlo, and Qll are in operation.

Transistor Q1. Q2 has two stable states, but it is assumed that in to, the transistor Q1 is on.

In that state, the collector voltage v3 of the transistor Q2 is equal to the power supply voltage: vs (hereinafter referred to as high level).The collector voltage v2 of the transistor Q1 is only a voltage drop from the power supply voltage VS by the product of the collector current of the resistor R6 and the transistor Q1. It is at a dropped potential (hereinafter referred to as low level).

On the other hand, in the transistor pair Q1o y Qll, the base of the transistor QIO is at a high level and the potential of Qll is at a low level, so the transistor Q1o is conductive, and the collector voltage V4 of the transistor Q8 is set to a low level, and the collector voltage V5 of the transistor Q is set to a high level. level.

Transistor Q8. Q9 is off. Next time t1
Consider a state in which the input voltage V1 suddenly reverses to negative.

In that state, transistor Q5. Q12 is off and Qa
y Qls turns on.

Therefore, the transistors Q1o and Q11 are turned off, but at the same time, the self-holding circuits of the transistors Qs and Qo are turned on to keep the voltages V4 and V5 in the same state as before, so that the low level and high level states are maintained, respectively.

On the other hand, voltage V25 V3 is applied to transistor Q1. The self-holding circuit of Q2 turns off and transistors Qs and Q4 enter the operating state, but the base of transistor Qa is at a low level and Q
Since the base of 4 is at a high level, it is reversed.

Below, at time t2, voltages V22 and V3 are held,
V4-V5 is reversed and at time t4, the voltage is V43V
5 is held and V25 V3 is reversed.

Therefore, as shown in FIG.
An output with a frequency of 1/1 is obtained.

Next, the features obtained by the present invention will be explained.

The binary counter according to the invention has a bias circuit (R
B, Dl, D2) and γ, which is essentially unnecessary, it is composed of 20 elements.

Furthermore, if necessary, Qla, Q14 and each RE can be connected in parallel to reduce the number of elements to 18.

Furthermore, when two or more stages are connected in series, a level shift is required between each stage, but even if approximately 5 elements are added for this purpose, one stage can be constructed with approximately 23 to 25 elements.

This is about one third of a binary counter using an ECL gate, and much less than TTL or DTL.

Also, very high speed operation is possible.

In FIG. 1, the current of Qla 3 Q14 constituting the current source is Dl.

The voltage drop (VD) of one diode of D2 is approximately R
It is determined by what happens to E.

Therefore, if RO is selected to be slightly smaller than RE (for example, about 70%), the base and collector junctions of transistors Q1 to Q8 will not be substantially conductive.

All transistors therefore operate in the non-saturated region.

Therefore, there is no accumulation effect and an operating speed close to ECL can be obtained.

Furthermore, since the operation is differential, the transition width is also relatively small, and the threshold value is O, which has very small variations and is located in the center of the transition width.

Therefore, there is no malfunction even if the logic amplitude is reduced, which is convenient for high-speed operation.

Furthermore, providing the input differentially and not depending on the common mode component is rather advantageous when configuring it in an analog integrated circuit, and the bias is also reduced.

Additionally, since they all operate differentially, the total current is always constant, and there is very little induction into other circuits due to common impedance such as the power supply.

As described above, according to the present invention, it is possible to obtain a frequency dividing circuit that has a small number of elements, is capable of high-speed operation, and is very suitable for being configured in an analog integrated circuit.

Next, the effect of the resistor γ connected to the emitter of Qa y Q12 in FIG. 1 will be explained.

Generally, frequency dividing circuits take pulses as input, but in analog signal systems, it is often desirable to frequency divide the output of a sine wave or triangular wave oscillation circuit.

In that case, there is no problem at relatively high frequencies, but at very low frequencies it becomes unstable because the transition time is very long.

The reason for this can be explained in Figure 1 as Q6 and Q1□
This is because they enter the active region at the same time.

In this case, transistor Q3. Since Q4 and transistors QIO and Qlt are turned on at the same time, a self-oscillation phenomenon peculiar to this frequency divider circuit occurs, and the previous state is erased.

On the other hand, as in the present invention, transistor Q6. Q1
When a voltage equal to the voltage applied to the bases of transistors Q5 and Qa is connected to the emitters of □, the current flowing through transistor Q is higher than the current flowing through transistor Q.
Similarly, when an equal voltage is applied to the base of transistor Q12゜Ql3, the current is set so that the current flowing through transistor Q12 is smaller than the current flowing through transistor Q13. .

In this case, for example, transistors Q5jQ12 are turned on, transistors Q6 . When an input voltage v1 with a polarity that crosses Q13 is applied to the input terminal, transistor Q6 is immediately turned off, but transistor Q12 is
It becomes difficult to turn on.

Therefore, transistor Q6. Q12 will no longer be turned on at the same time, and the above-mentioned problem will be solved.

In this case, as transistor Q5 turns on, transistor Q1. The self-holding circuit of Q2 is turned on and voltages V25-V3 are kept at their previous state, while this causes the state of voltages V42-V5 to be reversed.

Conversely, transistor Q65Q13 is on, Q5゜Q1
When an input voltage v1 that turns off transistor Q1 is applied, transistor Q1 turns off immediately, but transistor Q
These transistors Q6.6 are difficult to turn on.
Q1□ will no longer be turned on at the same time.

In this way, transistor Q6. By inserting a resistor r into the emitter of Q1□, the transistor Qa5 in the transition region
The current of Qt 2 can be reduced, stability can be improved, and low frequency sine waves and triangular waves can be divided without waveform shaping.

[Brief explanation of the drawing]

FIG. 1 is a drawing for showing an embodiment of the present invention, and FIG. 2 is a drawing for showing the operation of the present invention. Ql, Q2...first common emitter transistor pair, Q8. Q9... Second common emitter transistor pair, Qlo, Q1□... Third common emitter transistor pair, Q3, Q4... Fourth
common-emitter transistor pairs, Q5, Q6 and Ql
2 y Qla...Differential amplifier.

Claims (1)

[Claims] 1. A first and second transistor pair whose control electrodes and output electrodes are cross-connected and whose common electrodes are commonly connected to each other to form a self-holding circuit, and each control electrode is connected to the first transistor pair. The state of the first transistor pair, which is connected to each output electrode, and whose output electrode is connected to each output electrode of the second transistor pair, and whose common electrodes are commonly connected to each other, is transferred to the second transistor pair. a third pair of transistors to transfer, each having a respective control electrode connected to a respective output electrode of the second transistor pair and having an output electrode connected to each output electrode of the first transistor pair and having a common The state of the second transistor pair whose electrodes are commonly connected to each other is the first state.
a fourth transistor pair for transferring to the transistor pair;
a first current source having a respective output electrode connected to a common electrode of the first and fourth transistor pairs, a control electrode connected to the first and second input terminals respectively, and a common electrode connected to a first current source; The output electrodes of the first and second transistors and the third and second transistor pairs are connected to the common electrodes, and the control electrodes are connected to the first and second input terminals, respectively. third and fourth transistors connected to the second current source;
means for setting a current such that the current flowing through the second transistor is smaller than the current flowing through the first transistor when voltages applied to control electrodes of the first and second transistors are equal; and means for setting a current so that the current flowing through the third transistor is smaller than the current flowing through the fourth transistor when the voltages applied to the control electrodes of the fourth transistor are equal. circuit.