JPS5944693B2 - Abnormal data erasing device for magnetic tape storage devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an abnormal data erasing device that can prevent noise blocks from being mixed into a magnetic tape storage device by appropriately switching the reading head to the erasing head.

Currently, magnetic tape storage devices are often used to store and exchange data when processing information using computer systems, but the reliability of magnetic tape storage devices is limited by scratches on the magnetic tape and problems that cannot be completely erased. It is greatly influenced by so-called noise blocks caused by previous data, etc.
As a result, a situation occurred in which it became impossible to reuse important information.

In a conventional magnetic tape storage device, the information structure on a magnetic tape is such that data blocks in which a certain number of data or more are recorded and interblock gaps (IBG) in which nothing is recorded are arranged alternately. Three types of heads are arranged in the order shown in the figure, namely an erase head E connected to an erase current supply circuit ec, and a data write circuit w.
rc, and a read head R connected to a data read circuit rc.

Note that T is a magnetic tape running in the direction of the arrow. The conventional method of avoiding the above-mentioned noise blocks is to erase the old data previously written by the erasing head E as the magnetic tape T travels during data writing, and then erase the old data previously written by the erasing head E. After writing new data to the magnetic tape T using Either the data is rewound and rewritten, or the entire transferred data block is erased and the next section is newly written. However, with this method, if the threshold for determining whether or not changes in the magnetic flux density on the magnetic tape are judged as data changes, or if the running speed of the magnetic tape changes, the magnetic flux density that was not detected during writing may change. When a change is read, a situation may occur where the change is read as abnormal data. Furthermore, it has not been possible to handle the abnormality of the noise block that occurs after the write operation is completed. Furthermore, conventional magnetic tape storage devices do not have a function to erase the noise block other than when writing, and it is difficult to reliably erase only a specific block. Normal data input was sometimes impossible even if the data block was not destroyed. The present invention has been made in view of the above circumstances, and allows the read head, which was conventionally used only for reading data, to also be used as an erase head, and by switching to the functions of both heads at an appropriate timing,
In addition to writing, the IBG portion is repeatedly erased to prevent the noise block from being mixed in and to enable normal data block reading. The details of the present invention will be explained below with reference to FIG. 2 showing one embodiment thereof.

In the figure, 1 is a decoder circuit, 2 is a timing control circuit, 3 is an erase current generation circuit, 4 is a transfer control circuit, 5 is a data block end detection circuit, 6 is a noise block detection circuit, 7 is an inverter, and 8 is an AND 9 is a readout circuit, and 10 is a switching circuit. The read circuit 9 is a circuit that determines the change in magnetic flux density on the magnetic tape detected by the read head R as data and transfers it to the magnetic tape storage device control section X. The circuit within the broken line in the read head section Y is a circuit newly added according to the present invention, and a switching circuit 10 receives a signal from the control section X and supplies an erase current to the read head R for erasing the magnetic tape. VR, +VR2 in the read head section Y are power supplies required for the read operation of the read head R, C is a capacitor for removing DC components, D is a diode, Rl, R2, and R3 are resistors, and E is erased in the read head R. A power source that supplies current, Tr, is a transistor that controls erase current. 3 and 4 show the timing of each signal when controlling the magnetic tape storage device shown in FIG. 2. FIG. In other words, FIG. 3 shows the various signals that the magnetic tape storage device receives from the computer (CPU), for example, and starts running, until the running speed of the magnetic tape reaches a preset value and starts reading data. Indicates the timing of When the read operation instruction signal a from the CPU becomes logic 1'', the operation instruction is decoded by the decoder circuit 1 of the magnetic tape storage device control section X.

A timing control circuit 2 is operated by the output signal of the decoder circuit 1, and at the same time, an erase current generation circuit 3 is operated in response to the read operation command. The erase current generating circuit 3 sets the signal b, which instructs to supply the erase current to the read head R, to logic '1'.The signal g output from the noise block detection circuit 6 becomes logic when the read data block is a noise block. If it is not a noise block, the signal g is logic 0", so it is inverted to logic 1" by inverter 7 and input to AND circuit 8. Since the AND circuit 8 performs the logical product of the signal b from the erase current generating circuit 3 and the signal g, the output signal c becomes logic 11. The switching circuit 10 converts the signal c to logic S.
1'', an erase current is supplied to the read head R to start the erase operation.Meanwhile, the timing control circuit 2 instructs to drive the magnetic tape running motor (not shown) at time t1 after decoding the above operation command. Then, at an appropriate time T3 after the time T2 when the running speed of the magnetic tape reaches the set value, it acts on the erase current generating circuit 3 to change its output signal b to logic ``O''. Therefore, at this time T3, the above-mentioned erasing operation by the read head R is completed. Furthermore, after time T3 has elapsed, the timing control circuit 2 sets the output signal d to logic 1''. Therefore, when the tape runs at a constant speed, the readout circuit 9 outputs the signal d.
becomes logic "1" and starts reading data from the magnetic tape using the read head R, and transfers the read data to the CPU via the transfer control section 4. In FIGS. 3 and 4, SP represents the running speed of the magnetic tape. As can be seen from the above explanation, in the present invention, the running speed of the magnetic tape does not reach the set value from the part that was in contact with the read head R when the magnetic tape was stopped, so a reliable error check by the read operation cannot be guaranteed. An erasing operation is performed by the read head R over the range on the magnetic tape (that is, from the rise to the fall of the signal c). FIG. 4 shows the timing of each signal until the controller X detects the end of a data block during data reading, stops running the magnetic tape, and finishes executing the read operation command from the CPU.

In the operation shown in FIG. 4, the read circuit 9 shapes the data read from the read head R and transfers the output signal e to the transfer control circuit 4 and the noise block detection circuit 6. The transfer control circuit 4 transfers the read data to the CPU, and also outputs the read data to the data block end detection circuit 5 in order to detect the end of the data block. When the data block end detection circuit 5 detects the end, it becomes logic 1.
The output signal f is outputted to the timing control circuit 2, the erase current generation circuit 3, and the noise block detection circuit 6. The noise block detection circuit 6 determines whether the block input from the readout circuit 9 is a normal block or a noise block.
When the data reading is completed and the output signal f of the data block end detection circuit 5 becomes logic 1'', if the data is a noise block, the output signal g of the noise block detection circuit 6 becomes logic 1''. "become. The timing control circuit 2 starts generating a timing signal for completing the read operation when the output signal f of the data block completion detection circuit 5 becomes logic 1'', and the erase current generation circuit 3 starts generating the timing signal for completing the read operation. The output signal b under the control is logic ゜1''
Make it. If the data read by this operation is a normal data block (timing waveform A in Figure 4),
Since the input signals B and g of the AND circuit 8 are both logic 1", its output signal c becomes logic 1", and the switching circuit 10 operates, thereby changing the read head R from the read operation to the erase operation. The IBG can be erased from immediately after the data block to the part where the read head R is in contact with the magnetic tape when stopped. If the read data is a noise block (timing waveform B in FIG. 4), the output signal of the inverter 7 becomes logic 0I, so the AND condition of the AND circuit 8 cannot be satisfied and the erase operation is not performed. This means that when a normal data block exists immediately after a noise block, when the end of the noise block is detected, a brake is applied to the running of the magnetic tape, but by the time it stops, the normal data block has reached the read head position. This is because there is a possibility that the data may pass through, and therefore, the erasing operation cannot be performed in general. In FIG. 4, time T4 is the time when the travel motor is braked after creating an IBG of a specified length, time T5 is the time when the magnetic tape stops, and T6 is the time when execution of the read operation command from the CPU ends. It is. As is clear from the above, according to the present invention, the erasing operation, which was conventionally performed only when writing data, can be performed by using the reading head to detect the data block until the tape runs at a constant speed when reading data or when it stops. Erasing can be reliably performed until it stops, and at the same time, by repeating this read operation, it is possible to erase noise that has occurred after data has been written on the magnetic tape.

Furthermore, when information is exchanged between two or more magnetic tape storage devices, changes in the magnetic flux density within the IBG that do not result in an error in one device are detected as noise blocks in the other device due to differences in the characteristics of each device. It is possible to eliminate factors that prevent smooth information exchange.

[Brief explanation of the drawing]

FIG. 1 is a simplified layout diagram of heads in a conventional magnetic tape storage device, FIG. 2 is a circuit diagram of an abnormal data erasing device for a magnetic tape storage device of the present invention, and FIGS. 3 and 4 are various timing diagrams of the present invention. It is a diagram. 1: Decoder circuit, 2: Timing control circuit, 3: Erase current generation circuit, 4: Transfer control circuit, 5: Data block end detection circuit, 6: Noise block detection circuit, 7 Reinverter, 8: AND circuit, 9: reading circuit; 10: switching circuit; E: erasing head; R: reading head; T: magnetic tape; W: writing head;

Claims (1)

[Claims] 1. In a magnetic tape storage device in which information on a magnetic tape used as a recording medium consists of data blocks and interblock gaps, a read head and a circuit that supplies an erase current to the read head to operate as an erase head; A switching circuit that activates this circuit and switches the read head to erase mode, a detection circuit that receives a signal from the read circuit of the read head and detects the end of a data block, and an operation command signal that instructs to read data. The switching circuit operates the switching circuit for a predetermined period of time until the tape running speed reaches a constant speed in response to the detection circuit, supplies the erasing current to the read head, and operates the switching circuit for a predetermined period of time until the tape stops in response to the output of the detection circuit. and control means for activating the erase current and supplying the erase current to the read head.