JPS594227A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To reduce the pattern area to about a half in comparison with that of a conventional similar D/A converter, by operating an output voltage level shift circuit using an insulation gate field effect transitor(TR) as a constant current source. CONSTITUTION:A voltage VO2 of an output terminal O2 of the D/A converter circuit is converted linearly into VI-VDD corresponding to digital inputs a10- a1. The resistance value of a resistor 60 is selected to a value biasing the voltage VO2 to (VDD+V1/2) when the digital input is a digital quantity 0. E-n-MOSTs 31-40 operate at the saturating region as the constant current sources. An output voltage level shift circuit 70 controls a gate voltage VGS when the E-n- MOSTs 31-40 being the constant current source are selected by the digital inputs a10-a1. Thus, the pattern area is reduced by the area of the depletion TRs in comparison with a conventional D/A converter, and even if the number of bits of digital inputs ai is increased, the pattern area is reduced to about a half.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital-to-analog converter, and more particularly to a digital-to-analog converter (hereinafter referred to as D/A converter) using an insulated gate field effect transistor (hereinafter referred to as MOST) as a constant current source. converter circuit). - A conventional D/A converter circuit of this type is shown in FIG. 1. FIG. 1 is a circuit diagram showing a conventional D/A converter circuit. This circuit shows a T)/A converter circuit using a 10-bit n-channel MO8T (hereinafter referred to as n-MO8T). In FIG. 1, 1 to 10 are enhancement type n-type MO8T (hereinafter referred to as F, -n-MO8'
lr), each train electrode is connected in parallel to the output terminal 01, and each gate electrode receives a digital input signal a10.
1 each of a9 to a1 is input. E-n-MO8T,
~1o source' electrodes each have a depletion type n-type M
O8T, 1-20 (hereinafter referred to as D-n-MO8T)
The drain tl& of is connected. D-n-MOS
Each gate and source electrode of T, 1 to 2o is connected to V, (GND
) is grounded. Resistor 50 is on one side or power supply ■DD,
The other terminal is connected to output terminal 01. Here, the potential of "DD" is +5 V, and V88 is ()ND low level.

FIG. 2 is a diagram illustrating the operation of the D/A converter circuit shown in FIG. 1 above. To explain the operation of FIG. 1 using FIG. 2, the D/A converter circuit of FIG. 1 has a 10-bit digital input signal a1G+79 to 11.
It has a resolution of 210-1.

As shown in FIG. 2, alo is sign pitch), a.

is the largest bit (Most 51gn1ficant b
it: MOB), a.

is the least bit (Least 51gn1ficant
bit: LHS), and ai is the inverted signal of the digital input signal ai. In a conventional D/A converter circuit using a constant current source method, the current value of LSBal 1
1 is ΔV ■ = □ ・ (11' 10
24 x R5°. However, ΔV is the output voltage V. This is the difference between the Max value and Min value of 1. Also, the current value Ii of the constant current source (corresponds to the digital input amount, so I, +1 = l
1X2 = (IH-1X2)X2 = I, X2'
−(21). Therefore, the output voltage V.

1 is 'V. , =IL5ox(I, xd, +l2xd2
+,,,,,,+I,xd9+I,oxd,o)=R6
ox(I, xd, X2°+I, Xd2X2'+-, +i
,Xd,X28+I,xd,. x2')=l(,.×I
, x'; diX 2'-' -131
[Represented as ri1. Here, di is the digital input signal a.
(rlJ or rOJ). As described above, the constant current source Ii and the output voltage V are set. The relationship 1 holds true.

In Figure 2, the digital input signal is a digital quantity 0.
When (alo + ``g + ''' r aI
) ”” (0+0,...,0)=(1,1,-,1)
At this time, the voltage at output terminal 01 is biased to 4.75 V. Also, (a, ., R9゜...+ "1)" (1+0
+・= r O), output terminal 01 or minimum value 4.5
To V, (JO+ ag +...+a1)"(0+1,...
..., in the case of 1), the output voltage V with respect to the digital input signal so that the output terminal O□ reaches the maximum value of 5V. 1 or
It changes into a linear analog quantity from 45V to 5V. To perform the above operation, resistor 50 has a resistance value R5o that can be biased to 4.75V.

D-n-MO8T is in the saturation region as a constant current source! 1
~20 and D-n-MO8T- is D-n-MO8T
The geometric ratio W (channel width)/L (channel length) of the transistor must be considered so that the condition of the above equation (2) is satisfied for i+t (i=1 to 19).

Typically, D -n -MO8Ti+x channel @ wi
+1 is a large plate size that is approximately twice the channel width W of Dn-MO8T. E-n-MO8T1 to 1o are connected to constant current sources D-n-MO8 by digital human input signal a10''aI.
'f11 to 2o, and in order to operate in the saturation region, D-n-MOS T1. ~2o sauce・
Drain voltage ■Ds or D-n-MO8T, 1~2o
For the pinch-off voltage ■2, ■D8〉VP, ■D8-β(-VP)2- +41
F, -n -MO8'1' so that the condition of
, ~1° must be made sufficiently large.Also, normally for E-n-MOS Tk+, the channel width Wk+1 is equal to the channel width Wk (k=1~1°) of E-n-MOS Tk. It is about twice the size of 9).

Therefore, in the conventional D/A converter circuit configured as described above, as the number of bits of the digital input signal ai increases, that is, as the precision becomes higher, the pattern area of the D/A converter circuit increases. There was a drawback to that.

The present invention was made in order to eliminate the drawbacks of the conventional tags as described above, and the other end of a resistor whose one end is connected to a first power supply is used as an output terminal, and n (n) tags are connected to the output terminal. : an integer) are connected to the drain electrodes of the n insulated gate field effect transistors, the source electrodes of the n insulated gate field effect transistors are connected to the second source, and the gate electrodes are connected to the output terminal of the output voltage level shift circuit. and an n-bit digital input is input to an input terminal of the output voltage level shift circuit, and the output voltage level shift circuit operates the insulated gate field effect transistor as a constant current source. This type of D/A has a configuration in which it is possible to obtain an analog voltage for the n-bit digital input.
It is an object of the present invention to provide a D/A converter circuit whose pattern area is reduced to about 1/2 or less compared to a converter circuit.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit diagram showing a D/A converter circuit according to an embodiment of the present invention. This circuit has a 10-bit digital input and is a D/O using an E-n-MO8T.
A converter circuit is shown.

In Fig. 3, each drain electrode of E-n-MO8T3□~4o is connected to the output terminal 02, each source electrode is grounded to VS2 (OND) which is a second voltage source, and each gate electrode is connected to the output voltage level. Output terminal 01~ of shift circuit 7o
Each is connected to C1o. Digital inputs a1o, a9-a1 are input to the input terminals b1-b10 of the output' voltage level shift circuit 70, respectively.

In addition, the bias resistor 60 is connected to the power supply vDD, which serves as the first fi source.
One side is connected to the output terminal 02, and the other side is connected to the output terminal 02.

Next, one embodiment of the present invention shown in FIG. 3 above, I)/
The operation of the A converter circuit will be explained.

In the D/A converter circuit described above, as shown in FIG. 2, the voltage V at the output terminal 02 corresponds to the digital inputs a10' to a1. It is linearly changed into an analog quantity from 2 to 4.5V to 5V. Here, the resistor 6° has a voltage V when the digital input is digital ilO. 2 to 4.75 V
Select a resistance value that allows biasing. E-n-MO8T
31 to 4o operate in the saturation region as constant current sources, and En
M 08 T t is determined by taking into account the geometric ratio of the transistor, as in the conventional example, so as to satisfy the condition of equation (2) above.

The output voltage level shift circuit 7o is a digital human power a1
E −n −M OS ′ of the constant current source by 0”al
, ['3. -46, E-n-MOS
This is for controlling the gate voltage GS of T3 and -48. In order to operate E-n-MO8T3,~,0 in the saturation region, MO8-■tttl < vDS T
IDa = 2β(”as −Vtht)2−(5
J must be satisfied. However, VD8 is B-n
-MOS '1'31.40 (') TO' L/
The earth voltage, vthl, is the threshold value.

Gate voltage ■ that satisfies the above equation (5) by the output voltage level shift circuit 7o. 4 and 5 show specific circuit configuration diagrams of a D/A converter circuit including a 1-bit output voltage level shift circuit 70 for providing 8 bits.

In FIG. 4, which is the first specific example, the output voltage level shift circuit 70 is an E-n-MO with the same channel as the constant current source.
The E-n-MOS T8o inputs the digital input ai to the drain electrode, and the source electrode is connected to the 90 gate electrodes consisting of the E-n-MO8T constant current source, and the gate electrode is connected to the power supply ■DD. Normally conductive at the transfer gate connected to the E-n-MO
Using the threshold value vth2 of 8T8o and the bank gate effect, ■cs −vai −(■th++Δ■th2)−■D
D-(■1h2+Δ■thzΔ■1h2k(, layer q tribute V
, , l -i), and the condition of the above equation (5) can be satisfied by lowering the gate voltage . Where, vai is the input voltage of the digital input signal, V
thz is the threshold of E-n-MOS '1"8o,"
th is the fluctuation of the threshold value due to the back effect, k is the substrate constant, φ is the Fermi level 'h, and BG is the back gate voltage. Here, the channel width W of E-n-MO8T8o can be used if it is sufficiently small.

In FIG. 5, which is a second specific example, 81 has a source electrode connected to the power supply VDD, and a gate electrode connected to the input terminal.

, the drain' electrodes are connected to the output terminal f1, respectively.
-p channel type MO8T (hereinafter referred to as E-p-M08T), 82 is the source 1 [pole or V88 (GND), the gate electrode is the input terminal bi, the drain electrode is the output terminal f
E-n-MO8i'' connected to 1 respectively, 83 to source electrode or connection point 2, gate 1-'4 pole or output terminal f1
, E- connected to the drain electrode or output terminal f2, respectively.
p-MO8T, 84 is an E-n-MO8T whose source electrode is connected to 5s (GND), the gate electrode is connected to output terminal f1, and the drain electrode is connected to output terminal f2, 81, 82, 83 and 84 are connected to output terminal f2. Each pair forms a C-MOS inverter, and the output terminal f2 is connected to the output terminal Ci. 85 is a resistor connected at both ends to the voltage vDD and the connection point R1□, and 86 is the connection point. )(, □ and v8s(G
A third potential VR1□ is generated at the connection point R1□ by the resistance division of each resistor 85.86, which is connected at both ends to
Supply L/Verno potential. Further, digital human power ai is input to the input terminal, and the output terminal Ci is connected to a 910 gate electrode made of E-n-MO8T of a constant current source.

In the output voltage level shift circuit shown in FIG. 5 and configured as described above, the voltage V at the output terminal Ci is generated by generating the third potential VR1□ by resistance division of each resistor 85°86. i or the gate voltage V that satisfies the above equation (5). 8 can be supplied to the constant current source E-n-MO8T 91.Here, the channel width W of the E-MOS T can be used as long as it is sufficiently small.

As explained above, 1)/A which is one embodiment of the present invention
The converter circuit can be made smaller by the area of the depletion transistor compared to the conventional one in this building, and even if the number of bits of digital AI increases, the pattern area can be reduced to about 1/2 compared to the conventional one. It can be configured as follows.

Although the above embodiment has been explained using n-MO8T, it can be similarly applied to p-MOS T, and the bias resistor and third potential generation circuit can be used not only as passive elements but also as active elements of transistors. It is also possible to configure

Furthermore, in the above embodiment, the range of the fluctuating voltage of the analog voltage was set to 4.5V to 5V, but especially in this range,
There is no intention to be specific. By the way, the above fluctuation voltage ΔV
As the voltage increases, the linearity of the analog voltage will be impaired, and since the output voltage level is operated in the saturation region, the lower the output voltage level or the smaller the IVPl, the channel width W of the constant current source becomes narrower, and the pattern area becomes smaller. To avoid this, the fluctuation voltage Δ■ is set to 45 to 5 V.

As described above, according to the digital-to-analog converter according to the present invention, in a D/A converter circuit using an insulated gate t-'1 field effect transistor as a constant current source, the gate group of the insulated gate field effect transistor is , to the output terminal of the output voltage level shift circuit, and inputting an 11-bit digital input to the input terminal of the output voltage level shift circuit. By operating the field effect transistor as a constant current source, the analog circuit voltage for the n-bit digital input can be obtained.
Compared to the A converter circuit, the pattern area can be reduced to about 1/2 or less, and an extremely high precision D/A converter circuit can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional I)/A converter circuit, Fig. 2 is a diagram explaining the operation of the J)/A converter shown in Fig. 1, and Fig. 3 is a diagram of the present FIGS. 4 and 5 are circuit diagrams showing a D/A converter circuit according to an embodiment of the invention. FIGS. 4 and 5 are circuit diagrams of two embodiments showing specific circuit diagrams of the invention. 1~10.31~40,80.82,84゜" 90.
91...Enno-Acement type n-type P, R gate 11' effect transistor (E-n-MO8T), 1
1 to 20・・・・・・・・・Depression type n-type insulated gate field effect transistor (Dn −, hIos T
), 50, 60° 85.86... Resistance, 70... Output voltage level shift once K,
131.83・・・・・・En/Xement type p-type insulated gate field effect transistor (E-p-MO8
T). In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Makoto Kuzuno - Figure 1 Figure 3 Procedural Amendment (Voluntary) Commissioner of the Japan Patent Office 1, Indication of the case Patent Application No. 114263-1982 2
, 'R Ming (7) Name Digital-to-Analog Converter 3, Relationship to the amended person's case Patent applicant address 2-3 Sara-chome, Marunouchi, Chiyoda-ku, Tokyo Name (601) Representative of Mitsubishi Electric Corporation Hitoshi Katayama Hachibe 4, agent address Chiyoguchi, Tokyo] 2-3 Sara-chome, Marunouchi Ward
No. 5, Subject of amendment Detailed description of the invention in the specification, drawings. 6 Contents of correction fi+ The voltage of ``is 5VJ'' in the first line of page 3 of the specification is corrected to ``is a high potential.'' (3) [4,75V J on page 4, line 11 of the specification]
is "Vl", and "5■" on the 5th line of the same page is "■Du".
and "45■~5■" on the 16th line of the cylinder on the same page, [vI~V
DD J and J4.75VJ on the 5th line of the same page, (4)
[45V~5VJ on page 8, line 2 of the specification]
■DD'' and r 4.75 V'' (5
) r■tbJ on page 9, line 19 of the specification is changed to "Δ■th
2”. (6) "Bias" on page 12, line 4 of the specification is corrected to "bias". (In addition, on page 12 of the specification, lines 4-16,
It is something. ” to be deleted. (8) Amend Figure 2 of the attached drawings as per the attached sheet. Figure 2 → 1

Claims (1)

[Claims] The other end of the resistor connected at one end to the first power supply is used as an output terminal, and the drain electrodes of n (n: integer) insulated gate field effect transistors are connected to the output terminal, and the n insulated gate electric field The source electrode of the effect transistor is the second
connected to an IL source, a gate electrode connected to an output terminal of an output voltage level shift circuit, and configured by inputting an n-bit digital input to the input terminal of the output voltage level shift circuit, the output voltage level shift circuit and
A digital-to-analog converter, characterized in that an analog voltage for the n-bit digital input can be obtained by operating the insulated gate field effect transistor as a constant current source.