JPS5941274A - Printing method for dot-matrix printer - Google Patents
Printing method for dot-matrix printerInfo
- Publication number
- JPS5941274A JPS5941274A JP6591282A JP6591282A JPS5941274A JP S5941274 A JPS5941274 A JP S5941274A JP 6591282 A JP6591282 A JP 6591282A JP 6591282 A JP6591282 A JP 6591282A JP S5941274 A JPS5941274 A JP S5941274A
- Authority
- JP
- Japan
- Prior art keywords
- buffer
- address
- character
- control unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/22—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of impact or pressure on a printing material or impression-transfer material
- B41J2/23—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of impact or pressure on a printing material or impression-transfer material using print wires
- B41J2/30—Control circuits for actuators
Landscapes
- Dot-Matrix Printers And Others (AREA)
- Record Information Processing For Printing (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、ドツトマトリックス方式プリンタ印字方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a printing method for a dot matrix printer.
ドツトマトリックス方式のプリンタにて印字する場合、
マトリックス状の文字ドツトパターンを印字制御部のR
OM(リードオンリーメモリ)にもち、中央制御部より
文字情報及び印字情報としてJISコード及びコラム番
号等の情報を与え、それらより、ROM内の該文字が格
納されているアドレスを計算し該文字のドツト情報をf
gtり出す方式が通常用いられる。ただし、この方法で
は、印字へノドの移動方向が右方向、左方向にかかわら
ず印字をさせる場合(往復印字〕、回路で該文字のRO
Mアドレス又は印字パターンを方向の情報によって変換
する等の不便さがあった。その為回路が複雑化する傾向
があった。When printing with a dot matrix printer,
Print a matrix-like character dot pattern by pressing R on the print control unit.
Information such as JIS code and column number is given as character information and print information from the central control unit to OM (Read Only Memory), and from this information, the address where the character is stored in the ROM is calculated, and the address of the character is stored in the ROM. f dot information
The gt-out method is usually used. However, with this method, when printing regardless of whether the gutter is moving in the right or left direction (reciprocating printing), the RO of the character is
There were inconveniences such as converting the M address or print pattern based on direction information. Therefore, the circuit tends to become complicated.
また、ドツトマトリックス方式の印字制御は、印字部か
らのタイミングに同期して印字データ(ドツトパターン
)を印字部のヘッド駆動部に与えることを基本にしてお
り、高速になればなるほど印字制御部のデータ処理の時
間的余裕がなくなり、また、駆動パルスの時間々隔ある
いは、時間巾等の管理が複雑化する。このような処理の
欠点をさけるため従来のプリンタにおいては印字制御部
にDMA(ダイレクトメモリアクセス)方式の回路、あ
るいは、プリンタ制御専用のマイクロコンビーータ等を
もち、中央制御部と印字データの授受を行なう方法、ま
たは、中央制御部の処理内容のほとんどを印字部処理に
占有させる方法等が一般的であり、回路が複雑化、高価
になる、あるいは複数の入出力装置の同時制御を犠性に
しなければならないという欠点があった。In addition, dot matrix printing control is based on providing print data (dot patterns) to the head drive unit of the print unit in synchronization with the timing from the print unit, and the higher the speed, the faster the print control unit There is no time left for data processing, and management of drive pulse time intervals, time widths, etc. becomes complicated. In order to avoid the drawbacks of such processing, conventional printers have a DMA (direct memory access) type circuit in the print control section or a microconbeater dedicated to printer control, and exchange print data with the central control section. Or, most of the processing content of the central control unit is occupied by printing unit processing, which makes the circuit complicated and expensive, or sacrifices the ability to control multiple input/output devices simultaneously. The disadvantage was that it had to be done.
本発明は、これらの欠点を除去するものである。The present invention obviates these drawbacks.
具体的には、印字文字ドツトパターンを印字制御部内の
ROMにもち、中央制御部より該文字が格納されている
エリアの先頭アドレス(印字ヘッドが右方向に移動する
場合)、又は末尾アドレス(同じく左方向に移動する場
合)を指示し、印字タイミングに同期させてアドレス情
報塵させて、順次ドツトパターンをROMより取り出し
て印字する。その時、印字ヘッドの進行方向が右方向か
、左方向かによって、ROMアドレスをアップするかダ
ウンするか全決める。Specifically, the print character dot pattern is stored in the ROM in the print control unit, and the central control unit stores the start address (if the print head moves to the right) or the end address (in the same way) of the area where the character is stored. (in the case of moving leftward), address information is written in synchronization with the printing timing, and dot patterns are sequentially retrieved from the ROM and printed. At that time, it is determined whether the ROM address is to be moved up or down depending on whether the print head is traveling to the right or to the left.
この方法によれば、制御部より転送される情報がそのま
−JROMアドレスとなる為、回路が簡略化でき、安価
に構成することができる。According to this method, the information transferred from the control section becomes the JROM address as it is, so the circuit can be simplified and configured at low cost.
また、2バッファ方式を採用している為、中央制御部が
情報転送するタイミングに余裕を持たすことができ、複
数の入出力装置を同時に制御する場合有利となる。Further, since a two-buffer system is adopted, the central control unit can have a margin in the timing of information transfer, which is advantageous when controlling a plurality of input/output devices at the same time.
以下、本発明の一実施例を図面とともに説明する。An embodiment of the present invention will be described below with reference to the drawings.
第1図に、回路構成を示したもので、1に王メモリを含
む中央制御部、2は前段ノ(ノファ、3は後段バッファ
、4は文字パターンが入っていをROMを含むキャラク
タゼネレータ、5は中央市制御部1:に対して割込信号
全発生する智の割込コントローラ、6は印字部からの印
字タイミング等に従っテ前段バッファ2、後段バッファ
3、割込コントローラ6を制御するタイミングコントロ
ーラ、7はヘッド駆動回路を含む印字部であり、上記2
〜6で印字制御部を構成する。Figure 1 shows the circuit configuration. 1 is a central control unit including a main memory, 2 is a front-stage buffer, 3 is a back-stage buffer, 4 is a character generator containing a ROM containing character patterns, and 5 is an interrupt controller that generates all interrupt signals for the central control unit 1; 6 is a timing that controls the pre-stage buffer 2, post-stage buffer 3, and interrupt controller 6 according to the printing timing from the printing unit, etc. Controller 7 is a printing unit including a head drive circuit, and
to 6 constitute a print control section.
第2図は、第1図のキャラクタゼネレータ4内のROM
の文字パターン情報の記憶の様子及びアドレッシング方
法をモデル化したものである。Figure 2 shows the ROM in the character generator 4 in Figure 1.
This is a model of how character pattern information is stored and how it is addressed.
第3図は擬似9×7ドツトマトリノクス、40字/行の
プリンタの例で回路の動作チャートを示したもので、イ
、へは中央制御部1より印字制御部の前段バッファ2へ
印字文字情報を転送するタイミング、口は印字ヘッドを
動かすためのモータ:A−7信号%ハは印字ヘッドのホ
ームポジ/コン信号、二は印字ヘッドのワイヤ駆動用印
字タイミング、ホは印字制御部より中央制御部1への割
込タイミング、トハ前段バッファ2の内容、チは後段バ
ッファ3の内容を夫々示す。Figure 3 shows a circuit operation chart for an example of a pseudo 9x7 dot matrix printer with 40 characters/line. Timing to transfer information, 口 is the motor to move the print head: A-7 signal % C is the home positive/con signal of the print head, 2 is the print timing for driving the print head wire, E is central control from the print control unit 1 indicates the interrupt timing to section 1, 1 indicates the contents of the first stage buffer 2, and 1 indicates the contents of the second stage buffer 3, respectively.
次に本実施例の動作について説明する。Next, the operation of this embodiment will be explained.
まず、中央制御部1は、モータオンする直前に前段バッ
ファ2に第1番目の印字文字の印字情報、すなわちアド
レス情報塵1を中央制御部内のメモリから転送し、印字
ヘッドがホームポジションからにずれ、印字パルスが出
始める直前の割込タイミング信号(第3図、ホ)の前縁
で前段バッファ2より後段バッファ3へIr;、1情報
を転送し、後縁で中央制御部1へ割込みをかけ、中央制
御部1は、第2番目の印字情報爲2を前段・(ノファ2
へ転送する。後段バッファ3へ転送された虎1の印字ア
ドレス情報は、印字タイミングに)によってアップ又は
ダウンされ、キャラクタゼイ・レータ4内のROMの爲
1アドレスから規定のアドンス数を走査し、次々と嘔出
される文字パターンに、印字タイミングパルスに同期し
て、キャラクタゼネレータ4内で作られるヘッド駆動パ
ルスにより、印字部7に入力され、印字されていく。第
2番目以降も同様に印字されていく。割込タイミング(
(ホ)は、印字タイミング信号二を分周し1文字単位で
、タイミングコントローラ6によって作られる。First, the central control unit 1 transfers the print information of the first print character, that is, the address information 1, from the memory in the central control unit to the pre-stage buffer 2 immediately before turning on the motor, and the print head deviates from the home position. At the leading edge of the interrupt timing signal (FIG. 3, E) just before the print pulse starts to appear, information Ir;, 1 is transferred from the front buffer 2 to the rear buffer 3, and at the trailing edge, an interrupt is issued to the central control unit 1. , the central control unit 1 prints the second printed information 2 in the previous stage (nofa 2).
Transfer to. The print address information of the tiger 1 transferred to the subsequent buffer 3 is increased or decreased depending on the printing timing, and the specified number of addons are scanned from the address of the ROM in the character register 4, and the information is output one after another. In synchronization with the print timing pulse, the character pattern is input to the printing unit 7 and printed by a head drive pulse generated within the character generator 4. The second and subsequent numbers are printed in the same way. Interrupt timing (
(e) is generated by the timing controller 6 by frequency dividing the print timing signal 2, character by character.
印字アドレス情報は、第2図に示すように、例えば“1
″を印字する場合、印字ヘッドが左方向の時F120
番地、右方向の時1d10番地となる。The print address information is, for example, “1” as shown in FIG.
”, when the print head is in the left direction, press F120.
The address is 1d10 when facing to the right.
以上の説明より明らかなように、in番目の印字アドレ
ス情報の中央制御部から前段79ソフアへの転送は第(
n−1)番目の印字動作が終了する直前迄に行なえばよ
く、中央制御部が複数の人出力装 を同時に制御してい
る場合など、ピーク時負荷率を軽減させることになる。As is clear from the above explanation, the transfer of the inth print address information from the central control unit to the previous stage 79 software is
This can be done just before the end of the n-1)th printing operation, which reduces the peak load factor, such as when the central control unit is controlling multiple human output devices at the same time.
1だ、第2図に示す如く、印字アドレス指定は右方向、
左方向にかかわらず一定となり、この面でも回路を簡略
化させることができる。1, as shown in Figure 2, the print address is specified in the right direction,
It is constant regardless of the direction to the left, and the circuit can be simplified in this respect as well.
上記実施例の説明より明らかなように、本発明によれば
DMA方式、マイクロコンピュータ方式等のハードウェ
アを用いることなく、印字制御システムを構成すること
ができ、更に、中央御御装置の各種のデータ処理に要す
る時間的余裕を与えることができ、安価で処理能力の高
いシステム構築に寄与するところ大である。As is clear from the description of the above embodiments, according to the present invention, it is possible to configure a printing control system without using hardware such as a DMA system or a microcomputer system, and furthermore, it is possible to configure a printing control system without using hardware such as a DMA system or a microcomputer system. This can provide more time for data processing and greatly contributes to the construction of systems with high processing power at low cost.
第1図は本発明の一実施例におけるドツトマトリックス
印字方法を実施する装置のブロック図、第2図は同装置
のトンドパターンの記憶内容およびアドレッシング方法
の概略図、第3図イ〜チは同装置の動作説明図である。
1・・・・・・中央制御部、2・・・・・・前段バッフ
ァ、3・・・・・、後段バッファ、4・・・・・・キャ
ラクタゼネレータ、トローラ、7・・・・・・印字部。FIG. 1 is a block diagram of an apparatus for carrying out a dot matrix printing method according to an embodiment of the present invention, FIG. 2 is a schematic diagram of the memory contents of the dot pattern and the addressing method of the same apparatus, and FIGS. FIG. 3 is an explanatory diagram of the operation of the device. DESCRIPTION OF SYMBOLS 1... Central control unit, 2... Pre-stage buffer, 3... Post-stage buffer, 4... Character generator, troller, 7...... Printing section.
Claims (2)
いる記憶装置の文字格納アドレスを、印字へノドの右又
は左方向移動に応じて先頭アドレス又1尾アドレスを指
示して印字することを特徴とするドツトマトリックスプ
リンタ印字方法。(1) The character storage address of the storage device in which the dot matrix of printed characters is stored is characterized by specifying the first address or one tail address according to the right or left direction movement of the gutter to print. Dot matrix printer printing method.
l一時記憶し、1文字印字毎に上記第1のバッファより
情報が転送される第2のバッファを有し、上記第2バツ
フアは印字部からの印字タイミング信号をトリガにして
、印字へノドの右又は左方向移動に応じてアップカウン
ト又はダウンカラ(2) A first buffer l temporarily stores character storage addresses in the storage device, and a second buffer is provided to which information is transferred from the first buffer each time one character is printed, and the second buffer is used for printing. The print timing signal from the unit is used as a trigger to count up or down according to the right or left movement of the gutter to print.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6591282A JPS5941274A (en) | 1982-04-19 | 1982-04-19 | Printing method for dot-matrix printer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6591282A JPS5941274A (en) | 1982-04-19 | 1982-04-19 | Printing method for dot-matrix printer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5941274A true JPS5941274A (en) | 1984-03-07 |
Family
ID=13300650
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6591282A Pending JPS5941274A (en) | 1982-04-19 | 1982-04-19 | Printing method for dot-matrix printer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5941274A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4838031A (en) * | 1971-09-14 | 1973-06-05 | ||
JPS5066119A (en) * | 1973-10-11 | 1975-06-04 | ||
JPS5353926A (en) * | 1976-10-26 | 1978-05-16 | Tokyo Electric Co Ltd | Reciprocating print unit for dot printer |
-
1982
- 1982-04-19 JP JP6591282A patent/JPS5941274A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4838031A (en) * | 1971-09-14 | 1973-06-05 | ||
JPS5066119A (en) * | 1973-10-11 | 1975-06-04 | ||
JPS5353926A (en) * | 1976-10-26 | 1978-05-16 | Tokyo Electric Co Ltd | Reciprocating print unit for dot printer |
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