JPS594041U - Power-off state detection circuit - Google Patents

Power-off state detection circuit

Info

Publication number
JPS594041U
JPS594041U JP9774982U JP9774982U JPS594041U JP S594041 U JPS594041 U JP S594041U JP 9774982 U JP9774982 U JP 9774982U JP 9774982 U JP9774982 U JP 9774982U JP S594041 U JPS594041 U JP S594041U
Authority
JP
Japan
Prior art keywords
circuit
power
state detection
detection circuit
integrating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9774982U
Other languages
Japanese (ja)
Inventor
良 渡辺
数明 楠根
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP9774982U priority Critical patent/JPS594041U/en
Publication of JPS594041U publication Critical patent/JPS594041U/en
Pending legal-status Critical Current

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  • Stand-By Power Supply Arrangements (AREA)
  • Power Sources (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例の回路図、第2図はそのタイム
チャートである。 図中、1は全波整流回路、2はトリガ信号発生回路、3
は積分回路、4はタイマである。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a time chart thereof. In the figure, 1 is a full-wave rectifier circuit, 2 is a trigger signal generation circuit, and 3
is an integrating circuit, and 4 is a timer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 交流電源信号を整流する整流回路と、該整流回路に光学
的に接続され、該交流電源信号のレベル″   、に一
対一対応してトリガ信号を発生する回路と、トリガ信号
を一定の時定数で積分する回路と、該積分回路の積分出
力をスライスして、電源断状態を検知出力する回路とを
備えて成る電源断状態検出回路。
a rectifier circuit that rectifies an AC power signal; a circuit that is optically connected to the rectifier circuit and generates a trigger signal in one-to-one correspondence with the level of the AC power signal; and a circuit that generates a trigger signal with a constant time constant. A power-off state detection circuit comprising a circuit for integrating, and a circuit for slicing the integrated output of the integrating circuit and detecting and outputting a power-off state.
JP9774982U 1982-06-29 1982-06-29 Power-off state detection circuit Pending JPS594041U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9774982U JPS594041U (en) 1982-06-29 1982-06-29 Power-off state detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9774982U JPS594041U (en) 1982-06-29 1982-06-29 Power-off state detection circuit

Publications (1)

Publication Number Publication Date
JPS594041U true JPS594041U (en) 1984-01-11

Family

ID=30232377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9774982U Pending JPS594041U (en) 1982-06-29 1982-06-29 Power-off state detection circuit

Country Status (1)

Country Link
JP (1) JPS594041U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61183536U (en) * 1985-05-07 1986-11-15

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61183536U (en) * 1985-05-07 1986-11-15

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