JPS5939947B2 - Video signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video signal processing circuit applied to a brightness signal system of a color television receiver, and particularly to an ABL circuit that automatically limits excessive beam current.

The present invention is applicable to cases where a clamp circuit is provided which detects the pedestal level or sync tip level of a video signal, compares it with a reference level, and sets the pedestal level or sync tip level to a predetermined DC level based on the comparison output. The clamping operation and the ABL operation are performed at the same location to reduce the number of elements and the number of terminal pins, and the ABL operation is made to work satisfactorily.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. 1 is an input terminal to which a video signal (luminance signal) is supplied, 2 is an output terminal thereof, and the video signal obtained at the output terminal 2 is a luminance signal. The signal is supplied to a matrix circuit via a signal amplifier, etc., and matrixed with the three color difference signals from the color demodulation circuit to form three primary color signals, which are applied to the cathode of the color picture tube. .

The input video signal is supplied via a resistor 3, a delay line 4, a resistor 5, a resistor 6, and a capacitor 1 to the base of a transistor 21 constituting a clamp circuit. The emitter of this transistor 21 is led out as the output terminal 2, and the resistor 2
Grounded via 2. One end of a parallel circuit of a coil 8 and a capacitor 9 is connected to the output of the delay line 4, and the other end is connected to a resistor 10 inserted in series between the power supply terminal B+ and ground.
and 11 connection points. The parallel resonance frequency of the coil 8 and capacitor 9 is selected to be about 3 [MHz],
Peaking is performed around 3 [MHz] to improve image resolution. Further, one end of capacitors 12 and 13 are connected to both ends of the resistor 6, respectively, and the other end is grounded through the valley of the coil 14, thereby forming a trap circuit for the color subcarrier component. Furthermore, a resistor 15 is connected in parallel with the capacitor 7. Here, the parallel resistance of the resistor 10 and the resistor 11 is selected to be equal to the equivalent impedance of the delay line 4, and the resistors 5 and 6 have a small value of about several hundred ohms. Therefore, by providing the resistor 15, a slight bias is supplied to the base of the transistor 21 even when there is no clamp pulse, and the color picture tube is not cut off, resulting in a screen slightly brighter than black. Since the clamp pulse is formed from a horizontal sync signal that is separated from the received color television signal,
When an empty channel is selected, even if it is not an empty channel, the clamp pulse will not be generated when the fine tuning shifts, or during inspection after completion (aging). In these cases, if the transistor 21 is completely cut off, the output terminal 2 will be at ground potential, the color picture tube will be cut off, and the screen will sink into black, causing discomfort to the user and making it difficult to distinguish from a malfunction. There are problems such as. However, this problem can be solved by supplying a slight bias to the base of the transistor 21 as in this example. Now, the emitter of the transistor 21 is connected to the base of one transistor 23 constituting the differential amplifier, and the reference voltage source 25 is connected to the base of the other transistor 24.
4 emitter common connection point is resistor 26 and transistor 2r
is grounded between the collector and emitter of the transistor 27, and the base of the transistor 27 is led out as a clamp pulse supply terminal 28.

The clamp pulse is a pulse that becomes positive during the horizontal synchronizing signal period or the back porch period of the horizontal synchronizing signal. This clamp pulse turns on the transistor 27, and at this time the differential amplifier operates, and the horizontal The sync chip level or pedestal level of the synchronization signal is compared with a reference voltage. The collector of the transistor 24 is connected to the power supply terminal B+ via a resistor 29, and is also connected to the PN
P-type transistor 30 (all other transistors are NPN)
connected to the base of the The emitter of the transistor 30 is connected to the power supply terminal B+ via a resistor 31, and to the base of the transistor 21 via resistors 32 and 33 in series. A smoothing circuit including a capacitor 34 and a resistor 35 connected in parallel is provided between the connection point of the resistors 32 and 33 and ground. The connection point between the resistors 32 and 33 is connected to the collector of an ABL transistor 40, the base of which is grounded, and the ABL voltage is supplied to its emitter.

The ABL voltage is the secondary winding 42 of the flyback transformer 41.
It is formed by a detection resistor 43 inserted in series on the AC low potential side of. A negative voltage corresponding to the anode current of the color picture tube is generated across the detection resistor 43, and a predetermined positive bias is applied to this negative voltage by the resistor 44 and smoothed by the capacitor 45. So, A
A BL voltage is formed. Therefore, the ABL voltage decreases in proportion to the anode current (proportional to the beam current of the color picture tube), and becomes a negative voltage when the beam current exceeds a predetermined value, which causes the transistor 40 to be cut off. The ABL operation is now activated. To explain the operation of the embodiment of the present invention described above, first, the beam current is below a predetermined value, and therefore the ABL voltage is above the base potential of the transistor 40.
Transistor 40 will be cut off.

When a clamp pulse is supplied in this state, the video signal obtained at the output terminal 2 is compared with, for example, the sync chip level or a reference voltage. VO this sync chip level
If the reference voltage is r, then in the case (VO>r), the collector current of the transistor 24 decreases, the base voltage of the transistor 30 increases, the collector current of the transistor 30 decreases, and this collector current capacitor 3
Since the current discharged by the resistor 35 is larger than the current charged by the transistor 4, when the base voltage of the transistor 21 is (VOcr), the base voltage of the transistor 30 decreases, and the transistor 30 Since the collector current increases and the charging current to the capacitor 34 becomes larger than the discharging current, o is increased. In this way, (VO
=Vr). FIG. 2 is used for this explanation, and FIG. 2A shows the clamp pulse supplied to the clamp pulse supply terminal 28.

As mentioned above, in the case (VO>Vr), the current flowing from the collector of the transistor 30 to the resistor 32 is discharged from the capacitor 34 through the resistor 35 during the period between the clamp pulses, as shown in FIG. 2B. To replenish the small amount of charge, a relatively large current flows for a short time during the initial period of the clamp pulse, and a decreasing current flows as capacitor 34 charges. At this time, the maximum value of the current flowing through the transistor 30 is mainly due to the resistance 3.
2. In addition, in the case of (VO<Vr), the period in which this current flows is a large current, as shown in FIG. 2C, becomes long. When VO further decreases, as shown in FIG. 2D, the transistor 30 remains on while the clamp pulse is being supplied, and a constant current limited by the resistor 32 flows for a certain period of time.

This is the operating limit at which the clamping operation works normally, and even if VO falls further, it will not be compensated. That is, even if VO falls further, the current flowing through the transistor 30 and the period during which the transistor 30 is on do not change, so the feedback clamp operation of keeping the sync chip level of the clamp pulse constant is no longer performed.
As is clear from this operation, the resistor 32 is connected to the capacitor 3.
The maximum value of the current supplied to resistor 32 is determined.
The current is limited by Next, when the beam current exceeds a predetermined value and the ARL voltage becomes negative, a collector current flows through the transistor 40.

Therefore, the capacitor 34 is charged with a current obtained by subtracting the collector current of the transistor 40 from the current flowing through the resistor 32 (average value). Therefore, the second
As shown in Figure D, VO is forcibly changed to the limit state of the feedback clamp operation, and beyond this state, VO, that is, the DC level of the video signal, suddenly decreases.
As a result, the beam current is lowered, and an ABL operation is performed in which the average value of the beam current is less than or equal to a predetermined value. As is clear from the above description, according to the present invention, since the comparison output fed back from the clamp circuit is controlled by the ABL voltage, the number of elements and terminals is reduced, and the configuration is simplified. This is convenient for IC implementation.

In addition, in a feedback clamp circuit that uses the pedestal level or sync chip level of a video signal as a predetermined DC level, when the beam current is below a certain value, normal feedback clamping is performed, and when the beam current exceeds a certain value, Since the feedback gangway operation is forcibly not performed when the vehicle becomes loose, a sufficient ABL action can be achieved with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a connection diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram used for explaining the same. 1 is an input terminal, 2 is an output terminal, 28 is a clamp pulse supply terminal, and 40 is an ABL transistor.

Claims (1)

[Claims] 1 Detect the pedestal level or sync tip level of the video signal within the period of a clamp pulse having a certain width and compare it with the reference level, and charge the clamp capacitor with the comparison output output in synchronization with the clamp pulse. In a video signal processing circuit equipped with a feedback clamp circuit that sets the pedestal level or sync tip level to a predetermined DC level by discharging, a maximum current limiting resistor is connected in series in the charging path for the capacitor. At the same time, a means for detecting the beam current is provided, and when the beam current is below a certain value, a charging current whose charging period is varied according to the comparative output and whose maximum current is limited to a certain value is passed. The feedback clamp circuit performs a feedback clamp operation, and when the beam current is above a certain value, the comparison output causes a charging current whose charging period is constant and whose maximum current is limited to a constant value to flow through the beam current. A video signal processing circuit configured to limit the beam current by preventing the feedback clamp circuit from performing a feedback clamp operation and forcibly lowering the pedestal level or the sync tip level in response to an increase in the beam current. .