JPS5938991A - Management system of virtual storage - Google Patents

Abstract

PURPOSE:To minimize the change of a memory map to limit the work quantity for the change, by dividing a virtual storage area to an address conversion fixed area and a variable area and managing them and making it possible to register the fixed area in the variable area. CONSTITUTION:A virtual storage area 100 consists of address fixed areas such as an area 110 where software programs are stored and an extension area 120, an address conversion area, etc. This address conversion are a is divided to an address conversion fixed area FX for highspeed real-time processing and an address conversion variable area FL to which pages correspond at a program execution time, and the whole of the area 100 and areas FX and FL are managed through an area OS, and the area FL can be regitered in the area FX. By this constitution, the allocation to the area FL which is not used and the change of the map due to registering to the area FX are minimized at the memory map change time, and the quantity of the program reloading work is minimized. Further, the use effectivity of the virtual memory area or the like is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a main memory management method for a computer system, and particularly relates to a virtual memory management method suitable for executing a program requiring high-speed response and a program requiring large storage capacity at the same time. Regarding management methods.

Conventionally, in a storage device management method for a single system,
As one of the most advanced management methods, a virtual memory management method using on-demand page swapping (abbreviation: demand basing) is known.

In the virtual memory management method, the address of the storage device in the program that the computer executes is not a real address attached to the real main memory, but a virtual storage area that does not exist and consists only of a logical structure. It is characterized by being described using an attached virtual address. Therefore, a hardware mechanism and a software program for associating virtual addresses with real addresses are essential. The hardware and software required to make this association is called an address translation mechanism. The above-mentioned demand paging method is a typical method for realizing an address translation mechanism.

An overview of the demand basing method is given below.

In the demand paging method, a virtual storage area is divided into small areas called fixed-length pages, and a main storage device is divided in advance into small areas called page frames (hereinafter abbreviated as PF) having the same length as pages.

Both the page and the PF contain numbers +1 in order starting from 0.

A program consists of one or more 19 consecutive pages.
Second, other programs are placed on the same page as N11 itself. The processing that must be performed to execute a program in the demand paging method is as follows.

If it is found that a virtual address in a page that is not associated with a PF is to be translated during execution of a certain program (this is called a page fault), the page is associated with the PF. That is, in the address translation mechanism, if a page and a PF have not been associated with each other, PIi'' (this is called an empty PF), which has not yet been found to correspond anywhere, is associated with the page.There is no empty PF. In this case, according to a certain predetermined rule, the association between the PF and another page that has already been associated (this is called a page in use) is canceled, and the PF that becomes free through this operation is associated with the page.Program When the execution of the program ends, all the pages used by that program are disassociated from the PF, and those PFs become free.

The advantages of this demand paging method are: (1) Since only the page being executed needs to be associated with the PF, the size of the program is not limited by the capacity of the main storage device, and is dependent on the size of the virtual storage area. There is no limit in principle, (
2) Since the pages that are referenced and executed within a certain period of time are limited to a portion of the entire program area, it is rare for pages that are rarely referenced or executed to occupy the PF. , the main memory usage efficiency is high (
3) From the above points, when multiple programs are executed in parallel (this is called multiple programming), the total number of pages in use can be made much smaller than the total page capacity of the program group. As a result, the number of programs that can fit into the limited main memory is much larger than the number determined by the total page capacity, and the degree of multi-programming becomes large.

However, on the other hand, there are disadvantages: (1) Since page faults occur with a certain frequency during program execution, the original program execution time is longer by the time it takes to execute the page replacement algorithm (this is called O8 overhead). (2) If too many programs are executed unnecessarily, most of the computer time is spent on O8 overhead, resulting in the so-called thrashing phenomenon, and the computer system virtually stops functioning. (3) The price of the computer increases by the addition of the address translation mechanism. Of these, (
Regarding point 3), it has become less of a problem as 11.0 can be realized relatively inexpensively due to recent advances in hardware and device technology, but (1), (
Point 2) is an essential problem, and is especially fatal when real-time processing is performed in a plant control system or the like.

By solving these problems, we have made it possible to take advantage of the advantage of conventional demand paging methods, which is that large-capacity programs can be executed without being constrained by main memory capacity, while also making it possible to execute programs that require high-speed response processing. A virtual memory management system equipped with hardware and software for this purpose is proposed in Japanese Patent Application No. 56-200645. The feature of this invention is that the virtual storage area to be subjected to address translation is doubled, and one page and PF pair 1. F; Address conversion fixed area (Fixed Area: hereinafter referred to as Ti" The address conversion variable area (Floating Area: referred to as the PL area after J) is used, programs that require high-speed response are placed in the FX area, and large-capacity programs are placed in the FL area.

On the other hand, in conventional computer systems, when the size of programs and data changes due to system function expansion or changes in the specifications of existing functions, the arrangement of programs and data in main memory ( (This is called a memory map) had to be changed across all areas.

In real-time systems, in order to ensure high-speed processing, most programs are loaded into the computer system in the form of a load module having an absolute address on the host. Therefore, if you change the memory map, all programs will be moved to new main memory.
It is necessary to create another load module as a near address (, -% Mi) and reload it into the computer system, which requires a great deal of effort. This problem is caused by the main memory capacity being limited. As it gets bigger, the works up to T10-ding become more and more dog-like.
Especially in the virtual memory control method mentioned above, the influence will be great.

An object of the present invention is to minimize the amount of work such as reloading a program due to a change in a memory map, and to make it possible to effectively use the virtual storage area and main memory. An object of the present invention is to provide a virtual memory management system equipped with hardware and software that allows programs to be executed without being constrained by the capacity of a main storage device, and also to execute programs that require high-speed response.

In addition to the content described in the above-mentioned Japanese Patent Application No. 56-200645, the present invention is characterized by the management of the usage status of the virtual storage area, that is, which area is used and how, and the management of each PF of the main storage device. Expands system functionality by managing whether or not each page of virtual memory is in use, which PF in the main memory corresponds to each page, and managing the maximum capacity of programs allocated to the FL area. When the capacity of programs and data increases due to a change in specifications or specifications, the changed programs and data are placed in a different virtual storage area, and the PF used before the change and the previously unused ones are stored. By associating the corresponding page with the existing PF, it is possible to minimize changes to the memory map and limit the amount of work such as reloading programs and data associated with memory map changes to only the necessary parts. .

An embodiment of the present invention will be described below with reference to FIGS. 1 to 9.

FIG. 1(A) shows a virtual storage area (Virt) related to the present invention.
ual Storage: Hereafter abbreviated as V8) 100
, main %F2. '1st device (Main Storage)
:hereinafter abbreviated as M-S) 300, secondary storage device (Sec.
(ondary Storage: hereinafter abbreviated as SS)4
00 and the correspondence including the address translation mechanism 200. VSloo, address non-7
& area (hereinafter referred to as VR area) and address translation area (
(hereinafter referred to as the V〆R area), and virtual addresses are assigned in 1-byte units, with the left end as address 0 in the figure. The V=R area further includes O8 (Qperating) where basic software programs are placed.
System)' = 110 and F U (Future[Js
e) Consists of area 120. In addition, the V≠R≠ area is further divided into the F'X area, where the correspondence between vS and MS is fixed after system construction, and the correspondence between VS and MS is established at the start of program execution, and the correspondence between VS and MS is fixed at the start of program execution. After the completion, the FL area is configured to release the defense association. F
The X area is a place that performs a certain unified function and operates in parallel with each other.
'1. "ask)t 50, 1.60, and the global area (
GT, R) 130, and a subroutine (B, 80B) 140 commonly used by tasks. It is composed of FL area task 170.

MS is OS 110. GLB130. R,S[J
B140°R, TASK150. N几'T'ASK16
The blind area for each FX of 0 is in one-to-one correspondence with vS as shown in FIG. 1(A). Regarding the FL area, an area smaller than the FT area on the MS is arranged on the MS. MS is also 1 with the left end as 0
A real address is assigned to byte medium rise 1.

Dimension V ≠ control area, above mentioned page 180 and PF310
It is divided into units of. Pages 180 and PF 310 are also numbered in ascending order, with the leftmost page of vS9MS being 0.

Next, 88400 is a program that creates VSloo's F'U12 (a stone that stores all areas except 1) on the N13 from the beginning, since the contents of the MS300 are uncertain such as when the power is turned off. The start-up program I P
L (Tnitial Program J, oa
der) 410, a file 430 that is too busy to fit even in VSloo, and an area for holding the evacuation cutter 420 of NR, TASK 160.

5S400 is also addressed in ascending order of 512 bytes, with the left end being address 0. This address is called a logical sector address (hereinafter abbreviated as J and SA).

In this embodiment, two types of areas, R, TASK and NRTA8, are allocated to tasks. The difference between the two is R,'l
'ASK is an area where each task's program is given a page without interfering with each other, and the task is
300 (from this tone, the task on R,TASK is a resident task (R,es 1dent 'l'
In contrast, NR and TASK are areas that aim to make effective use of VS by assigning programs for multiple tasks that do not or need not run simultaneously to the same VS address. Therefore, depending on the priority level of the processing that is occurring for each task, the right to use the area is determined by F11 when the task is executed at start-up.Tasks with lower priority levels are The task is saved to the save area 420, and the task with the high priority level is loaded from above 58400 to 48300 (due to this yellowish color, the task on NR and TASK is called a non-resident task (Non-11, resident Ta5k)). It is prefecture.

Therefore, three types of tasks with different management methods can be placed in vSloo, and one in RTA8 in the FX area.
FL domain area NRTASK170 is R, TASK15 for severe high-speed processing tasks with 50 maximum real-time threads.
For tasks with a capacity exceeding 0 or NRTAST (size 160?
0 is used for tasks that are between the former two in terms of real-time performance and capacity.

Here, the memory map change on the MS and the associated vS
Figure 1 (13) shows a ladder of changes in the correspondence between MS and MS. (1) il-1 4f of VS explained so far
A quasi-memory map and the correspondence between vS and MS are shown below.

P X %C4 area and FL area each constituent area GLBI on VS100 131. R,5UBI 141.
rtTAsK1151, NR, TASKx161. N.R.
, TASKL171 has P U (FLlture (Jse) @4 area 1) in preparation for future customer expansion.
21 to 125 are provided as a memory map. MS 30
The correspondence with 0 is VS 10 excluding these F'U areas.
It is assumed that the valid areas on 0 are associated with areas previously allocated as FX area, FT, and area on MS from the beginning. In the memory map of (1), new C+T,
B 2132. If 152 is registered in R,5UB2 142°R,TA8, the memory map will be as shown in (2). That is, the FU area up to that point was 121°123.1
24 is associated from the beginning of the MS area 321, which was previously 2p (332, 342° 352). In this (2) memory map, R, TAS on the MS
If an attempt is made to expand the KI 151, the memory map rC will be as shown in (3). That is, on ■5100, F
The FU area 124 as the X area has a new TLTASK.
In order to accommodate and keep clean, a part of the FU area 125, which was set aside as the FL area, was repurposed as the FX reactor area, and it was set to R, TA8 with 1153, and RTAs at that size were set as the FX reactor area.
Kl 151 is assumed to be the FU area 126.

Also, the correspondence with]'V18300 is
, the MS area 353 that was associated with TASK 1, the area 354 that was previously vacant in the He48 area that was allocated as the FX Ryoyu, and the MS area that was allocated as the Ti'L area at that time. The empty area 355 will be associated with the DRTASKI 153 on the MS.

If the memory map is changed as above for j'-1, the object of the present invention can be achieved.

FIG. 2 shows the overall hardware configuration of a computer system to which this embodiment is applied. The computer system includes a main memory controller (MC) that controls the MS 3001.
(abbreviated as U) 500. A job processor (abbreviated as JOBP) 7 that has the function of decoding and executing machine instructions on the MS
00. The 5S400, the file control equipment (abbreviated as FCE) 890 that controls the SS, and the JOBP7
WI Note S S through the FCE based on instructions from
4 (10) A file processor 800 (abbreviated as FCP) that performs data transfer 2 with the MS 300, the λ[C
O200, JOBP700. A system bus (SFLrJS
) 610, and the 8BUS! /- Consists of a system bus control device (abbreviated as SBC) 600 for controlling. Furthermore, the JOBP 700 includes a memory address register (abbreviated as MAR) 710 for instructing the MCU 300 to access the target vS address, and a data register (abbreviated as DR) 7 for storing write data.
30. A series of flip-flops (abbreviated as FF) 720, logic, for controlling the MCU 300 and FCP 800;
Operator unit with arithmetic functions such as arithmetic and cyst calculation
(abbreviated as I-U) 740, a program counter (P
A general-purpose register group (abbreviated as GR) 790 used during # calculations, a control memory (abbreviated as WO2) 750 that decodes machine instructions and stores what kind of processing to perform, and Micro program counter (abbreviated as MPC) 7 indicating the next address to be executed on wcs
60. and a cache memory (CACHE) provided to shorten the time to access information in the MS300.
) 770.

The FCP800 also has a similar configuration to the JOBP700, and has an ALU840. WC8850, MPC860'r&
One. However, since it does not have the function of executing the machine instructions of the MS 300f, it does not have a PC 780 and instead has an 88
a data transfer buffer 870 for absorbing the difference in data transfer speed between MS 400 and MS 300, and the FC
It has a human output control circuit 880 for controlling data transfer to and from the E890.

Next, the MCU 300 has an input/output buffer register 550 with respect to the MS 300, a vS address register (abbreviated as VAR) 530, a real memory address register (abbreviated as MAR) 520 . Address conversion function W, unit (AT
(abbreviated as U) 580. Address translation buffer 7 (abbreviated as LB) 510 The page table index origin register (abbreviated as PTIOR) 5701 and the JOB
It is composed of control flip 70 knob group 540 corresponding to li"F'720 of P700°FCP800.

In the configuration shown in this figure, JOBP700TPC780
As a result of executing the instruction pointed to in accordance with WC8750, M S
The procedure for referring to 300 will be described below.

First, the JOBP should access VAR, 710.
Set the address and set the information to refer to FF'720. MCU300, this signal k F F
540 K Ukekel (!: V A R, 530K V
Load S7 address and start AT0580. The ATUHA VEQR560, PT, TOR570, TL
Refer to B510e, find the real address, and MAR520
, start the N4 S 300, and select the M A R
The data at the address specified by is retrieved, set in the turnout buffer register 550, and the fact that the data has been retrieved is displayed on the FF 540. When the display of JOBP700H1 is received in F'F720, the data of DR,7301/l is fetched from the turnout buffer register 550,
A series of MS reference processing is completed.

FIG. 3 shows a control table and a control program according to the present invention, which are arranged in the OS area 110 on the V8100.

The control table has a multi-level list structure, with PTIX (page table index) 20, P
FQ, (page frame waiting management table) 40, RQ
PB (Task Execution Waiting Pointer Block) 50. T.C.B.
There are (task control flll block) 60, ACT (x real control sub table) 701, PPCB (page frame analysis block) 90, and furthermore, under PTIX2o there are P
Below T (page table) 30 and PF'Q40, there is a list structure of PF'I'' (basic frame team) 8
It has a structure in which a list structure 'Jl' CB 60 is located below 0, T CB 60, R, and QPB 50.

Furthermore, 08CBIOHlV S 100 (7) FH?
7) VEQR indicating the final page address of V = R, which is located in the
ll, PTT('')R12゜PEQ, 40.R,Q
PB50, TCB60. ACT70. P to 'CB
TPPEQ indicating the start address of 90], 3. TPRQ
, PB14, 'J'P'l'CB15.TPACT16
．． Each field of TPPFCB97, FI, FXFT indicating the start VS address of the area, RV17, P L
Indicates the first real address of the area -1FXFLP, MIB
, A4A XIV/Is indicating the final real address of λ1S
19. MAXVS99.1 indicating the final address of VS
7'T, Development of a program that operates in the area - 1 (
number of pages) (i.e. F T, minimum required MS as area
It is composed of fields MIN and F'LPN98, which indicate the total capacity (number of PF').

The control programs include the area registration 1'ill removal program 1 having the function of managing each area on the VS 100, the R, TASK 150, NR, TASK 160, 170;
Task generation IQ'i' removal program 2, which has the ability to create or release a control table to be executed as a task, and a task start/end program 3 which has the function of starting or terminating the task created in 2; A task dispatcher (abbreviated as DISP) 4, which has the function of selecting an executable task with the highest priority level from among a plurality of tasks and transferring control to that task, is called by DISF' and has the function of transferring control to that task. If the task is PL area NR, TASK170, page 2180 and P
An MS acquisition release program 5 is provided which has a function of associating with F'310 and canceling the association.

FIG. 4 shows the TL1351.0° in the MCU 300, the control table in the O8 area 110, and the control table in the O8 area 110.
t2. PTIX20. PT30. ppQ4o, PQPB
50, TCB60. ACT70. PFT80. P.F.C.B.
90 configuration is shown. The value attached to the left end of each table indicates the relative byte position of the field. In this example, v
It is assumed that the S address is 32 bits (4 bytes) wide and the page size is 2048 bytes.

TLB510 has two sets of 1024-entry tables, where one entry corresponds to one page.
The entry number of the TLB is accessed using the page number (abbreviated as VPN) of the 11th to 20th bits of the address. The configuration of TLB 510 is as follows: page frame number P
FN511, access maintenance information for the page PRT5]
, 2. 1st to 10th bits of VS address (IMBfg
VA513 corresponding to the number when VS is turned off), T of the valid/invalid determination bit v514.2 of this TLB
LB rewriting control pin) Consists of R, 51, and 5.

PTIOR12 and PTIX20 have the same configuration, and PTIX
One entry is prepared for each VS area IMB.

These are the valid instruction flag V21, TPPT (I) indicating the start VS address and length of PTIX20 or PT30.
) and LENGTI-323.

PT30 has one entry prepared for each page, and is composed of a valid instruction flag V31, a page frame number PFN32, and access protection information PRT33.

PFQ40 is the total number of PFT cases PFCT41, free PFT first case VS address 43, free PPT last case VS address 44, occupied PF'T destination V100, final case VS address 45, 46, and the above MS is acquired when NRTASK is activated. Queue management area 47.48 (47,4
8 indicates the first and last case vS address of each waiting TCB.

Below, all list-structured tables are like this table,
(Managed by the VS address of the first and last case).

RQ, PB50 is queue header 51. of TCB60.
52), with one entry prepared for each task priority level. The task activation program 3 executes the RQ
The TCB 6055 of the task is connected to the end of the execution queue whose management table is the RQPB corresponding to the priority level determined by the task to be started in the PB. The task termination program 3 removes the TCB from the execution queue when the execution of the task ends.

TCB60 is prepared for each task, and the I(QPB50
Pointer R for connecting to QFP61. R,QB
P62, PFQ's PFWFP47. Pointers 63, 64 indicate the source wait state to be connected when the resource wait state such as PFWBP48 occurs, task number 65, wait state flag E66-1, other control flag 66, priority level 67-
1, access protection information 67, and other) control information 68.

ACT70 has each module in each area on V8100 (
Pointer ACTF prepared for each II' (SUB, GLB, task, etc.) and pointing to the vS address of the next table.
P71, ACTBP72. Module identification information IDES
TIF-IER73, VS start address where the module is placed, 7. VA74. First SS address LSA75.
It is composed of module size (number of bytes) SIZE 76 and other control information 77.

PξT80 is prepared as many as the number of PFs in the FL area of the MS 300, and a pointer FPNT81. BPNT82. Page number VPN83
, page frame number PFN84.

The PFCB90 manages the usage status of the PF of the MS300, and is used to store P for the FX area, F number EPPN, which is not yet fixedly associated with any page of VSloo.
X91, the number of PFs for the same FL claim EPFNL92, BI that manages the usage status of each PF (whether it has already been fixedly corresponded to VSlooo or not) in the order of PF number corresponding to bits
It is composed of TMAP93.

Next, using FIGS. 2, 3, and 4, the MCU
The address conversion method in 500 will be explained.

In the M CtJ, v given to VAR530 is not changed.
Compare the S address and VEQR, 560, and if the former is smaller or equal, or the V of PTIOR, 570
If the pit 21 indicates invalidity, address conversion is not performed and the 9th to
31 pit is set as is. Therefore VS100
Upper V = R, area ij VEQR560 (D Because it is smaller than the indicated address, address conversion is not performed and it is directly associated with 4MS 300. As a result of the above determination, V
S address is larger than VEQR1560 and PTI
If V pits 2 and 1 of OR570 indicate that they are valid, T is determined from bits 11 to 20 of VAR530.
Find the corresponding eight of LB510, VAR, 530 1st
It is checked whether any VA 513 of the two sets of TLB 510 with 10 bits matches. When there is a match (referred to as TLB bit time), the corresponding TL
The address conversion is completed by setting the PFN 511 of B to the 9th to 20th bits of MAR 520, and setting the 21st to 31st pits of VAR to the 21st to 31st pits of MAR.

If there is no match with any TLB in the above determination (referred to as TLB miss pit), the following processing is performed. First of all, TPPTI22 of PTIOR570, D PTIX
Find the start address of 20. Next LENGTH23
The first to seventh pits of and VAR are compared, and if the latter is smaller, it means that the corresponding PTIX does not exist, so the above-mentioned page fault is thrown. Said LENGTH23
is equal to or greater than the contents of the 1st to 7th bits of VAR,530, then PTIX
The corresponding case address of 20 is found and the V pit 21 is determined. If the V pit indicates invalidity, a page fault is determined. If valid, pP by TP PT 22
Find the start address of T30. Next, the 12th to 16th pits of the VAR 530 are compared with the LENGTH 23 of the PTIX 20, and the length of the PT 30 is checked in the same way as at the beginning.

Next, the corresponding case address of the P'T is determined from the 12th to 20th bits of VAII, 530(7), and the V bit 31 is determined. If the bit is invalid, it is a page fault, and if it is valid, the PFN32 is set to the 9th to 20th bits of the MAR520.
The lower 21 to 31 bits are set to VAR, 5.
Address conversion is completed by setting the 21st to 31st pits of 30 as they are.

As is clear from the above explanation, by setting the corresponding page frame number in advance in the PFN 32 of the corresponding PT 30 at the time of system generation, address translation can be fixed, and therefore the
Area X can be realized.

Next, FIGS. 5 to 9 show the processing flows of the above-mentioned ill control programs 1 to 5.

5(A) and 5(B) show the processing flow of the area registration program 1. FIG. This program uses the area type, identification number, first VS address, first SS address, ease and control information as manual information, and by setting these information in ACT70, registers areas in the FX area and FL area, Perform expansion.

First, the above human power information is fetched '1502), and it is determined whether the designated area exceeds the maximum VS address MAXVS99 (1504). As a result, the area is M
If it exceeds AXV890, output that the MS capacity is insufficient is output as return information (1548).
Finish the processing of this program. The area is MAXVS9
If it does not exceed 0, then the same - VS as the area
It is determined by searching tAcT (70) whether an area including the entire start address and capacity has already been registered (1506), and double registration of the same area is prevented. If an area that overlaps even partially with the area has already been registered, the area is outputted as return information indicating that it has been registered (1550), and the processing of this program ends.

If the area is an unregistered area, then the area is FX
It is determined whether the area is to be registered as an area or not based on the area type of the input information (1508). If the area is to be registered as an FX area, it is further determined whether the size of the area falls within the number of free PFs for Ii'X area EPFNX91 of PFCf390 (
1510). If the area falls within the size indicated by EPFNX91, the necessary PF occupancy processing and the association of the VS page with the MS PF are performed according to the procedure shown below. First, BITMA of PFCB90
P93 is searched from the beginning to find an empty PF number, and at the same time, the bit corresponding to the PF number is set to indicate that it is in use (151.2). Next, the VS you are trying to register
Find the address of PT30 corresponding to the address d) (1
, 514), sets the V bit 31 of the PT, and sets the P I”
N: S 2 first.

Set the PF number found in , and use PILT33i to
fil ・F^” Set a part of the information (1516). Process these steps 1512 to 1516 for the number of pages corresponding to the capacity of the area to be registered.
v(1518°1520)i”t, E[ of PIi”CB
I'll keep it for the number of pages I've climbed on JFNX91 (1522). Next, indicate the address of the unused ACT 70 (1560), and specify the IDENTIFI of the ACT.
ER73 has been given an area type and one hawk license,
Set the first vS address in VA74, set the first U118 S address in LSA75, set the capacity in 5IZB76, and set the limit? Set control information in I information 77 (156
2). Then, it is possible to process 1564 L pieces and 10 grams by outputting the fact that the process has ended normally as return information. In the above processing number 1i', the area in the X area can be registered.

On the other hand, in process 1510, if the area size of the FX area to be registered does not fit within the size indicated by El)FNX91 of PFCB (C is further
+EPFNL92-N11Nd'I, determine whether #'+ is within the size indicated by PN98 (1524
). This is to determine whether or not the area can be registered as having one eye in FL area 1. If the size does not fit within the above size, the program outputs return information indicating that 1 BB is insufficient (1558) and ends the processing of this program. For a page that fits within the above size, first go to the area corresponding to the number of pages indicated by the BPFN
The same process as above is performed to set the PFCB BITMAP 93 and gppNXc+t, j, - and l)T30 (1526). Next, the remaining pages in the area are registered by the following process (1530-1546). Obtain the address of the closed PFT 80 indicated by EFPN'T'43 of PF'Q40 (1530), remove the PFT from the free PFT list, and select OF'PNT4.
Connect to the PF'T list for 1st official managed in 5 (15
32).

Set the page number corresponding to the VS address to be registered in the VPN83 of the PFT, and obtain the page frame number PFN84 corresponding to the PFT (15
36). Search BITMAP93 of PFCB90,
The display is set to indicate that the Villa Tiger is in use, which corresponds to the above-mentioned PFN84 (1538). Regarding the VS address to be registered, the PT
Various information is set to 30 (1540). The vS address is advanced by one page (1542). These processes (1
After repeating steps 530 to 1542 for the remaining number of pages (1544), EPF'NL92 of P P CB
is decreased by the number of pages (1546). and,
Registering the area information in the ACT 70 and outputting the return information Performs the processes 1560 to 1564 described above,
Finish the processing of this program. As described above, area registration in the FX area can be performed by using not only the MS area allocated as the FX area but also the MS area allocated as the FL area to the extent possible.

-Also, if the area to be registered is in the FL territory, the area is EPFNL9 of PFCB90.
1552),
If it does not fit within the above size, output a message indicating that the MS capacity is insufficient as return information (1558),
The processing of this program ends.

If it fits within the above size, the area is MINF
If the size exceeds the size shown in I, PH10, set the size (number of pages) to MINFI, PH10 (1554, 1556), and then register the area information to ACT70 and output the return information. Processing 156
0 to 1564, and the processing of this program ends. By the above processing, areas in the i,+L area can be registered.

FIG. 5 (■) shows the processing flow of the area deletion program 2. This program uses the area type and identification number as human information, and disables ACT70 that has content that matches that information.
Delete the area in the FL territory.

First, import the human information (1572), search for ACT70, and check the IDh for the type and identification number of the finger area.
:NTIF'TE) 1.73 is determined (1574). At this time, if the corresponding ACT is not found (1576), a return message indicating that the area is unregistered is output (1602), and the processing of this program ends. If there is a corresponding ACT, i-ACT
After setting a code indicating that the ACT is empty in IDENTIF'IER73 (1578), it is determined whether the area is in the F"X 4 area (1580)
.

If the area is in the FX area, the V of the area
Determine the S address and capacity from the ACT (1582L and below process to release the occupation of the corresponding page on the VS and the corresponding PF on the MS. First, find the address of 1) T 30 corresponding to the VS address to be deleted. Search (1
584), V bit 311 of the FT? C reset, P
Find the corresponding PF number from F'N32 (1586)
. Next, on the BITMAP 93 of the PPCB 90, the bit corresponding to the fcPF number obtained above is set to indicate an empty space (1588).

Determine whether the relevant PF is for the FX area, and (1
590), if it is for the FX domain, PF'C
Add 1 to EPFNX91 of B. If it is not for the FX area, search the in-use PFT list indicated by 0FPNT45 of PFQ40 to find the PFT80 corresponding to the corresponding VS address (1610),
PFT P Ii'Q ■jili")) NT43
Register in the vacant PFT list shown in
, 92 is added by 1 (1612). Next, proceed by VS address & 1 page (1594), and perform the above process (158) for each area company (number of pages) to be deleted.
Steps 4 to 1594) are repeated, and finally, a message indicating successful completion is output as return information (step 1600), and the processing of this program ends. Through the above processing, the FX area can be deleted.

On the other hand, if the area to be deleted is an FL area, its capacity is determined from the ACT corresponding to the area (1604), and it is determined whether it is equal to MINFLPN98 (1606). At this time, the capacity of the area is M
If it is equal to INFLPN98, search for a valid ACT and find the maximum ACT size in the FL domain area. Find the area size of 1ν1INI”I,PN
Should I set it to 98 (1608), indicating normal completion? This is output as return information (1609), and the processing of this program ends. The capacity of the area is MINPT, PN98.
If it is not equal to , MINFLPN98 is left as it is and output as IJ turn information indicating normal completion (1
609), the processing of this program ends. Through the above processing, the FL territory area can be deleted.

FIG. 6(5) shows the flow of the task generation program 2. This program manually displays task numbers, destination levels, protection information, and program updates (910),
Process of setting various information on TC860 based on them (
911 to 915). Special processing 913 and 914 calculates the ACT'7 (l) corresponding to the task number from the input program information (program address, capacity) and sets a part of the ACT information in kTcB. When dispatching area task 7t, it is used to associate pages in the FL'vfi area with PFs.

FIG. 6(B) H shows the flow of the task deletion program 2. This program manually sets the task number (916) and vacates the TCB60 (917, 9).
18).

FIG. 7(A) shows the flow of the task activation program 3. This program manually inputs the task number (920) and calculates the priority level of the corresponding task (921).
, 922), a process of connecting the TCB 60 to the execution queue of the priority level managed by the RQPB 50 (923,
924).

FIG. 7(B) shows the flow of the task termination program 3. This program uses TCB60 of its own task.
The priority level is determined (925), the TCB is removed from the execution queue (926, 927), and control is transferred to dispatcher 4 in order to transfer control to another task (928).
)I do. At this time, if the task is in the PL area, the MS release program 5 is called to release the PF occupied by the task (984, 986
).

FIG. 8 shows the flow of the dispatcher 4. This program is based on RQPB50, which has the highest priority level.
The TCB 60 is sequentially searched from the execution queue of , and those whose E flags are OFF are found (930 to 934), and a process of transferring control to the task (941) is performed. At this time, whether the task is a FL domain task or not is determined from IDENTIFIEFL73 of ACT70 corresponding to the TCB60.
After calling the S acquisition program 5 (938, 939) and associating the vane on the VS and the PF on the MS necessary for the task to operate, control is transferred to the task.

Figure 9 CA)? -1, shows the flow of the MS acquisition program 5. This program uses task numbers and VS
Manually enter the start address of the area and the number of pages (950),
Determine whether there is enough free PFT 80 (951)
, If there is enough, find a free PFT 80 and mark it as in use (952-954), then set the VPN 83 (955)
, processing to create a corresponding PT30 (956, 957)
is performed for all pages (958, 959), and the process ends normally. In the above PFQ determination, vacant PJ'i'
If the number of T80s is insufficient, the program enters a nuclear task waiting state (961 to 963), reports the shortage of PFs as return information (964), and ends the processing of this program.

FIG. 9(B) shows the flow of the MS release program 5. This program requires inputting the start address and page number of the Vs area (970), and the corresponding PFT80.
Processing to empty (973°974) and corresponding P
The process of making T30 free (980, 982) is performed for all pages, and it is further determined whether there is any TCB60 waiting for a free PF (977), and if there is, the process of releasing those tasks from waiting (978). )I do.

According to this embodiment, the following effects can be obtained by using the programs 1 to 5 described above. In other words, by executing the area registration program and area deletion program 1, it becomes possible to easily register new areas, delete them, and change the layout of various areas on the VS (7); and the program and data changes caused by changes in the memory map can be easily performed. Work such as reloading (-2) can be kept to the necessary minimum.

In addition, Taste Batch 4 and MS acquisition program and MS
By fully executing the release program, it becomes possible to support the PL area by associating MS and VS during task execution.

According to the present invention, the virtual storage area is divided and managed into the address conversion identification area (FX area) and the address conversion variable area (1'i'' L area), and the area can be registered as an FX area as appropriate in the FL area. Therefore, it is possible to minimize the amount of work required for program loading when changing the memory map, and to make effective use of the virtual storage area and main storage.

[Brief explanation of the drawing]

FIG. 1(5) is a diagram showing an address translation method in the virtual memory management method according to the fourth aspect of the present invention. FIG. 1(B) is a diagram showing a memory map for showing the purpose and effects of the present invention. Figure 2 shows a system to which the present invention is applied.
4. 1 is a diagram showing an example of a machine system configuration. FIG. 3 is a diagram showing an example of a control table and program used in the present invention. FIG. 4 is an example of the field configuration of a control table used in the present invention. FIG. 5 shows an example of an area registration program and an area deletion program used in the present invention. FIG. 6 shows an embodiment of a task registration program and a task deletion program used in the present invention. FIG. 7 shows an embodiment of a task starting program and a task ending program used in the present invention. FIG. 8 shows an embodiment of a dispatcher used in the present invention. FIG. 9 shows the MS acquisition program used in the present invention, the MS release log 41 (
A) 1st leap (B) 2nd figure 3rd figure closed 4- Warm (B) l//) 5th opening (A) v 5 figure (B) 6th figure (A)

Claims (1)

[Claims] In a main memory management method of a computer system, an address translation mechanism that converts a virtual address in a virtual space to a physical address in real memory, a conversion means that associates a part of the virtual address with the real memory in a semi-fixed manner, and the virtual address A means for associating a part of the real memory necessary and sufficient for program execution at the start of program execution, a means for managing the usage status of the entire virtual space and the above two types of areas, a means for managing the entire real memory and A virtual memory management system characterized by providing means for managing the usage status of portions prepared in advance in the above two types of areas.