JPS5937890U - DC power circuit - Google Patents
DC power circuitInfo
- Publication number
- JPS5937890U JPS5937890U JP13338582U JP13338582U JPS5937890U JP S5937890 U JPS5937890 U JP S5937890U JP 13338582 U JP13338582 U JP 13338582U JP 13338582 U JP13338582 U JP 13338582U JP S5937890 U JPS5937890 U JP S5937890U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- thyristor
- tap
- peak
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Control Of Electrical Variables (AREA)
- Rectifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の直流電源回路を示す回路図、第２図は本
考案の一実施例を示す回路図である。
１・・・商用電源、２・・・電源トランス、３．４・・
・タップ、ＡＩ、Ａ２・・・増幅器−〇１〜Ｃ５・・・
コンデンサ、Ｄ１〜Ｄ４・・・ダイオード、Ｑ１〜Ｑ５
・・・トランジスタ、Ｒ１−Ｒ８・・・抵抗（ＳＣＲ・
・・サイリスタ。FIG. 1 is a circuit diagram showing a conventional DC power supply circuit, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1...Commercial power supply, 2...Power transformer, 3.4...
・Tap, AI, A2...Amplifier-〇1~C5...
Capacitor, D1-D4...Diode, Q1-Q5
...Transistor, R1-R8...Resistor (SCR/
...thyristor.
Claims (1)
巻線端に２個以上のタップを設け、低電圧端となるタッ
プは整流ダイオードを介して出力端の平滑コンデンサに
接続し、他の高電圧端のタップはサイリスタを介して前
記平滑コンデンサに接続し、該サイリスタのゲート回路
は、出力端の−微分電圧を増幅してピークホールドし、
該ピークホールドされた電圧と予め任意に設定された基
準電圧との差に応じてゲート電圧を制御するように構成
されていることを特徴とする直流電源回路。Two or more taps are provided at the secondary winding end of a power transformer whose primary winding end is connected to the commercial power supply, and the tap that becomes the low voltage end is connected to the smoothing capacitor at the output end via a rectifier diode, The tap at the high voltage end of is connected to the smoothing capacitor via a thyristor, and the gate circuit of the thyristor amplifies and peak-holds the -differential voltage at the output end,
A DC power supply circuit characterized in that it is configured to control a gate voltage according to the difference between the peak-held voltage and a reference voltage arbitrarily set in advance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13338582U JPS5937890U (en) | 1982-09-01 | 1982-09-01 | DC power circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13338582U JPS5937890U (en) | 1982-09-01 | 1982-09-01 | DC power circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5937890U true JPS5937890U (en) | 1984-03-09 |
| JPH0119595Y2 JPH0119595Y2 (en) | 1989-06-06 |
Family
ID=30300899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13338582U Granted JPS5937890U (en) | 1982-09-01 | 1982-09-01 | DC power circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5937890U (en) |
-
1982
- 1982-09-01 JP JP13338582U patent/JPS5937890U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0119595Y2 (en) | 1989-06-06 |
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