JPS593773A - Lru control system of buffer storage device - Google Patents

Abstract

PURPOSE:To reduce LRU bits by dividing associative levels into plural groups, performing LRU logical operation in each group and reduces the number of LRU bits, and providing tripled flag bits separately and making a majority decision. CONSTITUTION:For example, eight associative levels are divided into a group 6-1 of levels 0-3 and a group 6-2 of levels 4-7. The LRU logical operation is performed in each group. Further, an H/C (hop and cold) bit 8 for indicating which group is to be replaced is provided and tripled to provide three HCO- HC2, making a majority decision. Consequently, while the associative levels are increased, the LRU bits are minimized and the buffer performance is prevented from deteriorating even in case of error occurrence.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for determining a replacement block in a buffer storage device that copies and stores part of data in a main storage device block by block.

[Prior art to the invention]

Generally, 1.RU (Le
Ast Recently Used) logical method is used, but as the number of LRU target blocks increases, LRU
The capacity of memory bits increases exponentially.

FIG. 1 is a block diagram of an embodiment of a general set-associative buffer storage device. FIG. 2 is a diagram illustrating a set-associative buffer storage device.

In FIG. 1, reference numeral 11 indicates request address registers 2-0 to 2-m71, tag sections 53-0 to 3-1, 1 indicates a match circuit, and 4 indicates update logic, respectively.

In FIG. 1, the data storage section of the buffer storage device is omitted.

Request address register 1 contains one request address: ], respectively, at social level 0, 1 . ... corresponds to each of m-1. Second
As shown, the buffer 1 device BS has associative levels ol to m-1, and each associative memory unit is divided into a set. 1
In this specification, the divided unit is referred to as a block. In the main memory WNIS, each block B constitutes 11 memory units. When the program y<,
The necessary data in block B of main memory MS is transferred to any one of m blocks B belonging to the same set.

When accessing buffer storage, tag section 2-0.2-
1. . . 2-m-1 are searched by the set address, and the upper address is read. Each tag part 2-0.2-1. . . . 2-Ni: The upper address read from the match circuit 3-0.3-1. ...3-1
It is compared with the upper address of request address register 1 by .

Buffer storage [BS can be deleted every ~associative level. Which associative level is being deleted is indicated at the time. If any of the match circuits 3-0 to 3-m-1 outputs a tag match signal, the update logic circuit 4 generates a new LRU pattern indicating the 1-oldest order. The LRU pattern created by the update logic circuit 4 is stored in the LRU memory 6. LRU memory 6
stores, for each set, information indicating the order of age of data in blocks belonging to that set.

If the corresponding address does not exist in tag sections 2-0 to 2-m-1, 1 corresponding block is stored in the main memory device MS.
It is necessary to load the data into the new nine, but the replacement logic circuit 7 determines which associative level the data should be loaded into. In this case, the set address in the request address □ register 1 is set in the LRU address register 5, and the LRU memory 6 is read. The LRU information read from the LRU memory 6 is input to the 1-replace logic circuit 7, and the replace logic circuit 7 combines this LRU information with the discrete
based on the associative Φ level information and f”’)
- Determine one block to be replaced from among the blocks that have not been replaced.

In such a buffer 1 storage device BS, when the number of associative levels is m, the LRU bits for one set of 1 LRU memory 6 are m(m-1)/2 bits. For example, 6 bits are sufficient for 4 levels, but 28 bits are required for 8V base, which does not mean that the capacity of LRU memory 6 increases, but also that the replace logic circuit 7 and update logic circuit 4 are very large. This increases complexity and even affects operating speed. On the other hand, there is an increasing demand for increasing the number of levels in order to increase the hit rate of the buffer 1 storage device.

[Early invention]

The present invention increases the number of associative levels to 1 and L
It is an object of the present invention to minimize the increase in the number of RU bits and to allow processing to be continued without deteriorating the buffer capacity even if an error occurs.

[Purpose of the invention]

The present invention increases the number of uncia tape levels by 1, and
It is an object of the present invention to minimize the increase in the number of RU bits, and further to enable processing to be continued without reducing buffer capacity even if an error occurs.

[Structure of the invention]

The present invention divides one associative level into a plurality of groups and uses LRU logic within each group.
The number of RU bits is reduced, and instead a flag bit is provided separately to indicate which group is to be replaced. Furthermore, since the buffering capacity decreases at the moment of an error in this flag bit, the flag bits are tripled and decisions are made by majority vote to prevent performance degradation.

[Embodiments of the invention]

FIG. 3 is a block diagram of a main part of an embodiment of the present invention, showing nine examples in which eight associative levels are divided into two groups. 6-1.6-2 shows one set of LRU bits in the LRU memory 6, which are divided into a group 6-1 of levels 70 to 3 and a group 6-2 of levels 4 to $2. 7-1.7-2 is a circuit related to levels 0 to 3 of the replacement logic circuit 7 and a circuit related to levels 4 to 3.
This is a circuit related to 7.

In LRU memory 6-1.6-2, (01) to (6
7) are each 1 bit of information, for example, p) (i, j)
indicates whether level 5 or level j is newly used.

Further, 8 is a flag bit called H/e (hot meeting and cold), which instructs which of the two groups is to be replaced. This H/C bit is controlled so that when there is a block load on the associative level of either group, its value is updated so that the other group is targeted for replacement. Note that when the number of groups is three or more, the groups to be replaced may be designated cyclically.

A replacement determining means can be configured.

If an error occurs in H/C bit 8 and it degenerates to a fixed value, replacement will always be performed only in a specific group, and as a result, the performance will be the same as when there are only 4 associative levels. You won't get it. Therefore, in the present invention, H/C bits are triplexed and H/C bits are triplexed.
Three bits from CO to HC2 are provided. At the time of reading, the majority vote of these three pits is taken by each zero circuit 9) and applied to each replay U logic circuit 7-1, 7-2. In addition, delete signals 0 to 3 from 0P8R are given to the replace logic circuit 7-1, and delete signals 4 to 7 are given to the replacement logic circuit 7-2.
The oldest level is determined from among the associatives that have not been deleted in the group specified by the C bit and is output as a replacement associative level.

It goes without saying that LRU bits 6-1, 6-2 and H/C bit 8 exist for each of all sets. It goes without saying that these can be constructed by making one word of the LRU memory 6 accessed by a set address 15 pits. , according to the present invention, can be expressed using 6+6+3=15 bits, which not only saves 60 LRU memories, but also allows the use of multiple circuits with the same configuration for the replane logic circuits 7-1 and 7-2, reducing circuit complexity. It improves the stability and reduces the cost by 1.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the control section of a general set-associative type buffer 1 storage device. Yes, 6-1゜6-2 is each group glue,
RU bit S8 is H/C (hot and cold)
Flag pit) 7-1.7-2, the replacement logic circuit S9 of each group is a majority circuit. 507

Claims (1)

[Claims] In a buffer 1 storage device that copies and stores a part of data in the main storage device block by block, and determines the block to be replaced when storing a new block using the LRU method, Divide the blocks into a plurality of groups, provide means for determining a replacement block for each group using the LRU method, and provide a flag bit to indicate which group is to be replaced,
An LRU control method for a buffer storage device, characterized in that three left flag bits are provided so that a majority vote is taken at the time of one read.