JPS593753B2 - How to drive a dot display using 7-segment decoder output - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for converting the output of a 7-segment decoder into a dot display signal to display a dot display.

There are 7-segment numeric displays and 7-segment dot displays.

There are two types of driving methods: a 7-segment decoder and a matrix decoder. Looking at the display formats of the two, matrix dot display is easier to read because the font is not distorted. This difference becomes especially noticeable in the case of a large clock display. However,
Since the signal processing means of the driving decoders for both displays are completely different, the displays are not compatible. Therefore, an object of the present invention is to enable the driving of a dot display by signal processing the decoder output of a 7-segment 10-diameter display.

In order to achieve this object, the present invention has a 7-segment display section formed by a plurality of dot-shaped display sides, and a display section formed by two dot-shaped display sides disposed inside the 7-segment display section. The dot display is divided into an lb display side and a dot display section, and the output of a 7-segment decoder is signal-processed and selectively supplied to each section, thereby making it possible to display numbers on the dot display. . An embodiment of the method according to the present invention will be described below.

Figure 1 shows an example of the arrangement of each dot on the dot display.Each dot indicated by an alphabet is obtained by arranging a plurality of light emitting diodes, for example. display side a including ', display side b including dot display area b', display side c including dot display area c', display side d including dot display area d', and dot display area e'. A display side e including the dot display part f', a display side f including the dot display part f', and a display side g including the dot display part g'
A 7-segment display section is formed by the above, and a 7-segment display section is arranged therein, and a display side consisting of a display side i and a display side is arranged inside the 7-segment display section.

Then, each display side a, b, c, d, e, f, g, and i and dot display area a', bi, c', d'3e', '5
f' and g' are expressed numerically according to the logic shown in the following truth table. Next, an example of a circuit that sends out a logical output according to the truth table will be described with reference to FIG.

1 is a 7-segment decoder, which has output terminals A, B,
A known decoder with C, D, E, F and G.

Each output appearing at this output terminal is subjected to signal processing, which will be described later, and sent to the dot display 2, where it acts to produce a necessary display. Although the dot display 2 is omitted, each display side and each dot display part shown in FIG. 1 are formed, and a predetermined number is displayed according to an output signal. .

Reference numeral 3 denotes a signal converting device, which performs signal processing to convert the display signal of the 7-segment display appearing as the output of the 7-segment decoder 1 into a numeric display signal necessary for the form displayed by the aforementioned dot display 2. This is what we do.

That is, an inverter circuit 3a divides the logic level of the output terminal of the 7-segment decoder 1 into a level H and a level L, respectively, and a signal supplied from the inverter circuit 3a is processed by a gate circuit 3b and a gate circuit 3c. , is supplied to the display side and dot display section divided into 16 groups constituting the display 2, thereby obtaining a numeric display effect.

That is, at each output terminal of the 7-segment decoder 1, the following logical outputs of truth values are obtained. If, for example, 1 is to be displayed corresponding to the outputs appearing at the output terminals A, B, C, D, E, F, and G of the 7-segment decoder 1, the output terminals B and C of the 7-segment decoder 1 are The logic level becomes H, and this action energizes the display sides H, i and the dot display section g' of the dot display shown in FIG. 1, thereby producing a display. Note that since the dot display section a' displays any number from 1 to 0, it remains in the display state during its operation. When the level of the output terminals A, B, D, E and G of the 7-segment decoder 1 becomes H, the signals are passed through the display sides A, b, g, e and d and the dot display sections a', g' and d'. Lightning is plotted and 2 is displayed.

The same applies to the following numbers 3 to 9 and 0.
Reference numeral 3d denotes a drive transistor circuit, which becomes conductive when a processed signal is supplied to its base terminal, and has the function of lighting up the display side or dot display section connected to each.

Figure 3 shows the output of the 7-segment decoder described above! As a result of processing the force by the signal converter 3, the dot display 2
This shows the display pattern from 0 to 9, which is much easier to read than the display using a 7-segment numeric display. Next, the signal flow until the output of the 7-segment decoder 1 appears on the dot display 2 will be explained using an example.

First, the output for displaying 1 on the output terminal of 7-segment decoder 1, that is, the logic level of output terminals B and C is H.
In gate circuit 3b, gate b-1
Only the output of the gate is at level H, and the output of the other gates b-0, b-
2, b-3, b-4, b-5 and b-6 levels are L
It is. Therefore, due to the level H of the gate b-1, a signal is transmitted to the gates c-1, c-2, 2-c-8 of the gate circuit 3c and the inverter c-9, but the signal is transmitted to the transistor d-2 of the drive transistor 3d. , d-3 are off, and transistors d-14 and d-15 are turned on to energize display side h and display side 1. Further, since the dot display section a/ is always in the energized state, it is energized as it is, and the dot display sections g/ and d' are also energized, so that the display pattern 1 shown in FIG. 3 is displayed on the dot display 2.
It will appear in

The dot display sections g' and d' undergo the following processing operations in the signal processing process described above. That is, the output of the gate b-5 of the gate circuit 3b is at level L, so the transistor d-10 is turned on, and the output of the gate circuit 3c0)0R gate c-7 is also at the level L, so the transistor d-13 is turned on. This is because the dot display section is also turned on, thereby energizing these dot display sections.

Thereafter, similar signal processing is performed for the display of each number, and a display according to the display pattern shown in FIG. 3 can be obtained. Note that the reference numerals given to the collector terminals of the drive transistors 3d in FIG. 2 are made to match the reference numerals of the display sides and dot display portions shown in the dot display shown in FIG. FIG. 4 shows a plurality of dot displays 2 displayed by the method of the present invention connected to a multiplexer 6.
This shows an example of time-division driving using .

Note that 4 is a BCD code signal generator, and 5 is a counter. By configuring such a circuit, dynamic display is possible. As is clear from the above explanation, this invention
1 by signal processing the output of the 7-segment decoder.
Since the dot display can be driven by the display side divided into six groups and the dot display section, it is possible to obtain a display that is much easier to see than the conventional seven-segment display.

Particularly, in cases where the existing 7-segment display is difficult to view, the display form can be changed using the output without replacing the decoder, resulting in fewer replacement parts.

Note that the dot display shown in FIG. 1 may use a liquid crystal instead of a light emitting diode.

[Brief explanation of drawings]

Fig. 1 is a front layout diagram of the dot display, Fig. 2 is a drive circuit diagram of the dot display according to the present invention, Fig. 3 is a display pattern diagram of the dot display from 0 to 9, and Fig. 4 is a dynamic diagram. FIG. 4 is a block diagram when driving. 1: J segment decoder, 2: Dot display, 3:
Signal conversion device, 3a: inverter circuit, 3b, 3c: gate circuit, 3d: drive transistor circuit.

Claims (1)

[Claims] 1. A dot display divided into a display side and a dot display section, and a signal conversion process in which the display side and dot display section correspond to the numerical display output of a 7-segment decoder, resulting in a 7-segment display. 1. A method for driving a dot display using an output from a 7-segment decoder, characterized in that the dot display is driven by the output.