JPS5936051U - reset circuit - Google Patents
reset circuitInfo
- Publication number
- JPS5936051U JPS5936051U JP13003082U JP13003082U JPS5936051U JP S5936051 U JPS5936051 U JP S5936051U JP 13003082 U JP13003082 U JP 13003082U JP 13003082 U JP13003082 U JP 13003082U JP S5936051 U JPS5936051 U JP S5936051U
- Authority
- JP
- Japan
- Prior art keywords
- switch
- turned
- ejecting
- cassette
- reset circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Nonmetal Cutting Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図及び第2図は挿入スイッチと排出スイッチの動作
状態をカセットの挿入位置対応に図示した図、第・3図
はカセットの挿入排出時における挿入スイッチと排出ス
イッチの動作状態を示す図、第4図はこの考案の実施例
を表わす構成図、第5図はIC34の真理値表を示す図
、第6図はこの考案の別の実施例を表わす回路図である
。
1はカセット、2は挿入スイッチ、3は排出スイッチ、
4はアクチュエータ、5はホルダ、6はレバー、30は
電源端子、31は挿入スイッチのスイッチ情報が加わる
入力端子、32は排出スイッチのスイッチ情報が加わる
入力端子、33はリセット信号の出力端子、34は単安
定マルチバイブレークを構成するIC170はパルス発
生回路、 71は禁止ゲートである。
譚入時
排出時1 and 2 are diagrams showing the operating states of the insertion switch and the ejecting switch corresponding to the insertion position of the cassette, and FIGS. 3 and 3 are diagrams showing the operating state of the insertion switch and the ejecting switch when inserting and ejecting the cassette, FIG. 4 is a block diagram showing an embodiment of this invention, FIG. 5 is a diagram showing a truth table of the IC 34, and FIG. 6 is a circuit diagram showing another embodiment of this invention. 1 is the cassette, 2 is the insertion switch, 3 is the ejection switch,
4 is an actuator, 5 is a holder, 6 is a lever, 30 is a power supply terminal, 31 is an input terminal to which switch information of the insertion switch is added, 32 is an input terminal to which switch information of the ejection switch is added, 33 is an output terminal of a reset signal, 34 IC 170 is a pulse generation circuit which constitutes a monostable multi-by-break, and 71 is an inhibit gate. At the time of entry and exit
Claims (1)
オートローディング、オートエジェクト制御用マイクロ
コンピュータがリセットされて排出スイッチをオフにす
る動作を伴うローディング動作が行なわれ、カセット排
出時は前記挿入スイッチがオフされて後前記排出スイッ
チがオンとなり該排出スイッチのオン時にエジェクト動
作を終了せしめるカセットテープレコーダにおけるリセ
ット回路において、前記挿入スイッチのオン時に前記マ
イクロコンピュータに加えるリセットパルスを発生する
パルス発生回路と、該パルス発生回路の出力を前記排出
スイッチのオフ期間中禁止するゲート手段とを県備した
ことを特徴とするリセット回路。When inserting a cassette, the insertion switch is turned on, which resets the microcomputer for auto-loading and auto-ejection control, and a loading operation is performed that involves turning off the ejection switch.When ejecting the cassette, the insertion switch is turned off. After the insertion switch is turned on, the ejecting switch is turned on, and the ejecting operation is terminated when the ejecting switch is turned on.The reset circuit in the cassette tape recorder includes: a pulse generating circuit that generates a reset pulse to be applied to the microcomputer when the insertion switch is turned on; 1. A reset circuit comprising: gate means for inhibiting the output of the generating circuit during the off period of the discharge switch.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13003082U JPS5936051U (en) | 1982-08-28 | 1982-08-28 | reset circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13003082U JPS5936051U (en) | 1982-08-28 | 1982-08-28 | reset circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5936051U true JPS5936051U (en) | 1984-03-06 |
JPH0249010Y2 JPH0249010Y2 (en) | 1990-12-21 |
Family
ID=30294438
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13003082U Granted JPS5936051U (en) | 1982-08-28 | 1982-08-28 | reset circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5936051U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0294721A (en) * | 1988-09-30 | 1990-04-05 | Nec Corp | Spectrum inversion privacy telephone system |
-
1982
- 1982-08-28 JP JP13003082U patent/JPS5936051U/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0294721A (en) * | 1988-09-30 | 1990-04-05 | Nec Corp | Spectrum inversion privacy telephone system |
Also Published As
Publication number | Publication date |
---|---|
JPH0249010Y2 (en) | 1990-12-21 |
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