JPS5935213B2 - ladder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ladder network circuit operating system in which output deviation can be easily adjusted and the configuration of the circuit used is also extremely simple.

In general, a feedback type analog-to-digital converter (hereinafter referred to as A-
Ladder network circuits are used for the D converter) and the digital-to-analog converter (hereinafter referred to as the DA converter).

The ladder network circuit referred to herein includes a local decoder in the A-D converter ζ, a ladder network in the D-A converter, a constant current source, and a current switch connected thereto.

FIG. 1A is a block diagram of an A-D converter, including a sampling circuit and holding circuit 1, a comparison circuit 2, a distribution circuit 3, a ladder network 4, a ladder network switch 5, a logic circuit and a memory circuit 6,
It consists of a buffer circuit 7.

FIG. 1 is a block diagram of the Tama D-A converter, including a buffer circuit 8, a ladder network switch 9, a ladder network 10, and a resampling system 1.
It consists of 1.

The ladder network circuit shown in FIG. 2 is used as the ladder network 4 and the ladder network switch 5 of the A-D converter, and the ladder network switch 9 and the ladder network 10 of the D-A converter.

That is, the ladder network circuit used as the ladder network 4 and the ladder network switch 5 receives the input PAM signal (PAM signal) in the comparator circuit 2.
M: pulse amplitude modulation) and the reference signal whose amplitude value is compared, and the ladder network circuit used as the ladder network switch 9 and the ladder network 10 are sampled by the resampling system 11 and converted into a PAM signal. It plays the role of generating analog outputs according to the input digital information indicated by the connection state of the constant current sources connected to each mode of the ladder network circuit.

Next, the operation of the ladder network circuit shown in FIG. 2 will be explained.

There are various possible correspondences between the level of the analog signal and the combination of each signal value (0 or 1) of the digital signal obtained by converting it, but here we will use the level of the analog signal as the simplest and most convenient way. Let us consider the case where the magnitude of the digital signal corresponds to the value when the arrangement of each signal value of the digital signal is considered to be a binary number.

That is, for example, if the level of the input analog signal is between 0 [■] and 1 [V], the following correspondence is made.

Input analog signal Converted digital signal Now, this ladder network circuit generates an analog output Vout at the output terminal according to the digital signal, but Rl in the figure
k (k = 1..., n) as parallel arm resistance R2k (k
= 1, ., n-1) is called the series arm resistance, and normally, if the value of R2□ is r, then R2k (k = 1, -
--n -1) and R1n as rlRlk(k=2,...
, n-1) is set to 2r.

R11 may be anything, but it is easier to understand if 4 is considered to be r for convenience.

Further, the symbol 5Wk (k=1, . . . , n) is a switch, and each corresponds to each digit of the binary number of the digital signal.

However, the smaller node number corresponds to the upper digit of the binary number.

Furthermore, Ik (k=1° . . . , n) is a constant current source in which all current values are constant.

A ladder network circuit with such a configuration is usually called an r-2r ladder network circuit, and in this circuit, when each bit of the binary number is 1, the switch 5Wk (k = 1..., n) is closed and the value is 0. If the voltage level of the analog output Vout is opened when
It is proportional to its value when considered as a base number.

In addition, each constant current source ■k (k-1゜-・-,
n) are all ladder wire resistances R1k (k=1,”・,n)
.

Although it is provided in the direction in which the current flows into the R2k (k=1, ''·, n 1 ) side, even if it is reversed, the polarity of the analog output Vout will only be reversed.

However, in this specification, in order to avoid confusion, unless otherwise specified, the orientation shown in the drawings will be used.

Therefore, even if the directions of the currents and the polarities of the voltages are reversed throughout this specification, the absolute values of the currents and voltages will maintain exactly the same properties.

Furthermore, it goes without saying that the constant current source Ik (k=1...n) can actually be constructed from a circuit using transistors, diodes, and the like.

By the way, the ladder network circuit explained with reference to FIG.
), and a ladder network circuit is also known in which the minimum value and maximum value are symmetrical about the OCV.

For example, if we consider a 5-stage ladder network circuit and the level of the PAM signal is from -1 [■] to +1 [■], then the digital input signal "ooooo" (hereinafter "゛°'" indicates a binary number)
-1 (V) &("1]111" +1. (V)
, set “10000” and “01111” to 0(V)+
Either this is made to correspond (see (a) below), or the value set to 0 [■] is shifted evenly upward by 0 with respect to O [■] (see (b) below).

(a) 011・・・・・・・・・・・・ 1→0
[■] 100・・・・・・・・・・・・0→0 [■]
Δ (D)011・・・・・・・・・・・・1→−−(V
)Δ 100・・・・・・・・・・・・0→-1−(V〕Δ
: Minimum quantization step width FIGS. 3 to 5 are circuit diagrams representing different embodiments of ladder network circuits that output bipolar outputs.

In the case of the circuit shown in FIG. 3, the input digital information Di (i=
1, 2. -..., when n) is 1, connect the constant current source in the direction in which the current flows into the ladder wire resistance side, as in the case of the circuit shown in Figure 2, but when it is 0, instead of opening the switch. A constant current source I having the same current value and opposite direction as the constant current source
It is connected to in.

In this way, the output voltage will have a symmetrical dynamic range with O [■] as the center. In the case of the circuit shown in Fig. 4, the switch 5i (i21, . . .
・The operation etc. of This creates a wide dynamic range.

In the case of the circuit shown in Figure 5, for a positive input signal, the second
The operation is the same as in the case shown in the figure, and for the negative input signal ζ, by using a constant current source pointing out instead of a constant current source pointing in, the center ζ This provides a symmetrical dynamic range.

That is, to make 00...0'' correspond to the minimum level and 11...1'' to the maximum level, if the input signal is positive and Di = 1, then the constant current source I i pG is connected D i =
If it is O, it is open when the input signal is negative, and if Di21 is open, if it is Di20, it may be connected to the constant current source Iin.

Now, consider the deviation in the ladder network circuit.

If each resistor and constant current source constituting the ladder network circuit are ideally made, the above-mentioned correspondence between the output PAM input signal and digital signal can be perfectly achieved.

However, in reality, these components have deviations, so there is a difference between the output PAM and input signals, and this becomes a deterioration value of the static characteristics in the ladder network circuit.

Normally, when designing a system of A-D converters and DA converters, an allowable amount of deterioration depending on this factor ζ is allocated as deterioration allocation.

In order to suppress the deterioration value within this allocated value, first,
It is possible to suppress the deviation of each component within a certain range.

However, it is not easy to suppress the deviations of each component so that characteristics are within allowable deterioration.
Furthermore, even if it is possible, it would be unreasonable in terms of cost.

In addition, in addition to the initial deviation, each component has fluctuations over time, temperature fluctuations, etc. When these factors are taken into account, the initial deviation allowed for each component becomes even more severe.

The above problems of deviation and precision are particularly important in ladder network circuits used in successive approximation feedback linear encoders.

For example, consider the deviation in the circuit shown in FIG.

This circuit configuration originally had a P of 0 (V) as the minimum level.
A constant current source I is used for a unipolar output type that receives an AM input signal.
By adding O, the output level is shifted and input 2
Bipolar output is achieved by adjusting the output level to 0 when the leading signal is exactly at the center.

However, if such a configuration is applied to, for example, a folded linear encoder equivalent to n-bit encoding with a minimum step width of m bits within the folded line, it is necessary to In order to obtain accuracy, it is necessary to consider the deviation with respect to an m-stage ladder network circuit, and in order to obtain an output with n-bit precision, a circuit with Q-m-bit precision is required, which is extremely unreasonable.

This also applies to the circuit shown in FIG.

Conventionally, with respect to such a gap, the deviation has been reduced by using the configuration shown in FIG. 5, for example.

In other words, in the case of the circuit shown in Figure 5, the highest binary number determines whether the force is greater than the median value, and for inputs with a level greater than the median value, the When facing the switch, switch to the left side, for example, if it is the first stage, switch to terminal C and connect it to the corresponding constant current source, and connect the switch at the node where 0 stands to the open switch in the center, for example, if it is the first stage, connect it to terminal C. For inputs with a level smaller than the median value of the inverse Q, the switch at the node where 1 is set is placed in the open position in the center, and the switch at the node where 0 is set is placed on the right side. For example, in the first stage, bipolar output is obtained by switching to terminal A.

Therefore, to obtain an m-bit output, a ladder network circuit with m-1 stages is required.

In this configuration, when the inputs "01111...1" (former) and "10000...0" (latter) have output characteristics as shown in Figure 6, both ζ are 0 [■] , when the output characteristics are as shown in FIG.
The deviation can be reduced by adding a current source corresponding to the most significant digit so that c is matched.

Such a conventional deviation adjustment method is easy to adjust even in the case of a polygonal encoder, but there are two points to implement this method.
Double the number of constant current sources is required, and the circuit configuration of the switch portion also becomes complicated.

The present invention provides a ladder network circuit configuration that provides bipolar output.
For example, the purpose is to make the circuit as shown in Fig. 4 as simple as possible, and according to the above expression t, if the output has n-bit precision, it can be handled with the precision of n stages. (1) Passive element circuit network, a group of current switches that independently turn on and off the current supplied to the passive element circuit network, and a group of current switches ζ that are connected in correspondence with each other and that when the current switches are turned on, A zero point is placed at the output of the digital-to-analog converter at the connection point between the circuit group each having a constant current source group that supplies a directional current and the circuit corresponding to the most significant digit of the digital input among the circuit groups. It includes a bias current source connected to have a symmetrical spread around the center, that is, a bipolar dynamic range, and is expressed by a combination of the on/off states of each of the current switches at a predetermined terminal in the circuit. In a ladder network circuit that generates an analog signal at an output level corresponding to a binary input digital signal, a test period is provided periodically in the operating state, and one or more predetermined digital signals are detected during the test period. A determining means for comparing and determining whether an output corresponding to an input is greater than one or more predetermined values, a holding means for holding a determination result by the determining means, and a holding result by the holding means ζ and a smoothing means for smoothing the current, and the value of the bias current source and the value of the constant current source that causes the same current to flow in or out through a current switch connected to the bias current source according to the output of the smoothing means. A ladder network circuit operating method characterized in that one or both of them are adjusted so that an output corresponding to one or more predetermined digital inputs matches one or more predetermined values.

(2) The present invention provides the ladder network circuit operating method according to item 1 above, characterized in that the period of sampling operation of the input analog signal is used as the testing period of the ladder network circuit, which will be described in detail below. do.

In the present invention, digital inputs (check mode) at both levels of 0 [■] as described above are applied to the ladder network circuit for a predetermined period of time, and depending on the state of the output, a constant current source of the highest digit is applied. In addition, the value of the constant current source for level shifting is adjusted to obtain predetermined characteristics.

FIG. 8 is a circuit diagram of the main part of the circuit used in the first embodiment of the present invention. In the figure, CP is the comparator. ,
FF1. FF2 is a flip-flop circuit, LPo, L
P2 each indicates a low pass filter.

In this embodiment, in the check mode, first, the input is set to the check mode "1oooo", the PAM signal output from the ladder network circuit at that time is compared with the O level by the comparator CP, and the result is flipped.・Flop circuit FF,
to hold.

That is, the flip-flop circuit FF1 has, for example, '
If 000...0'' is thicker than 0 [V], 1 is held, and if it is smaller, O is held.

Next, the check mode "011...1" is input, and the output PAM signal at that time is compared with the O level by the comparator CP, and the result is held in the flip-flop circuit FF2.

The values of the flip-flop circuits F Fl and F F2 are low pass filter LP1.

Smoothed by LP2, resulting in a constant current source
The current values of o and l are controlled.

That is, for the constant current source ■o, for example, if the output when the input of check mode 011...1 is applied is more than 0, then Io is changed in the direction of increasing Io. Adjust 0 to lower the potential of the output terminal, and conversely, if it is smaller than 0, make 0 smaller to raise the output potential.

Regarding ■1, for example, check mode 10...
Add 0, and if the result is greater than 0, ■ decrease 1 to lower the output potential, and conversely, if it is smaller than O, ■ increase 1 to increase the output potential. Adjust the potential.

Similarly, in constant current source ■1, if the output in check mode ゛100...0'' is less than 0, then the smaller one, and if it is less than 0, the larger one (that current value is adjusted.

■ in Figure 8.

Since tll is a current source circuit, it needs to be controlled by some kind of analog signal.

Furthermore, since the judgment of correction is a result of either right or wrong, the simplest method for transmitting it as analog information is to integrate the judgment result.

The period of integration is made sufficiently longer than the period of determination so that drastic corrections are not made based on only one courtyard result.

That is, if the average information of the judgment results is not adjusted, and the adjustment ζ is made based on only one judgment result, the level will fluctuate, which will have the opposite effect.

We have also shown a general method of holding the judgment result in a flip-flop FF, smoothing the result with a low-pass filter, and converting it into analog information. It is also possible to count digitally and generate an adjustment level from the result.

In this way, the output PAM signal always has a center level of 0.
It is controlled so that it approaches [■], and the output deviation is suppressed.

In this embodiment, the effect is obtained by only adding a small number of control circuits.

That is, without complicating the configuration of the ladder network circuit, the output level can be checked in the same manner as in the circuit shown in FIG. 5, and a highly accurate output can be obtained at a low level.

Furthermore, by providing a check mode at any time, it is possible to cope with temperature fluctuations and temporal fluctuations.

Incidentally, in the case of the output characteristics shown in FIG. 7, the reference power supply of the comparator CP may be set to -7.

In this case, the mode may be switched accordingly, or a comparator may be provided separately.

Further, if necessary, it is also possible to control by comparing with an arbitrary level.

However, such cases are rare.

Various methods of inserting the check mode in the present invention are conceivable.

For example, when using this ladder network circuit as a local decoder of a feedback type A-D converter, the successive conversion time
Any free time slot on the chart can be used.

That is, in a feedback type A-D converter, as is clear from FIG. 9, one time stand is usually provided for holding in the sampling holding circuit.

For example, in an 8-bit A/D converter, the sampling period is divided into nine time slots, with the first time slot used to hold the input analog signal.

During this period, the local decoder is not used in its original role, so a check mode can be inserted at that time.

This can be easily realized by changing the settings of the logic circuit and memory circuit (see FIG. 1).

Furthermore, in the DA converter, it is also possible to utilize the time when no real signal is transmitted, such as the position of a synchronization signal on a transmission path.

In any case, the check mode insertion time is A-D
Alternatively, considering the application conditions of each D-A converter, it can be easily ensured, and considering the effect of the present invention on the deviation, it can be said to be extremely useful.

Incidentally, in the above embodiment, the explanation was made using binary levels and adjustments, but for example, a certain level ■1 and the corresponding code C1, and level -■1 and the corresponding code C-1 are the two points mentioned above. Using a total of 4 points in addition to 1, set 1 to a large level (for example, the maximum level) ζ From this, adjust in two areas, small level and large level, to determine the overall deviation and the deviation seen at the small level. It is also possible to make corrections.

However, increasing the level value increases the number of circuits, so the above example is desirable in practice.

As can be seen from the above explanation, according to the present invention, the feedback type A-
By simply adding an extremely simple correction circuit to the ladder network circuit used in the D converter or DA converter, the output deviation can be minimized.

[Brief explanation of the drawing]

Figure 1A is a block diagram of a feedback type A-D converter using a ladder network circuit.
A block diagram of the A converter; Figure 2 is a circuit diagram of a ladder network circuit that provides a unipolar output; Figures 3 to 5 are circuit diagrams of a ladder network circuit that provides a bipolar output; Figures 6 and 5 are diagrams of a ladder network circuit that provides a bipolar output; Figure 7 is D-
A diagram showing the input/output characteristics of the A converter, Fig. 8 is a circuit diagram of the main part of the circuit used in one embodiment of the present invention, and Fig. 9 is a feedback type A-D.
The operating time charts of the converters are respectively shown. In the figure, Rlk (k=1...n) is the parallel arm resistance, R2k (k=1,..., n) is the series arm resistance, and SWk (k=1, -, n) is the switch. , Ik (k=o, −・−, n) is a constant current source, Nk (
k=1°..., n) is a node, Dk (k=1, m
, n) is digital input terminal, CP is comparator, FF
I, FF2 are flip-flop circuits, LP, LP2
indicate low pass filters, respectively.

Claims (1)

[Scope of Claims] 1. A passive element circuit network, a group of current switches that each independently turn on and off the current supplied to the passive element circuit network, and a current switch connected to the current switch group in a corresponding manner. A connection point between a circuit group each having a constant current source group that supplies a unidirectional current when the circuit is turned on, and a circuit corresponding to the most significant digit of the digital input among these circuit groups. The output of the digital-to-analog converter includes a bias current source connected to have a symmetrical spread around the zero point, that is, a bipolar dynamic range, and each of the current switches is connected to a predetermined terminal in the circuit. In a ladder network circuit that generates an analog signal with an output level corresponding to a binary input digital signal expressed by a combination of on and off states, a test period is set periodically in the operating state, and the test period is determining means for comparing and determining whether an output corresponding to one or more predetermined digital signal inputs is larger than one or more predetermined values; and a holding means for holding the determination result by the determining means. and smoothing means for smoothing the holding result by the holding means, and depending on the output of the smoothing means, the value of the bias current source and the current flowing into the same point via a current switch connected to the point ζ, or Ladder network circuit operation characterized in that one or both of the values of the constant current source to be drained is adjusted so that the output for one or more predetermined digital inputs matches one or more predetermined values. method. 2. Claim 1 characterized in that the period of sampling operation of the human-powered analog signal is used as the inspection period of the ladder network circuit.
Ladder network circuit operating method as described in .