JPS5935035B2 - frequency signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency signal generator that can be used as a tone generator for electronic musical instruments.

As a conventionally known tone generator for electronic musical instruments, there is one that uses a frequency dividing circuit.

In this method, the highest frequency signal is successively frequency-divided by multiple stages of frequency dividing circuits to obtain square wave pulse signals of multiple frequencies in parallel. For example, if the number of notes in one octave is 12 and the number of octaves is 5, 60 types of frequency signals can be obtained in parallel. These frequency signals, or sound source signals, are selected according to key presses on the keyboard.
When a plurality of sound generation channels are provided to enable simultaneous generation of a plurality of sounds, all frequency signals are supplied to each sound generation channel, and for each sound generation channel, the frequency signal of the sound assigned to that channel is selected. In this case, since all frequency signals must be supplied to the selection circuits of each channel, there is a drawback that the number of frequency signal supply lines becomes considerably large. For example, if the number of channels is 12, then 720 (60 x 1
(2) wiring is required. To reduce the number of wires,
It is conceivable to provide a frequency dividing circuit for each channel and supply the highest frequency signal of each note name (C-B) to the frequency dividing circuit of each channel, but in this case, each channel Since the frequency dividing operation is performed separately in , there is a drawback that when notes with the same note name are assigned to different channels, the phases may be reversed. For example, when sounds with the same pitch name are assigned to two channels, and the frequency-divided outputs of both channels are exactly opposite in phase, a situation arises in which the sounds generated in both channels cancel each other out and no sound is produced at all. This invention was made in order to eliminate the above-mentioned inconvenience, and by making it possible to generate multiple frequency signals by superimposing them, multiple frequency signals can be generated using fewer wiring lines than the number of these signals. It is designed to be able to send out signals.

This invention can generate a square wave signal consisting of binary logic levels of "1" and 60 degrees by digitally superimposing multiple frequencies, and at least the logic level of the highest frequency square wave is inverted. Each time, the logic level data of each square wave signal of a different frequency at that time is serialized and generated, thereby superimposing a plurality of frequency signals.

By replacing the logic level data of each serialized square wave signal with parallel data and storing and holding each, continuous square wave waveform signals of a plurality of frequencies can be obtained in parallel. When applying this invention to a tone generator for an electronic musical instrument, multiple stages of frequency-divided data are serialized and generated sequentially, thereby superimposing frequency-divided signals of multiple frequencies, and converting this frequency-divided data string into parallel data. By replacing them and storing them separately, a plurality of square-wave frequency-divided signals can be obtained separately. Hereinafter, the present invention will be explained in detail based on the embodiments shown in the accompanying drawings.

In FIG. 1, a frequency signal generator 1 according to the present invention
0 generates a plurality of frequency signals obtained by dividing a signal of a certain frequency, that is, a plurality of stages of frequency division signals.

In this frequency signal generator 10, a superimposed frequency-divided signal generating section 11 generates a plurality of frequency-divided signals related to a signal of a certain frequency by superimposing them, and this superimposed frequency-divided signal is received via a line 13. The information is sent to section 12. The superimposed frequency-divided signal receiving section 12 extracts individual frequency-divided signals from the superimposed frequency-divided signal and makes each frequency-divided signal usable. In the figure, multiple input type logic elements such as AND circuits and OR circuits are illustrated using the illustration method shown in FIGS. 2a and 2b.

This draws one input line on the input side and draws multiple signal lines orthogonal to this input line. The intersection point between the signal line of the signal to be input to the circuit and the input line is surrounded by a circle. For example, the conditional expression for the AND circuit in Figure 2a is A-B-D=Q, and the conditional expression for the OR circuit in Figure 2b is A.
+B+C=Q. The delay flip-flop adopts the method shown in FIG. 2c, and although the clock pulses for controlling the input/output timing are not particularly shown, they are all controlled by a common clock pulse. The period of this clock is called one bit time. The superimposed frequency division signal generation section 11 can be roughly divided into a digital oscillation section 14 and a frequency division data creation section 15.

The digital oscillator 14 counts clock pulses at a desired frequency division ratio to generate a fundamental pulse signal P of a desired frequency, and the frequency division data generator 15 sequentially divides the frequency of this fundamental pulse signal P. Digital data (ie, frequency-divided data) regarding a plurality of frequency-divided signals are created. This frequency-divided data is sent out serially via line 13. The digital oscillator 14 inputs a 7-stage/1-bit shift register 16 in which seven delay flip-flops and OR circuits are successively connected in cascade, and data A6 and A7 of the sixth and seventh stages of the shift register 16. A circuit consisting of an AND circuit 17, a NOR circuit 18, and a NOR circuit 19 to which the basic pulse signal P is input, and the shift register 1.
Data A1 from 1st stage power of 6 to 6th stage
It includes a maximum length counter (maximum length counter) consisting of a NOR circuit 20 inputting ~A6,
When the content of this maximum length counter reaches a preset value, the AND circuit 21 generates an output "1" with a width of 1 bit time. , or from the AND circuit 25 via the OR circuit 24 as the basic pulse signal P. The maximum length counter is set to an initial state by the basic pulse signal P applied via the line 26. Therefore, the maximum length counter consisting of the shift register 16 and the like repeats counting from the initial state every time the basic pulse signal P is applied.
The oscillation interval is determined according to the input connection state of the AND circuit 21 and control of whether or not the output of the AND circuit 21 is delayed via the delay flip-flop 22. The output data A1 to A7 of each stage of the shift register 16 is input to the AND circuit 21 directly or via an inverter.

In the example of FIG. 1, data Al, A2, A5, A6 and A
7 is directly input, and data A3 and A4 are inverted by an inverter and input. Therefore, when the contents of the maximum length counter, that is, the data A1 to A7 of the shift register 16 are 111001111, the input conditions of the AND circuit 21 are A1, A2, A3, A4, A5, A6,
A7 is established, and an output 611 is generated from the AND circuit 21.

When the signal on the control line 27 is "1", the AND circuit 23
is operable, AND circuit 25 is inoperative, and a signal delayed by one bit time via delay flip-flop 22 is selected.

Further, when the signal on the control line 27 is "0", the AND circuit 23 is inoperative, the AND circuit 25 is enabled, and the output of the AND circuit 21 is selected as is (without delay). Therefore, The input connection state of the AND circuit 21 is changed to the maximum length by the pulse signal P on the line 26.
The data contents A1 to A7 are detected when a predetermined number of N clock pulses (not shown) counted from when the counter was set to the initial state are applied to (each delay flip-flop of) the shift register 16. If the signal on the control line 27 is 60'', the basic pulse signal P is generated at an interval of N bit time (N base), and if the signal on the control line 27 is 61'', the pulse signal P is generated. occurs at an interval of N+1 bit time (N+1 base).In the end, the digital oscillator 14 divides the frequency of the clock pulse for the delay flip-flop to generate the basic pulse signal P, and the frequency division ratio is Almost set depending on the input connection state of the circuit 21,
Depending on the signal on control line 27, slight changes are made.
The actual oscillation period of the fundamental pulse signal P obtained by frequency division is scaled by the clock pulse period (for example, around 1 μs) for the delay flip-flop. The frequency division data creation section 15 includes delay flip-flops FF1 to FF7.
a 1-bit adder 28, and a carry output CO of the adder 28.
It has a delay flip-flop 29 which delays the signal by one bit time and feeds it back to the carry input Ci via an OR circuit 30 and an AND circuit 31, and performs a serial addition operation.

During the serial addition operation, the frequency division data creation section 15 serially shifts the contents of the delay flip-flops FFl to FF7, and transfers the pulse signal P given from the oscillation section 14 to the least significant bit (the bit of the delay flip-flop FF). Add to data. Control of whether to perform a serial addition operation, that is, a shift operation of delay flip-flops FF1 to FF7, or a memory operation is performed by the output of the set-reset type flip-flop 32. When the output of the flip-flop 32 is "11", the signal on the shift line 33 becomes "1", the signal on the memory line 34 becomes "O", and the upper delay flip-flop FF7
The held data is sequentially shifted from FF1 to the lower delay flip-flop FFl. Then, the output data of the lowest delay flip-flop FF1 is added to the basic pulse signal P or the carry signal from the delay flip-flop 29 in an adder 28, and the result is input to the highest delay flip-flop FF7. When the output of the flip-flop 32 is O'', the signal on the memory line 34 is 61.
Then, the signal on the shift line 33 becomes "0" and the data held in the delay flip-flops FF1 to FF7 is self-held.The flip-flop 32 operates only for a bit time corresponding to the number of stages of the register consisting of the delay flip-flops FF1 to FF7. produces a set output 61''.

To explain this point with reference to FIG. 3, when one basic pulse signal P is generated from the oscillator 14 as shown in FIG. is set. At this time, the signal 81'' is read into the second to seventh stages of the shift register 16 via the line 26, and the signal ``O'' is read into the first stage via the line 26 and the NOR circuit 19.
Since " is read, data A1 to T2 are read as shown in FIG. 3b at time slot T2 after one bit time.
A7 force 011111r". This data is sequentially shifted to the right, so as shown in Figure 3b, data A1~
A7 changes, time slot T8 after 7 bit time
At this point, the data A7 of the seventh stage of the shift register 16 falls to ``0''. This data A7 is inverted via the inverter 36 as shown in FIG. Therefore,
As shown in FIG. 3d, the flip-flop 32 is set only for 7 bit times (time slots t1 to T7) from when the basic pulse signal P rises to 111, producing a set output "1". The signal 1C applied to the circuit 35 is an initial clear signal that becomes "1" when the power is turned on. The data held by each delay flip-flop FFl to FF7 in the memory state (memory line 34 is 11) is represented by Q, to Q7, and the data output from the delay flip-flop FF1 in the shift state (shift line 33 is 11). The result is as shown in Figure 3e. That is, between time slots t1 to T7, delay flip-flop FFl outputs registers (FF, to FF7).
)'s held data Q1 to Q7 are serially output from the lowest order. The output of the delay flip-flop FFl is applied to the addition input A of the adder 28 via an AND circuit 37 and an OR circuit 38. To explain the serial addition operation, first, at time slot t1, the basic pulse signal P is applied to the addition input Cl of the adder 28 via the OR circuit 30 and the AND circuit 31. The AND circuit 31 is enabled to operate from time slot t1 to time slot T7 by the signal 61' on the shift line 33. In this time slot t1, the least significant bit data Q from the delay flip-flop FF1 is applied to the adder 28, so that the pulse signal P and the least significant bit data Q1 are subtracted. The addition result (this is referred to as Q1') is input from the output terminal S to the delay flip-flop FF7, and the carry output CO at that time is
is added to the delay flip-flop 29. In the next time slot T2, the pulse signal P disappears, but the carry signal from the lower bit temporarily held in the delay flip-flop 29 is applied to the addition input Cl and added to the data Q2. Thereafter, the carry signal from the addition result of the lower bits and the data Q3 to Q7 of the upper bits are sequentially added, and the serial addition ends at time slot T7. At the end of this time slot T8, the output of the flip-flop 32 becomes 101, and the memory line 34 becomes 101.
11, so the addition results performed from time slot t1 to time slot T7 are added to each delay flip-flop FFl-F.
Self-maintained at F7. As a result, the basic pulse P is frequency-divided by 163264128 at a frequency division ratio of - by the serial addition in the frequency-divided data creation section 15, and the frequency-divided data corresponding to the logic level of each frequency-divided signal is applied to each delay flip-flop FF1 to FF7. Each will be stored in memory.

The frequency division data Q1 to Q7 created as described above in the frequency division data creation section 15 are connected to the line 39 and the OR circuit 4.
0 and are output in series via the AND circuit 41.

The AND circuit 41 is enabled to operate only during the time slots t1 to T7 in FIG. 3 by the output of the flip-flop 32, and the frequency-divided data is output only during this period. That is, the output data Q1 to Q7 of the delay flip-flop FFl, which occurs as shown in FIG. . Since the aforementioned serial addition operation is performed after the delay flip-flop FFl, the frequency-divided data Q output via line 39
1 to Q7 represent the previous serial addition results. By the way, in the time slot t1, the basic pulse signal P passes through the OR circuit 40 and the AND circuit 41 to the line 1.
3 is output. Since this basic pulse signal P is always 1F' in time slot t1, the frequency divided data Q
1, and the data Q1 is canceled. Therefore, the contents of the data sent from the superimposed frequency division signal generator 11 to the line 13 are as shown in FIG. 3f. That is, by serializing the frequency-divided data Q2 to Q7, the frequency-divided signals are effectively superimposed. The basic pulse signal P appearing at the beginning of the frequency-divided data Q2 to Q7 is used as a timing signal when the superimposed frequency-divided signal receiving section 12 takes out each of the frequency-divided data Q2 to Q7 separately. It is extremely important to superimpose such a timing signal (G) together with the frequency-divided data (Q2 to Q7) in order to know the time slot where the superimposed frequency-divided signal is located. In the example shown in FIG. 1, slight switching changes in the generation intervals of the basic pulse signals P are made in a fixed combination while four pulse signals P are generated.

This combination is determined depending on the setting position of the switch 42.
The switch 42 has four terminals B1, B2, B3, and B4, and the basic pulse signal P is connected to the grounded terminal B1.
The signal "1" is not given even once during the period in which the signal "1" is given. The lowest frequency division data Q1 is input from the delay flip-flop FFl of the frequency division data generation section 15 to the terminal B2, and the signal "1" is inputted twice while the four basic pulse signals P are applied. given once. The frequency-divided data Q1 and Q2 held in delay flip-flops FFl and FF2 are applied to an AND circuit 43 and an OR circuit 44, the output of the AND circuit 43 is applied to terminal B3, and the output of the OR circuit 44 is applied to terminal B4. Therefore, the signal 11' is supplied to the terminal B3 only once while the basic pulse signal P is generated four times. Further, the signal "11" is applied to the terminal B4 three times while the four basic pulse signals P are generated. The values of the frequency division data Ql and Q2 of the lower 2 bits and each terminal B1 of the switch 42
Table 1 shows the relationship with the value of the signal applied to B4. The output of switch 42 is applied to control line 27 via delay flip-flop 45 to control the frequency division ratio of digital oscillator 14, that is, the generation interval of basic pulse signal P. As mentioned above, when the frequency division ratio set by the AND circuit 21 is N-ary, when the signal on the control line 27 reaches 11°'', the basic pulse signal P is generated at the N+1-ary frequency division ratio, and the line 2
When the signal of 7 becomes '0', it is generated at an N-adic frequency division ratio.
Therefore, in the digital oscillator 14, the basic pulse signal P
The division ratio for generating is always N-ary when the switch 42 is set to terminal B1, but it is a repetition of N-ary and N+1-ary when set to terminal B2, and when it is set to terminal B3. is N+1 base only once after continuing N base 3 times, and if set to terminal B4, N+ is performed once in N base and then N+
Continue the 1-decimal sequence three times. In the example of FIG. 1, switch 4
2 is set at the position of terminal B4.

The input conditions of the AND circuit 21 in the digital oscillator 14 are "A1, A2, A3, A4, A5, A6, A
7'', which means that the maximum length counter in the configuration shown in the figure is set to 112 (N=112). The generation state of the basic pulse signal P in this case is shown in FIG. 4a. The numbers in FIG. 4a indicate the number of clock pulses included therebetween, that is, the division ratio with reference to the clock pulses. As mentioned above, the AND circuit 41 outputs the basic pulse signal P and then the frequency-divided data Q.
2 to Q7 are output in series. Figure 4b is line 13
This frequency-divided data string Dl, D2, D3...
This shows the state of occurrence. Each frequency-divided data string Dl,
As shown in FIG. 3f, D2, D3, . . . include frequency-divided data Q2 to Q7, respectively, with the basic pulse signal P at the beginning. Since the frequency division data Q2 with the smallest frequency division ratio is obtained by dividing the basic pulse signal P by one, its value changes to "1" or "O" every time two reference pulse signals P are generated.
to be reversed. Therefore, if a frequency-divided data string is generated at the generation period of the basic pulse signal P, the data string with the same content will continue twice as Dl, Dl, D2, D2, etc., as shown in FIG. 4b. . Frequency division data string Dl, D2, D3...
* may occur only once each, but there is no particular problem even if they occur twice in succession as in this example. Frequency division data Q2 and Q3 are extracted as an example of the data contents in each frequency division data string Dl, D2, D3, . . . and are shown in FIGS. 4c and 4d. Table 3 shows changes in the data contents of the frequency-divided data sequences Dl, D2, . . . over a longer period of time. Among the frequency-divided data Q2 to Q7, the frequency-divided data Q2 repeats inversion of "1" and "0" at the earliest cycle.

Therefore, the frequency signal generated based on the frequency division data Q2 is the highest frequency signal. As is clear from the numbers shown in FIG. 4a, in the example of FIG. 1, the frequency signal obtained based on the frequency division data Q2 is the frequency signal obtained by dividing the frequency of the tarock pulse for driving the delay flip-flop 1 by one. That is, the frequency division data Q2 is obtained by dividing the basic pulse signal P by 1, and in this example, the clock pulse is divided by one frequency once, and then divided by one frequency three times to obtain four clock pulses. This is because the basic pulse signal P is generated. The frequency signals obtained based on the frequency division data Q3, Q4, Q5, Q6, and Q7 are obtained by dividing the highest frequency signal corresponding to the frequency division data Q2 by −, −, 1, −, and 1, respectively.2481632 Ru.

Therefore, data of a plurality of frequency signals having an octave relationship are generated in a superimposed manner. The reason why the switch 42 is provided to allow slight changes in the division ratio is that the Maxima
This is because it is possible to obtain delicate frequency division ratios that cannot be divided by the length counter alone. That is, when the maximum length counter reaches N-ary, the AND circuit 21
Assuming that the switch 42 operates, the four terminals B1 to B1 of the switch 42
4N base, 4N+1 base, 4N+2 base 4 corresponding to B4
It is possible to obtain the frequency-divided data Q2 with a slightly different frequency division ratio of N+ternary. As described above, the frequency division data Q2 to Q7 are serially superimposed and outputted from the superimposed frequency division signal generating section 11 every time the basic pulse signal P is generated. These superimposed frequency-divided signals are applied to the shift register 46 of the superimposed frequency-divided signal receiving section 12 via line 13. The shift register 46 and delay flip-flops of the receiving section 12 are thus operated synchronously with the same clock pulses as the generating section 11. The seven-stage shift register 46 sequentially performs a serial shift operation from the first stage S1 to the seventh stage S7, and the basic pulse signal P and frequency division data Q2 to Q7 given via the line 13 are sequentially read. .

The frequency divided data Q2 is serially transmitted by this shift register 46.
-Q7 are parallelized and the parallelized data Q2-Q7 are stored in the latch circuit 47. A basic pulse signal P is used as a timing signal to control the latch timing of the latch circuit 47.
is used. Since the frequency-divided data Q2 to Q7 are always sent out after the basic pulse signal P, no signal appears on line 13 for at least 6 bit times immediately before the basic pulse signal P appears on line 13 (10 ). Therefore, when the basic pulse signal P is read into the first stage S1 of the shift register 46, the outputs of the second stage S2 to the seventh stage S7, which represent the signal states of the immediately preceding 6 bit times, are all 40°. This time is the fifth
In the figure, the timing is indicated by t/. The NOR circuit 48 is for detecting this timing t'1, that is, the arrival time of the frequency-divided data string D1 or D2 or I)3 . As the basic pulse signal P is read into the first stage S1 of the shift register 46, the output of the first stage S1 becomes 611, and the output of the inverter 49 becomes 10. The output of the inverter 49 and the outputs of the second stage S2 to the seventh stage S7 are input to the NOR circuit 48, and an output 6r'' is generated at timing t/.The output 01n of the NOR circuit 48 is of the set-reset type. The flip-flop 50 applied to the set input of the flip-flop 50 enters the set state as shown in FIG. 5b, and its set output is applied to the AND circuit 52 after being delayed by one bit time by the delay flip-flop 51 as shown in FIG. 5c. From timing t/ to T7'
, each stage S1 to S of the shift register 46
7, the frequency-divided data Q2 to Q7 are sequentially shifted as shown in FIG. 5a. At timing T7', the basic pulse signal P is transferred to the seventh stage S7 of the shift register 46.
The stage has been shifted from 1st stage S1 to 6th stage S1.
By stage S6, all frequency divided data Q7, Q6,
...Q2 is held respectively. At timing T7', the signal 61' (signal P) output from the seventh stage S7 of the shift register 46 is applied to the reset input of the flip-flop 50 and also to the AND circuit 52. Therefore, as shown in FIG. 5b, the flip-flop 50 is reset, but the delay flip-flop 51 falls to ``0'' one bit time later, so the AND circuit 52 is still operable at timing T7'. Then, a latch command signal L is applied from the AND circuit 52 to the latch circuit 447 as shown in FIG. 5d. In the latch circuit 47, based on this latch command signal L, the frequency dividing stages Q7, Q6, . . .
2 into 6 memory locations in parallel. Therefore, the frequency-divided data Q2 to Q7 that are intermittently generated at the generation period of the basic pulse signal P are stored and held in the latch circuit 47 and converted into a continuous signal. The level (111, 60") of the signal output from each storage location of the latch circuit 47 is line 1.
It changes every time the level of each frequency-divided data Q2 to Q7 given through 3 changes. Therefore, the superimposed frequency division signal generation section 11
6 superimposed frequency-divided data Q2 to Q7 output from
Six frequency signals (square wave pulses) corresponding to the above are individually output from the latch circuit 47, that is, from the superimposed frequency divided signal receiving section 12. FIGS. 4E and 4F show square wave frequency signals output from the latch circuit 47 based on the frequency division data Q2 and Q3, respectively. Figure 6 shows an example of applying this invention to a tone generator for an electronic musical instrument.
If the maximum number of simultaneous sound generation is n notes, tone generation series 53-1 to 53-n are provided corresponding to n sound generation channels, respectively.

Although the internal outline of only the musical tone generation series 53-1 is illustrated, the other musical tone generation series 53-2 to 53-n have the same configuration. The pressed key detection circuit 55 detects the pressed key on the keyboard 54 and supplies information representing the pressed key to the sound generation assignment circuit 56. The sound generation assignment circuit 56 is for allocating the sound of the pressed key to an appropriate sound generation channel. Key data KD of the pressed key is generated corresponding to the assigned sound channel. The key data KD includes note data N1 representing the note name of the pressed key assigned to that channel...
, octave data 01 representing the octave range of the key
. . . key-on data K that becomes "1" when the key is pressed and becomes "O" when the key is released, etc. are included. The key data KD corresponding to each channel is the musical tone generation series 53-1 to 53- corresponding to that channel.
Used in n. For example, the key data (note data N1, octave data 01, key-on data K1) of the key assigned to the first channel is used in the tone generation series 53-1 corresponding to the first channel. Further, the key data (note data N2, octave data 02, key-on data K2) of the key assigned to the second channel is used in the musical tone generation sequence 53-2 corresponding to the second channel, and is assigned to the n-th channel. Key key data K
D(Nn, On, Kn) is used in the tone generation series 53-n corresponding to the n-th channel. As the key press detection circuit 55 and the sound generation assignment circuit 56, for example,
The device described in the specification of No. 100879 (Japanese Unexamined Patent Publication No. 52-24518) entitled "Key switch detection processing device" or any other appropriate device can be used.

In the above device, the key data KD of each channel is generated from the sound generation allocation circuit 56 in a time-divisional manner, but in such a case, each musical tone generation series 53-1 to 53-n
key data (Nl,
Ol, Kl or N2, O2, K2...Nn, On
, Kn) are respectively latched and converted to a static state for use. Circuits 11-1 to 11-12 having the same configuration as the superimposed frequency-divided signal generating section 11 shown in FIG. 1 are provided corresponding to each of the 12 note names C+, D, . . . B, C, respectively. However, in each superimposed frequency division signal generation section 11-1 to 11-12, the input connection state of the AND circuit 21 (FIG. 1) in the digital oscillation section 14 and the setting mode of the frequency division ratio fine adjustment switch 42 (FIG. 1) are different from each other, and frequency division data Q2 to Q7 corresponding to the musical tone frequency of each note name C-B can be generated by superimposing them on the respective output lines 13-1 to 13-12. Table 2 shows an example of the input conditions (A, to A7) of the AND circuit 21 and the setting positions (B1 to B4) of the switch 42 in each of the generation units 11-1 to 11-12. In Table 2, the N column shows the original frequency division ratio obtained by the maximum length counter (shift register 16, etc.) according to the input connection state of the AND circuit 21,
Columns 2, 3, and 4 show the respective frequency division ratios when generating four basic pulse signals P, which differ slightly depending on the setting position of the switch 42. The Q2 column is the sum of the above four frequency division ratios, that is, the output lines 13-1 to 13-1.
2 shows the frequency division ratio of the frequency division data Q2 corresponding to the highest frequency among the frequency division data Q2 to Q7 of each note name derived from 2. The numbers indicating the frequency and frequency division ratio indicate the period of the frequency division signal when the period of the clock pulse for driving the shift registers is set to 1.

For example, if the period of this clock pulse is approximately 1 μs, the period of the frequency signal obtained based on the C tone frequency division data Q2 is approximately 239 μs, and this frequency is approximately 418 μs.
It becomes 4Hz. This is the frequency of the 8-foot C8 note. Further, the period of the frequency signal obtained based on the frequency division data Q2 of C≠sound is approximately 451 μs, and this frequency is approximately 2217 Hz. This is the frequency of the 8-foot C note. Therefore, each superimposed frequency division signal generation section 11-
The highest frequency signals obtained based on the frequency division data Q2 generated from 1 to 11-12 are signals of C7, D7, D7...A7, B7 and C8 sounds of the 8-foot system. . In addition, each generation unit 11-1 to 11-12 is
As described above, the six frequency-divided data Q2 to Q7 are generated by superimposing them. Here, the frequency-divided data Q3 to Q7 correspond to the frequency-divided data Q2 that is successively divided. Therefore, the frequency division data Q7 corresponding to the lowest frequency corresponds to the frequency division data Q2 divided by one, and the frequency division data Q7 corresponds to the frequency division data Q2 divided by one, and the tone (C to J: J et al. ) is obtained based on the frequency division data Q7. Therefore, in FIG. 6, when the period of the clock pulse is approximately 1 μs, the frequency division data Q2 to Q7 corresponding to the musical tone sound source signal in the range from Ct to C8 in the 8-foot system are generated in each superimposed frequency division signal generation section. 11-1 to 11-12. The superimposed frequency divided data Q2 to Q7 sent to lines 13-1 to 13-12 for each note name correspond to all musical tone generation sequences 5, respectively.
3-1 to 53-n.

The note selection circuit 57 of the musical tone generation series 53-1 to 53-n selects the note name of the note assigned to the channel based on the note data N1 (N2...Nn) given from the sound generation assignment circuit 56. The corresponding line (13-
1 to 13-12) superimposed frequency division data Q2~
Select Q7. The superimposed frequency-divided data Q2 to Q7 regarding the single note name selected by the note select circuit 57 of each generation series 53-1 to 53-n are sent to the superimposed frequency-divided signal receiving sections 12-1 to 12-n, respectively. is input. For example, when the note C is assigned to the first channel, the note data N1 represents the note C, and the note select circuit 57 selects the superimposed frequency divided data Q2 to Q of the line 13-1 corresponding to the note C, is selected and applied to the superimposed frequency-divided signal receiving section 12-1 via line 13A. The superimposed frequency-divided signal receiving sections 12-1 to 12-n have the same configuration as the superimposed frequency-divided signal receiving section 12 shown in FIG.

As already explained, the superimposed frequency-divided signal receiving sections 12-1 to 12-n separately take out the individual frequency-divided data Q2-Q7 from the superimposed frequency-divided data Q2-Q7 and latch them.
Therefore, corresponding to the frequency division data Q2 to Q7 of a single note name selected by the note select circuit 57, six square wave sound source frequency signals having the same note name in an octave relationship are superimposed and generated in the frequency division signal generating section 12. -1 (through 12-n) in parallel. For example, if the C note is assigned to the first channel, the 8-foot system C3, C4, C5'C
A square wave signal having a frequency of 67C7'C8 tone is generated from the superimposed frequency division signal receiving section 12-1 in correspondence with each frequency division data Q7, Q6, Q5, Q4, Q3, Q2. The tone name frequency signals of each octave output from the superimposed frequency divided signal receiving sections 12-1 to 12-n are each musical tone generation series 53-1 to 53-5.
The signals are respectively input to the switching circuits 58 in 3-n.

The opening/closing circuit 58 selects the pitch name frequency signal of each octave by imparting amplitude envelope characteristics such as attack/decay based on the key-on data Kl, K2, . The amplitude envelope characteristics of attack, decay, etc. are from key-on data K1 to
It can be provided using a time constant circuit consisting of a capacitor/resistor that controls charging and discharging depending on the presence or absence of Kn. The pitch name frequency signals of each of the six octaves to which envelopes have been added are input to the octave select circuit 59, and the pitch name frequency signals of the octave range represented by the octave data o1 (02 to 0n) are selected for each foot system. be done.

In this example, 2 feet (2'), 4 feet (4●,
Musical tones can be generated in each of the four foot systems of 8 feet (8') and 16 feet (161). For example, octave data 01 is the first
The first octave range is the 8-foot range C3, D3, D3...A.
3. Assuming that the 12 tones of B3C4 are included, the octave select circuit 59 of the first channel to which the C note is assigned.
Now, let's take a signal with the frequency of the 8-foot C4 tone (data Q
6) as the 8-foot musical tone signal, and
Select the frequency signal of the C3 tone of the foot system (corresponding to data Q7) as the 16-foot musical tone signal, and select the signal of the frequency of the C5 tone and C6 tone of the 8-foot system (corresponding to data Q5 and Q4) as the 4-foot musical tone signal. This is selected as the musical tone signal of the system and 2-fi system. Therefore, in terms of a certain foot system, among a plurality of frequency signals having the same pitch name and having an octave relationship with each other, which are supplied in parallel via the opening/closing circuit 58, the octave represented by octave data 01 A single frequency signal falling within the tone range is selected, and this single frequency signal is generated from the musical tone generation series 53-1 as the sound source signal of the tone (key) assigned to the channel. The sound source signals generated from each musical sound generation series 53-1 to 53-n are mixed for each foot system and supplied to a filter circuit (not shown) for tone color control.

FIG. 7 shows an example of the note select circuit 57.
The note data N1 is provided as a 4-bit code signal in a time division manner, for example, and after this code signal is decoded by a decoder 60, it is latched by a latch circuit 61.

Among the outputs of the latch circuit 61, only a single output corresponding to the note name represented by the note data N1 is "1". Twelve AND circuits 62 are provided corresponding to each note name.
The output of latch circuit 61 enables a single AND circuit 62. Superimposed frequency division data supply lines 13-1 to 13-12 corresponding to each note name are individually input to each AND circuit 62, and data corresponding to a single note name is inputted via the single AND circuit 62. Line (13-1 to 13-12
) is selected. The output of each AND circuit 62 is led to line 13A via OR circuit 63, and is applied to superimposed frequency-divided signal receiving section 12-1. FIG. 8 shows an example of the opening/closing circuit 58 and the octave select circuit 59. Key-on data K, which is applied in a time-division manner, is latched by a latch circuit 63 and converted into a direct current.

When the key-on data K1 becomes blank due to a key depression, the field effect transistor 64 is turned on and the capacitor 65 is charged. When the key-on value K1 becomes 1' due to the key being released, the field effect transistor 64 is turned off and the charge in the capacitor 65 is discharged through the resistor 66. Thus, on line 67 there appears an envelope waveform voltage characterizing the attack, sustain and decay of the tone amplitude. When the square wave frequency division signal corresponding to each frequency division data Q2 to Q7 outputted from the superimposed frequency division signal receiving section 12-1 is at the level "O", the field effect transistors 68-1, 68-2, .
... to select the ground voltage, and when the level is "1", turn on the field effect transistors 69-1, 69-2, etc. to select the envelope waveform voltage of the line 67. Therefore, each minute The level of the frequency signal is scaled by the envelope waveform voltage on line 67 and output to octave select circuit 59.Octave data 0 is, for example, a 2-bit code signal, which is decoded for each octave range by decoder 70. It is held by the latch circuit 71. Each octave selection line 72-1 to 72
Field effect transistors 73, 74, 75, . . . are provided so that a frequency-divided signal in the octave range can be selected for each foot system based on the -4 signal. For example, the field effect transistors 73 and 74 are turned on by the signal "1" on the first octave selection line 72-1, and the frequency division signal corresponding to the frequency division data Q7 is output in the first octave range of 16 feet (16●). The frequency-divided signal corresponding to the frequency-divided data Q6 is selected as a signal in the first octave range of 8 foot system (8●).As explained above, according to the present invention, a plurality of frequency signals Since multiple frequency signals can be sent out in a superimposed manner, the number of wiring can be saved in cases where a large number of frequency signals must be generated (for example, in a tone generator for an electronic musical instrument).

Furthermore, when a plurality of frequency-divided data are superimposed and generated according to the present invention, the timing of change in the value of "1゛, ゛0゜゜ of each frequency-divided data is synchronized. Even when musical tone signals are generated in a plurality of sounding channels based on the frequency division data of the same note name, the phases of the valley musical tone signals are always the same and never out of phase. If used in the tone generator of an electronic musical instrument, there is no need to provide a special phase matching circuit in case the same note name is assigned to multiple channels.
There is an effect. In addition, a timing signal is placed just before the superimposed frequency signal data (divided data), and the receiving section determines the location of the frequency signal data based on this timing signal. The circuit configuration when extracting a signal from a superimposed signal can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining how to illustrate various circuit elements, and FIG. 3 is a diagram for explaining the operation of the superimposed frequency division signal generator shown in FIG. 1. 4 is a timing chart showing how the superimposed frequency division data is generated from the superimposed frequency division signal generation section of FIG. 1, and FIG. 5 is a timing chart showing how the superimposed frequency division signal receiving section of FIG. 1 is generated. A timing chart for explaining the operation, FIG. 6 is a plotter diagram showing an example of the application of the present invention to a tone generator of an electronic musical instrument, FIG. 7 is a circuit diagram showing an example of the note select circuit of FIG. 6, FIG. 8 is a schematic circuit diagram showing an example of the opening/closing circuit and octave select circuit of FIG. 6. 10... Frequency signal generator, 11, 11-1
to 11-12...superimposed frequency division signal generation section, 12
, 12-1 to 12-n...superimposed frequency division signal receiving section, 14...digital oscillation section, 15...
- Frequency division data creation section, 16...shift register, 57...note select circuit, 58...
...Opening/closing circuit, 59...Octave select circuit.

Claims (1)

[Claims] 1. Every time the logic level of the highest frequency signal among a plurality of frequency signals each consisting of binary logic levels is inverted, at least data corresponding to each logic level of the other frequency signals at that time. a first means for sequentially and serially generating a plurality of frequency signals corresponding to each data of the data string by parallelizing and storing a data string serially applied from the first means; and second means for separately extracting the frequency signal. 2. The second means is a circuit that parallelizes the data string given serially from the first means and stores it, and rewrites the memory every time a new data string is given from the first means. A frequency signal generating device according to claim 1, comprising: 3. The first means includes an oscillation unit that generates a pulse with a period corresponding to the highest frequency, and a frequency-dividing unit for sequentially frequency-dividing the pulse, and logic level data for each frequency-divided signal obtained by the frequency division. each time the pulse is generated, the circuit assigns the pulse to a different type slot and sequentially transmits it in series, and the second means includes a shift register that parallelizes the logic level data string applied serially. , and a latch circuit for storing the parallel output data of the shift register. 4. The first means generates a predetermined timing signal in advance of the data string, and the second means performs the rewriting operation based on the timing signal. 2. The frequency signal generator according to item 2. 5. Every time the logic level of the highest frequency signal among a plurality of frequency signals each consisting of binary logic levels is inverted, data corresponding to at least the respective logic levels of the other frequency signals at that time is generated in series. a first means for outputting a signal for selecting and specifying one of the plurality of frequency signals; and a first means for outputting a signal for selecting and specifying one of the plurality of frequency signals; and third means for selecting predetermined data according to a signal output from the apparatus and generating a frequency signal corresponding to the selected data.