JPS5934722A - Duty controller - Google Patents

Duty controller

Info

Publication number
JPS5934722A
JPS5934722A JP57145763A JP14576382A JPS5934722A JP S5934722 A JPS5934722 A JP S5934722A JP 57145763 A JP57145763 A JP 57145763A JP 14576382 A JP14576382 A JP 14576382A JP S5934722 A JPS5934722 A JP S5934722A
Authority
JP
Japan
Prior art keywords
pulse
generator
output
timer
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57145763A
Other languages
Japanese (ja)
Other versions
JPH0369213B2 (en
Inventor
Katsunori Zaizen
克徳 財前
Junichi Nakakuki
準一 中久木
Katsuaki Suzuki
克彰 鈴木
Sadatoshi Tabuchi
貞敏 田縁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57145763A priority Critical patent/JPS5934722A/en
Publication of JPS5934722A publication Critical patent/JPS5934722A/en
Publication of JPH0369213B2 publication Critical patent/JPH0369213B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses

Landscapes

  • Control Of Resistance Heating (AREA)
  • Control Of Temperature (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To increase the service life of a load controller and to suppress the flicker, by switching the duty ratio of a duty controller only with the fall timing of a pulse generated from a pulse generator. CONSTITUTION:An AC power supply AC is applied to a pulse generator 2 after the half-wave rectification carried out by a half-wave rectifying circuit 1. A capacitor C2 of the generator 2 repeats charging and discharging with the upper/ lower limit voltage decided by resistances R4, R5 and R7. Thus a pulse VT is generated. A flip-flop IC4 of a switch 6 supplies a waveform obtained by differentiating the pulse VT to a clock input T and therefore fetches the output VD of a signal generator 4 only in the fall of the pulse VT to deliver it to an output Q. As a result, the output VO of a timer 3 is turned on and off in a prescribed working time in spite of the variation of the output of the generator 4. Then a load l is turned on and off by a relay of a load controller 5. Thus the ON/OFF frequencies are reduced to increase the lifetime of the controller 5, and at the same time the flicker is suppressed.

Description

【発明の詳細な説明】 産業上の利用分野 ノーティ切換時のチャタリング除去に関するものである
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the removal of chattering during switchover in the industrial field of application.

従来例の構成とその問題点 従来例のデー−ティ制御装置では第1図に示すように交
流電源ACに接続さ才した半波整流回路1と、コンデン
サC2、抵抗R3、電圧比較器IC1とからなるパルス
発生器2と、コンデンサC3、抵抗R8、IM、用比較
器’C2とからなるタイマー3と、タイマー3の動作時
間を、温度検出素””’15の値に従って切換る切換器
4と、タイマー3の出力で負荷aをオン、オフする負イ
:・“I制御器5とて構成され、パルス発生器2の発生
するパルスの周期と、タイマー3の動作時間とて決する
デ・−ティ比で負荷制御器5をON、OFFする1、し
かし、第2図に示すように、温度検出素子R15と抵抗
R11の分割電圧Vsが図に示すような変化をした場合
、電圧比較器IC3の出力電圧VDは、その変化に追従
し、オン、オフの動作が反復される。タイマー3の動作
時間の切換点近くで、前記オンオフの反復動作が行なわ
れた場合、タイマー3の出力、すなわち負荷制御器6が
オンオフの反復動作をするため負荷制御器6がリレー等
の機椋的接点を有する場合は、その接点寿命が著しく減
少する。父、負荷制御器5がトライアック等の半導体ス
イソナング素子の場合は、フリッカ雑音の発生等の問題
が生じる。
Configuration of the conventional example and its problems As shown in Fig. 1, the conventional data control device includes a half-wave rectifier circuit 1 connected to an AC power supply, a capacitor C2, a resistor R3, a voltage comparator IC1, and the like. a timer 3 consisting of a capacitor C3, a resistor R8, an IM comparator C2, and a switch 4 that switches the operating time of the timer 3 according to the value of the temperature detection element 15. and a negative i that turns on and off the load a with the output of the timer 3: - A negative a that is configured as an I controller 5 and determines the cycle of the pulses generated by the pulse generator 2 and the operating time of the timer 3. 1. However, as shown in FIG. 2, if the divided voltage Vs of the temperature detection element R15 and the resistor R11 changes as shown in the figure, the voltage comparator The output voltage VD of IC3 follows the change, and the on/off operation is repeated.When the on/off operation is repeated near the switching point of the operation time of the timer 3, the output of the timer 3, In other words, since the load controller 6 repeats on-off operations, if the load controller 6 has a mechanical contact such as a relay, the life of the contact will be significantly reduced. In the case of an element, problems such as generation of flicker noise occur.

発明の目的 本発明は、負荷のデコーティ制御を行う装置のデー、−
ティ切換時に発生する装置の短い周期でのオンオフの反
復動作を除去することを目的とする、発明の構成 本発明は一定周期のパルスを発生するパルス発生器と、
このパルス発生器の発生するパルスに同期し、かつこの
パルスの周期以下の所定の時間動作するタイマーと、こ
のタイマーの動作時間を前記パルスに同期したタイミン
グでのみ切換る切換器と、この切換器に前記パルス発生
器の発生するパルスと非同期に切換指示の信号を出力す
る信号発生器と、前記タイマーの出力で負荷を駆動する
負荷制御器とで構成したものである。
OBJECTS OF THE INVENTION The present invention provides data for a device that performs load decoupling control.
The present invention provides a pulse generator that generates pulses with a constant cycle, and a pulse generator that generates pulses with a constant cycle;
a timer that operates in synchronization with the pulses generated by the pulse generator and for a predetermined period of time equal to or less than the cycle of the pulses; a switch that switches the operating time of the timer only at a timing synchronized with the pulse; and the switch A signal generator that outputs a switching instruction signal asynchronously with the pulses generated by the pulse generator, and a load controller that drives the load with the output of the timer.

実施例の説明 以下、添付図面に基づいて本発明の一実施例について説
明する。
DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings.

第3図は、本発明の構成を示すブロック図で、一定周期
のパルスを発生ずるパルス発生器2と、このパルス発生
器2の発生ずるパルスに同期し、かつこのパルスの周期
以下の所定の時間動作するタイマー3と、このタイマー
3の動作時間を前記パルスに同期したタイミングてのみ
uJ換る切換2に6と、この切換器に前記パルス発生?
!32の発生ずるパルスと非同期に切換指示の信号を出
力するi+”r ”J発生器4とで構成し、前記パルス
発生器10発生するパルスの周期と前記タイマー3の動
作時間とで決まるデユーティ比に従って負荷制御器5を
オンオフする。
FIG. 3 is a block diagram showing the configuration of the present invention, which includes a pulse generator 2 that generates pulses with a constant period, and a predetermined pulse that is synchronized with the pulses generated by the pulse generator 2 and whose period is equal to or less than the period of this pulse. A timer 3 that operates for a time, a switch 2 to 6 that switches the operating time of the timer 3 to UJ only at a timing synchronized with the pulse, and a switch 6 that generates the pulse?
! and an i+"r"J generator 4 which outputs a switching instruction signal asynchronously with the pulses generated by the pulse generator 10, and has a duty ratio determined by the period of the pulses generated by the pulse generator 10 and the operating time of the timer 3. The load controller 5 is turned on and off accordingly.

第4図はその回路図で、1は交流電諒ACに接続され、
以下の各ブロックに直流電圧を供給する半波整流回路、
2は抵抗R3とコンデンサC2の嘴数回路と電圧比較器
IC1によるノーミツト回路からなるパルス発生器、3
は抵抗R9とコンデンサC3の時定数回路と電圧比較器
IC2からなるタイマー、6は抵抗R16と抵抗R1□
とコンデンサC4とからなる微分回路とD形フリノフリ
ロッグ’C4とで構成した切換器、4は温度検出素子R
12と電圧比較器’C3とからなる信号発生器5は負荷
aをオンオフする負荷制御器である。
Figure 4 is its circuit diagram, where 1 is connected to an AC power source,
A half-wave rectifier circuit that supplies DC voltage to each block below,
2 is a pulse generator consisting of a beak number circuit including a resistor R3 and a capacitor C2, and a norm circuit including a voltage comparator IC1;
is a timer consisting of a time constant circuit of resistor R9 and capacitor C3, and voltage comparator IC2, and 6 is a timer consisting of resistor R16 and resistor R1□
4 is a temperature detection element R.
12 and a voltage comparator 'C3, the signal generator 5 is a load controller that turns on and off the load a.

以下上記構成における動作を説明する。交流電源へCが
接続されると、半波整流回路1より直流電圧が供給され
、コンデンサC2は、抵抗R4と抵抗Hによる分割電圧
まで抵抗R3を介して充電される動作と、抵抗Rと抵抗
R7の並列回路と抵抗R4による分割電圧捷で抵抗R7
及びダイオードD4を介して放電する動作を交互に繰り
返す。従って電圧比較器IC1は、第5図に示すように
パルスvTを発生する。コンデンサC2は、このパルス
vTがローの時はダイオードD5を介して放電され、・
々ルス■Tが・・イの時は抵抗R1゜と抵抗R11によ
る分割電圧もしくは、抵抗R11と抵抗R18の並列回
路と抵抗R9による分割電圧捷で抵抗R9を介して充電
されるため、第6図に示ずように、電圧比較器’C2の
出力■oはパルスvTに同期しかっこのパルスvTの周
期TO以下の所定の動作時間T1及びT2 を持ってい
る。負荷制御器5はこのパルスの周期T。とタイマーの
動作時間T1  もしくはT2によって決するデー−テ
ィ比で負荷のオンメツを行′)。
The operation of the above configuration will be explained below. When C is connected to an AC power supply, a DC voltage is supplied from the half-wave rectifier circuit 1, and the capacitor C2 is charged via the resistor R3 to the voltage divided by the resistor R4 and the resistor H, and the resistor R and the resistor Resistor R7 is divided by parallel circuit of R7 and resistor R4.
and discharging via the diode D4 are alternately repeated. Voltage comparator IC1 therefore generates a pulse vT as shown in FIG. When this pulse vT is low, capacitor C2 is discharged via diode D5,
When T is...A, the sixth voltage is charged via resistor R9 by the voltage divided by resistor R1° and resistor R11, or by the divided voltage by the parallel circuit of resistor R11 and resistor R18 and resistor R9. As shown in the figure, the output ``o'' of the voltage comparator 'C2 has predetermined operating times T1 and T2 that are synchronized with the pulse vT and shorter than the period TO of the parenthesized pulse vT. The load controller 5 determines the period T of this pulse. The load is applied at a duty ratio determined by the operating time T1 or T2 of the timer.

このタイマーの動作時間T1 及びT2の切換は、D形
フリップフロップ■c4 の出力Qで行なわ7する。一
方、このD形フリノダンロップ’C4のクロック人力T
Kは、前記パルスvTを抵抗R16と抵抗R1□とコン
デンサC4とからなる微分II−J路で微分した波形が
印加されているので、パルスVTの立下り時のみ信号発
生器4の出刃VDを取り込んで出力Qに出力する。した
がって、信づ発生器4の出力VDが、第6図に示すよう
に化1ト比較H:<IC3の入力端子すに印加される重
重二イτ]近で、入力端子aに印加される電圧vAが変
動する/こめにオンオフの動作をある期間短い周期で反
復しても、タイマー3の出力■○は、所定の動作時間T
1  もしくはT2にしたがってオンオフを行い、前記
パルス■Tの立下り時以外での信号発生器4の出力電圧
VDのオンオフ動作の反復は除去されるという効果があ
る。
Switching between the operating times T1 and T2 of this timer is performed by the output Q of the D-type flip-flop c4. On the other hand, this D type Furino Dunlop 'C4 clock manual T
K is applied with a waveform obtained by differentiating the pulse vT by a differential II-J path consisting of a resistor R16, a resistor R1□, and a capacitor C4. It is taken in and output to output Q. Therefore, as shown in FIG. Even if the voltage vA fluctuates/the on/off operation is repeated in short cycles for a certain period of time, the output of the timer 3
1 or T2, and the repetition of the on/off operation of the output voltage VD of the signal generator 4 at times other than the falling edge of the pulse T is eliminated.

なお、上記実施例では、負荷制御器6をリレーとしその
接点寿命を縮める設定値付近でのオンオフ動作の反復を
なくした例を7ドし/(か、トライアック等の半導体素
子ても、前記反復動作時に発生するフリッカの問題を解
消できる、 発明の効果 以−に説明したように本発明のデー−ティ制御装置は、
デー−ティ比の切換を、特定のタイミングてのみ切換る
ようにしたことにより、負荷制御器の寿命の向上や、フ
リッカの抑制をはかることができるものである。
In the above embodiment, the load controller 6 is used as a relay to eliminate the repetition of on/off operations near the set value that shortens the life of its contacts. Advantages of the Invention As explained above, the data control device of the present invention can solve the problem of flickering that occurs during operation.
By switching the duty ratio only at specific timings, the life of the load controller can be extended and flicker can be suppressed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例を示す回路図、第2図は従来例の動作を
示す動作図、第3図は本発明の構成を示すブロック図、
第4図は本発明の一実施例を示す回路図、第5図は実施
例の動作を示す動作図である。 2・・・・・・パルス発生器、3・・・・・・タイマー
、4・・・・・・信号発生器、5・・・・・負荷制御器
、6・・・・切換器。
FIG. 1 is a circuit diagram showing the conventional example, FIG. 2 is an operation diagram showing the operation of the conventional example, and FIG. 3 is a block diagram showing the configuration of the present invention.
FIG. 4 is a circuit diagram showing an embodiment of the present invention, and FIG. 5 is an operation diagram showing the operation of the embodiment. 2...Pulse generator, 3...Timer, 4...Signal generator, 5...Load controller, 6...Switcher.

Claims (1)

【特許請求の範囲】[Claims] 一定周期のパルスを発生ずるパルス発生器と、このパル
ス発生器の発生するパルスに同期し、かつこのパルスの
周期以下の所定の時間動作するタイマーと、このタイマ
ーの動作時間を前記パルスに同期したタイミングでのみ
切換る切換器と、この切換器に前記パルス発生器の発生
ずるパルスと非同期に切換指示の信号を出力する信号発
生器と、前記タイマーの出力で負荷を駆動する負荷制御
器とで構成したデー−ティ制御装置。
A pulse generator that generates pulses of a constant period, a timer that is synchronized with the pulses generated by this pulse generator and operates for a predetermined time shorter than the period of this pulse, and an operating time of this timer that is synchronized with the pulse. A switch that switches only at the timing, a signal generator that outputs a switching instruction signal to the switch asynchronously with the pulses generated by the pulse generator, and a load controller that drives the load with the output of the timer. Configured data control device.
JP57145763A 1982-08-23 1982-08-23 Duty controller Granted JPS5934722A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57145763A JPS5934722A (en) 1982-08-23 1982-08-23 Duty controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57145763A JPS5934722A (en) 1982-08-23 1982-08-23 Duty controller

Publications (2)

Publication Number Publication Date
JPS5934722A true JPS5934722A (en) 1984-02-25
JPH0369213B2 JPH0369213B2 (en) 1991-10-31

Family

ID=15392592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57145763A Granted JPS5934722A (en) 1982-08-23 1982-08-23 Duty controller

Country Status (1)

Country Link
JP (1) JPS5934722A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63316112A (en) * 1987-06-18 1988-12-23 Aichi Electric Co Ltd Hot water temperature controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49133529U (en) * 1973-03-19 1974-11-16
JPS54111024A (en) * 1978-01-27 1979-08-31 Bosch Gmbh Robert Apparatus for controlling impact coefficient of frequencyyvariable signal row

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49133529U (en) * 1973-03-19 1974-11-16
JPS54111024A (en) * 1978-01-27 1979-08-31 Bosch Gmbh Robert Apparatus for controlling impact coefficient of frequencyyvariable signal row

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63316112A (en) * 1987-06-18 1988-12-23 Aichi Electric Co Ltd Hot water temperature controller

Also Published As

Publication number Publication date
JPH0369213B2 (en) 1991-10-31

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