JPS5931049B2 - Camera information setting display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for setting and displaying photographing information such as shutter speed and aperture value in a camera, etc., and in particular, a method for setting and changing information electrically by operating a push button switch or the like. This invention relates to a method for displaying shooting information settings.

In a camera equipped with an exposure control circuit, conventionally, in order to set photographing information in the variable elements of the circuit, the variable elements linked to these are manually operated, for example, on a mechanical information setting mechanism such as a shutter dial, aperture ring, etc. I was changing positions.

Therefore, when taking pictures, it is necessary to separately operate the information setting mechanisms as described above provided on the camera body or the lens, which is inconvenient when taking pictures quickly. The present invention enables the above-mentioned photographic information such as shutter speed and aperture value to be freely set by operating a push button located at an appropriate location on the camera, without using mechanical setting means such as a shutter dial or aperture ring. The present invention provides a photographing information setting display method that allows selective settings and display, and allows the direction of information change and change mode to be arbitrarily selected by selecting the switch operation stroke.
And to provide a photographing information setting display method for a camera in which the setting information is appropriately displayed digitally inside the viewfinder and outside the viewfinder, and desired photographing information can be quickly set with a simple operation while monitoring this. It is.

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 is a block circuit diagram showing an embodiment of the electronic photographing information setting and display method according to the present invention. The figure is a block diagram of a device for setting and displaying photographic information in a camera, and each input and output terminal in the figure indicates a transmission terminal for input and output signals from each part of the digitally controlled camera. In the figure, the symbol "c" attached to each terminal indicates one pole of the camera's power supply, and the other poles are connected to the part indicated by the earth symbol. Reference numeral 1a is an input terminal of a circuit for switching the direction in which the set value is increased or decreased, and when the switch Swl is on, a logic "1" is sent to the transmission path 9, and when it is off, a logic "1" is sent out.

With this input from 9, up/down counter 2 becomes 1
When the count is ``, the step count is in the up direction, and when the count is ``O'', the step count is in the down direction.The terminal 1b is a terminal for controlling the clock pulse of the count, and when the switch Sw2 is turned on, the ``O'' signal is sent to the transmission path 17. , a "1" signal is sent out when the clock pulse generator 7 is off.The clock pulse is generated by the clock pulse generator 7, and the setting values and other changes are made in steps at the cycle. The clock input control signal from b is applied to the CP input of the up/down counter 2 via the line 17 and counted in steps according to the up/down direction instruction from the line 9. It is also transmitted to the display control device 5.The terminal 1c constitutes the power supply circuit of the up/down counter 2, and due to the self-holding action of the timer 8 inserted therein,
Even if the power of the device is turned off, the power supply to the counter 2 is maintained for a certain period of time. 3 is the central control unit (
The brightness information from the photometry device including the light receiving element, the priority command signal from the terminal 1d, and the output signal 15 of the counter 2 are inputted to the CPU), and the outputs include control signals to the shutter control section, the aperture control section, and the illustrated Various signals such as the above are sent to the display control device 5.

The switch Sw3 of the d circuit is a priority mode changeover switch. When Sw3 is on, the camera operates in shutter priority mode, and when it is off, the camera operates in aperture priority mode. Of the signals sent from the CPU 3 to the display control device 5, the shutter single digit signal and the aperture digit signal passing through the lines 10 and 11 are transmitted via a gate controlled by a signal from the terminal 1e, and are turned on and off by turning Sw4 on and off. The display stops or blinks. Note that a warning signal "1" for displaying various warnings such as a warning when the calculated value exceeds the controllable exposure information value range of the camera is sent directly to the display control device 5 via the line 12.
Display segment signals are sent directly from the CPU to the display device 6. The output 15 of the up-down counter 2 is input to the CPU and also to the counter control circuit 4.
The circuit 4 is also applied with the clock control signal 17 to the clock input control device 1 and outputs a counter control signal to its output, which is sent to the parallel presetable input terminal of the up-down counter 12. Also output 1 of 4
The signal 6 is also sent to the clock input control device 1 and the display control device 5 to turn on/off their control operations. The display control device 5 receives clock pulses from a clock pulse generator 7 and a signal 16 from the counter control device 4 as shown.
In addition, signals from the line 17 are inputted, and control actions for various displays are performed according to various commands 10, 11, and 14 from the CPU, and outputs a shutter one-second signal 18 and an aperture signal 19. . These display signals are input to the display device 6, and various information displays are displayed, for example, in a viewfinder, etc., according to display segment commands from the CPU. The display device is constituted by a combination of a known segment and digit driver, a 7-segment LED, and other display elements. The configuration and operation of the electronic photographing information setting and display device according to the present invention have been explained above with reference to FIG. 1, and FIG. This will be explained in detail below.

In the following drawings, the same parts as in FIG. 1 are designated by the same reference numerals. FIG. 2 is a circuit diagram showing an embodiment of the clock input control device 1 in FIG. 1, and FIG. 3 is a curve diagram showing an example of a timing chart of the device shown in FIG. In the figure, the pulses from the clock pulse generator 7 have a waveform as shown in FIG. 3A. 23 is a frequency divider constituted by a circuit such as a flip-flop, and a signal having a waveform as shown in FIG. 3 is obtained at its output.

All clocks are synchronized at the falling edge of the pulse, and the output Q4 of the counter 21 is ANDed via the inverter 27.
Since it is returned to gate 24, gate 21 outputs Q4 and at the same time inhibits clock input. FIG. 3C shows the input of the tarlock input control device 1, and when the switch Sw2 is off, it is "1", and when it is on, it is "01". This signal is also input to the counter 21 reset input, the 0R gate 25, and the AN
C of up/down counter 2 via D gate 26
This becomes P input. The output of the counter 21Q4 becomes an input to the AND gate 22, is ANDed with the frequency-divided output of the clock, and is inputted to the CP of the up-down counter 2 via 0R25 and AND26, thereby changing the count of the up-down counter 2 by one step. A control signal from a counter control device shown at 4 in FIG. 1 is input as a second input to the AND 26, and the clock to the counter 2 is controlled to be turned on or off. Figure 3 shows a case where the off time of the clock input control switch Sw2 is long, and in this case, when the Q4 output of the counter 21 reaches ``1'' (towards the figure), the up-down counter is immediately turned on as shown in Figure 3. 12
counting starts. This shortens the time between each step after the second step when the set value is continuously manipulated. Figure 4 shows the counter control device 4 in Figure 1.
FIG. 2 is a circuit configuration diagram showing an example of the present invention.

In the figure, the outputs C1 to C of uptown counter 2 are
5 is input to the CPU 3 via the line 15 and is also sent to the 0R gates 28, 29 of the counter control device. 0R
The outputs of the gates 28 and 29 are input to the 0R gates 30 and 31 together with the up/down direction switching signal from the line 9.
The outputs of R gates 30 and 31 are ANDed by AND gate 33.
The output signal is output to the line 16 as a counter control output via 34 0R gates.

Note that a clock input control signal (C or H in FIG. 3) is input from the line 17 to the 0R34. Assuming that the output of the up-down counter 2 has now reached "00000", that is, the upper limit of the setting range, and the direction command from the track 9 does not indicate down and is O゛, then the output of 0R28 is O-0.
The output of R29 becomes 1°. At this time 0R30 and 3
The signal input to 1 is O゛ if it is 30, and 1 if it is O-31.
′゛、. 1゛, and the output of 0R30 becomes ``0゛, 0.
The output of R31 is 1", so the output of AND33 is 0"
When the signal from the line 17 becomes ``O'', the counter control output 16 becomes 10'', which is sent to the clock input control device 1, and the clock input to the up-down counter 12 is stopped. .

Further, when the output of the counter 2 reaches "1, 0, 0, 0, 1", that is, the lower limit of the setting range, and the command from the line 9 is 81° indicating up, then the output of the 0R gate 28 is 1,0,0,0,1. The output of ``29'' becomes 10'', and the counter control output 16 becomes ``0'' and the clock is stopped in the same way as in the above case. In all other cases, the counter control output is 1, and the clock changes stepwise in response to an UP or DOWN command from the line 9.

Table 1 shows the correspondence between the output of the up-down counter 12 and the control output of shutter priority or aperture priority in the CPU. Obtains the one-second shutter speed or step change in aperture value required for shooting. FIG. 5 is a circuit diagram showing an embodiment of the display control device 5 in FIG. 1.

As shown in the figure, the device is composed of AND, OR, NAND gates and inverters; a clock pulse generator 7 outputs a clock pulse, a line 16 outputs a counter control output, a line 17 outputs a clock input control signal, a line 10,
11, 12 and 14 input command signals from the CPU for shutter single digit, aperture digit, warning and priority setting, respectively, to device 5, and the output from 5 is sent to lines 18 and 19.
The signal is transmitted to the display device to display the shutter time, aperture value, etc. To explain an example of the operation of the device shown in the figure, when the counter output input to the CPU 3 in FIG. 1 is within the appropriate exposure setting range, the input from 16 is 61°,
Further, the warning input 12 from the CPU becomes "0".

If we now consider the case where the priority setting is set to shutter-first priority mode, the line 14 becomes "1", and with these inputs, the outputs of AND gates 30 and 31 both become "0", and the AND
The output of the gate 34 is 10'', and since the line 16 is 1'', the output of the NAND gate 33 is 1''. In addition, the output of the NAND gate 32 becomes "1", and the inputs of the AND gate 36 are all 11" except for the shutter one-digit signal 10. Therefore, the CPU's shutter one-digit signal 10 is output to the output 18 of the AND gate 35, which is displayed on the display device. 6, and the shutter time of one second is displayed. Similarly, in the case of aperture priority mode, use the AND gate 4 in the same manner as above.
6 input becomes 11゜ except for aperture digit signal 11, AN
The aperture digit signal 11 of the CPU is output to the output 19 of the D gate 45. Next, when the set value of up-down counter 2 reaches the limit value of the set range, 16 becomes 40゛,
Since the output of the OR circuit 50 changes to "0" and "1" with the output of the clock generator 7, that is, the clock cycle, the signals of the outputs 18 and 19 of the display control device also change to "0" and "1" accordingly.
1'' is repeated periodically, so the display on the display device 6 repeatedly blinks.

As described above, when the combinations of the signals of the input lines 17, 12, 16, and 14 in the display control device shown in FIG. is controlled in various ways and produced at output 18 or 19.
The display on the display device 6 changes in various ways depending on these outputs.

Table 2 shows changes in the display corresponding to various logic inputs to the display control device as described above. In the figure, the numbers in the columns of outputs 18 and 19 correspond to one digit of the shutter.
0, the aperture digit is indicated by 11, and the number with a circle around it lights up continuously,? } indicates blinking. Note that "0" indicates off. Next, a few examples of the various operations of the display control device shown in FIG. 5 shown in Table 2 will be explained.

Logic "0011" shown in the second and third rows of Table 2
"0010" indicates the control of information display during the setting of priority setting information, and "0011" indicates the case where both the set value and the calculation result during the setting of priority setting information are within the control range. In this case, each input signal in FIG.
14 becomes "1".The output of NAND33 is 41", N
AND32 is “1” if clock 7 is outputting “1”.
Since the output of 0R50 is also "1", all other inputs of AND36 except shutter single digit signal 10 are "1", and signal 10 passes through 36.AND35
Since the input also becomes ゛1゛゛1゛゜, the signal 10 is sent to the output 18 of the device. Next, NAND43 outputs "0", and NAND42 outputs "1".
ND46 passes the aperture digit signal, but since AND45 is turned off, signal 11 does not appear on output 19. Therefore, in this case, only the shutter single digit signal 10 (set value) from 18 is displayed, and the aperture digit signal 11, which is the calculation result, is not displayed. Next, the setting of the priority setting information is stopped, and if both the set value and the calculated value at this time are within the control range, the logic "1" shown in the first row of Table 2 is
01×”.

× can be set arbitrarily, so if the information is set with priority given to the shutter, the logic will be “1011”,
In this case, both NAND33 and NAND43 are 1
Even if the input from clock 7 is also 0, both NAND32 and NAND42 output 61. Therefore AND36, 35 and AND46
, 45 are all on, and the shutter single digit signal 10 (setting value) and aperture digit signal 11 (calculated value) are sent from the CPU.
will be sent together at outputs 18 and 19 to the display device, and these two pieces of information will be displayed. Next, consider the logic “000U” and “000U” in the fourth and fifth rows of Table 2.
000'' is a case where the set value exceeds the control range while setting the priority information, and in this case, the 16 inputs of the logic in the second and third lines are equal to 0.

The shutter single digit signal 10 and the aperture digit signal 11 are both produced at outputs 18 and 19, and the input from clock 7 is "1".
The ANDs 36 and 46 will repeat on and off states depending on when the signal is 0'', and therefore the display by 16 and 19 will be a blinking display. That is, in this case, both the set value (limit value) and the calculated value are displayed blinking. Next, logic [0111'' and [0110'' in the 7th and 9th lines of Table 2 are cases where the calculated value due to arithmetic failure exceeds the limit value of the control range while setting the priority information. In this case, the warning signal 12 from the CPU becomes "1".

If the shutter is the priority now, if you select "0111", it will be NANl.
) 33 and 43 both output 61゛. Also NAND3
2 always outputs pi 1, but NAND42 outputs clock 7.
When the output is Yama 1 power, it is 0 - When the output is 0 Tsutsu, it is Dl
Output n. Therefore, the setting position (
The shutter single digit signal) always appears on output 18, but the AND
The calculated value (aperture digit signal) passing through 46 and 45 flashes at the cycle of clock 7. As described above, by providing the respective logics shown in Table 2 to the display control device of FIG. 5, the display of the display device can be varied in various ways as shown.

6a and 6b illustrate the configuration of a logic circuit for a specific operation among various operations in the display control device of FIG. This is a case where the set limit value and the calculated value are displayed, and FIG. b shows a case where when the set value reaches the limit value, this is displayed by blinking the indicator light. In FIG. 6a, the display control signal 16 that warns that the set value has reached the limit value becomes ``0'', so NAND33 and 4
3 both have an output of 11゛, and the soyota single digit input 10 and aperture digit input 11 from the CPU both have outputs 18 and 1.
9 and sent to the display device 6. That is, input 10,
Since one of 11 is a set value and the other is a calculated value, this circuit configuration outputs both the set limit value and the calculated value. FIG. 6b shows that when the set value reaches its limit value, 16 becomes 0, and 17 becomes 1 through the inverter 52, and the on/off signal from the clock signal generator 7 is sent to the 0R gate on these 16 lines. Since 14 is "F", that is, when the shutter has first priority, the output of AND35 turns on and off at the cycle of 7, and the set value from line 10 is displayed blinking, while the calculated value from line 11 is displayed. It is turned off by AND gate 4q.Next, FIG. 7 is a circuit diagram showing another embodiment of the counter control device in FIG.
A signal can be sent to the output 20 from 4 in the figure, that is, the parallel preset input enable terminal of the up/down counter 2.

In the figure, counter 2 is now "1, 0, 0, 0, 1"
Assuming that the set limit value of line 9 has been reached, line 9
If the up count command is ``1'', then in the next state it will be ``1''.
, 0, 0, 1, 0'' and the output of the NAND gate 62 is ``
0'', and the output of 0R64 also becomes ``O''. In addition, since the clock input control signal from the line 17 is "0", the output of the NOR66 becomes "1", which is the counter 2.
The signal is sent to the reset terminal, and all counters are reset. Contrary to the above, the counter is now “0,0,0
, 0, 0'', the down command 10'' is input from 9, the output of NOR65 becomes 1'', this is input to the parallel preset input enable terminal of counter 2, and counter 2 Preset input P1~
The value of P5 "1, 0, 0, 0, 1" is input.

FIG. 8 is a block circuit diagram showing another embodiment of the photographing information setting display method according to the present invention, in which the same parts as in FIG. 1 are indicated by the same symbols, and switches of each input circuit are omitted. .

The difference between the embodiment shown in FIG. 1 and FIG. 1 is that a warning signal 12 when the calculated value from the CPU 3 exceeds the control range is sent to the display control device 5 and the tarotsuta input control device 1 via an inverter 71 and an AND gate 72. This is what is being communicated. According to the circuit arrangement as shown in the figure, the warning 12 indicating that the calculated value is out of the control range can be considered to be completely equivalent to the signal 16 when the set value reaches the limit value range. In other words, when the calculated value is out of the control range, the warning output 12 of the CPU 3 is 1゛, which is input to the AND gate 72 ``O'' through the inverter 71, and the output of the AND 62 becomes ``O'', which is output to the display control device. 5
to display a warning. The operations of the other circuits have been explained in detail with reference to FIG. 1 and the detailed drawings in and after FIG. 2, and will therefore be omitted here. If the circuit shown in FIG. 6a is used as the display control device in FIG. 8, the priority set value and the calculated value will be displayed simultaneously, and the circuit shown in FIG. This can be done by blinking both. In this case, the clock input control signal 17 must always be kept at "1", and since the outputs of the NAND circuits 3σ and 4σ are 11", 16/ becomes 60". The signals 18 and 11 are outputted as blinking signals to 18 and 19, respectively. Next, FIG. 9 is a main part plotter circuit diagram showing another embodiment of the photographing information setting display method according to the present invention. In the embodiment, the subject brightness information is converted into digital information by an A-D converter, and this is input to the CPU 3 and simultaneously to the preset inputs P5 to P of the up/down counter 2. In this way, the device When the power is turned on, the digital information from the photometry circuit is immediately preset to counter 2.The monostable multipipe radar circuit shown in the figure operates only when the power is turned on, and the parallel preset input terminal of the counter Figure 10 is a main block circuit diagram according to another embodiment of the present invention, and in this circuit, the preset inputs P5 to P of the up/down counter 2 are set to "0, 0.
, 1, 0, 0''.

In other words, when the device is powered on in this circuit state, if the parallel preset input enable signal is input to counter 2, the counter will automatically change to the above logic value "0, 0, 1, 0, 0". will be preset. In other words, if the shutter has first priority, this preset value "0,0
, 1, 0, 0'' is 1/125 seconds, and in the case of aperture priority, it is Fll, so according to the circuit in Figure 10, when the device is powered on, the shutter speed or aperture value, which is frequently used, is on the counter. It can be preset to 2. FIG. 11 is also a main block circuit diagram showing another embodiment of the system according to the present invention, and in the circuit shown in the figure, the CPU 3
Outputs R5 to R1 are sent to the preset inputs P5 to P1 of the up/down counter 2, respectively, and a signal is also input from the priority switching signal circuit to the parallel preset input enable terminal of the counter 2 via the monostable circuit. .

When this circuit is used, the CPU calculates the value that is initially set to the counter 2 by manual operation, etc., and the calculated value is transferred to the CPU by switching the priority mode (by Sw3).
is sent from the calculation output terminals R5 to R, of the counter to the preset input terminals P5 to P1 of the counter, and the set value of the counter 2 is replaced with the calculation value from the CPU at the time of priority switching. In other words, if you use the camera in shutter priority mode and want to take the next shot in aperture priority mode using the aperture value obtained from information from the photometry circuit, etc., simply switch priority switch Sw3 using this circuit. By operating the aperture value, the previously obtained aperture value is automatically set on the counter, making it possible to quickly switch the priority mode. Next, FIG. 12 is a block circuit diagram showing an application example of the method according to the present invention, and is an example in which a nonvolatile memory is used as the counter memory of the device.

As a non-volatile memory, the recently developed MNOS (
(semiconductor elements based on metal nitrides and oxides). In the figure, it is a non-volatile generation counter memory constructed using a ZC-OS, and a clock signal to this is inputted from a clock input control device 1 through a line a. This input clock drives an external pulse generator through a delay circuit and delivers a +25V normal to line VM when the counter transient is over and safe. This pulse causes the threshold of the memory transistor in the counter to be -2
set to V. The pulse voltage of M then returns to -25V. At this time, the threshold value of some of the memory transistors changes to -10V in accordance with the state of the binary counter. As a result, the count value of the counter is held in the memory transistor. The other circuit configurations and operations are the same as those described in FIG. 1 and subsequent figures, so their explanations will be omitted. Next, FIG. 13 is a perspective view showing the appearance of an embodiment of a camera using the photographing information setting display method according to the present invention. As shown in the figure, each operation switch Swl to Sw4 in FIG. It is desirable that the camera be placed in the optimum location for the photographing operation.

FIGS. 14 and 15 are perspective views showing one embodiment of the configuration of the operation button (or lever) provided on the camera body and each switch inside the camera body in the method of the present invention.

In the figure, 101 is an operation button for setting information;
It is rotatably supported by a switch board 102 by a mechanism not shown. Swl and Sw2 are the up/down direction command switches and clock input control switches shown in FIG. 1, and by pressing the right or left protrusion of the button 101, the setting information is stepped up or down. 103 is a switch Sw for display control
This is a push button for operating 4.

In the arrangement shown in FIG. 15, the display control switch Sw4 can be operated either by operating the button 103 or by operating the setting button 101.
The first stroke of the button 101 switches the display switch Sw4.
Turn on Swl, Sw in the second stroke of 101.
2 is configured to turn on. As described above, in the shooting information setting display method according to the present invention, the setting information is changed stepwise by operating means such as a push button placed at an appropriate location on the camera, and the setting information is displayed on the display device together with the calculated value obtained from the calculator. It can be applied to digitally controlled cameras and has a great effect because it can display appropriate operation for various priority shooting modes, setting operations and warning displays when the control operation range is out of range. It is something.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of the photographing information setting display method according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of the clock input control device in FIG. 1, and FIG. A curve diagram showing an example of the timing chart of the circuit shown in the figure, FIG. 4 is a circuit configuration diagram showing an example of the counter control device in FIG. 1, and FIG. 6 is a block diagram of a logic circuit for a specific operation of the display control device shown in FIG. 5, FIG. 7 is a circuit block diagram showing another embodiment of the counter control device, and FIG. Block circuit diagrams showing other embodiments of the system of the present invention, FIGS. 9, 10, and 11 show other embodiments of the system of the present invention, in particular the essential parts for causing the counter to perform a specific operation. 12 is a block circuit diagram showing an application example of the method of the present invention, FIG. 13 is a perspective view showing the external appearance of a camera according to the method of the present invention, and FIGS. 14 and 15 are FIG. 3 is a perspective view showing an example of the configuration of provided operation buttons and respective changeover switches. 1... Clock input control device, 2...
Up-down counter 1, 3...Central control unit (CPU), 4...Counter control failure, 5.
... Display control device, 6 ... Display device, 7
......Clock signal generator, 8...Timer for self-preservation.

Claims (1)

[Claims] 1. An operation switch operated when setting exposure information, an operation signal forming means for detecting the state of the operation switch and forming a signal when the switch is operated, and forming a digital signal from the signal, digital signal forming means for sequentially updating the digital signal while the signal is being formed in response to the signal; and an operation for performing exposure calculation based on the digital signal and luminance information formed by the digital signal forming means. a circuit, a set exposure information display circuit that displays set exposure information according to the digital signal formed by the digital signal forming means, and a calculated value display circuit that displays the calculated value calculated by the calculation circuit; and a display control circuit that detects the signal of the operation signal forming means and forms a prohibition signal for prohibiting the display operation of the display circuit while the signal is being formed, and transmits the prohibition signal to the calculated value display circuit. An information setting display device for a camera, characterized in that the prohibition signal disables a calculated value display circuit and prohibits display of calculated values when an operation switch is operated.