JPS593075B2 - Video output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a DC regeneration circuit that clamps the pedestal level of a video output circuit of a color television receiver, particularly in the blanking section of a video signal, and particularly allows for easy and stable clamping. This is how it was done.

That is, in the present invention, the horizontal planking section of the luminance signal, including the horizontal synchronization signal part, is clamped to a constant level to obtain a luminance signal with the horizontal synchronization signal substantially removed, and this and each color difference are Each primary color signal without a horizontal synchronizing signal is obtained from signal No. 5, and the blanking section of this primary color signal is clamped to a constant level.

Hereinafter, one embodiment of the video output circuit according to the present invention will be described with reference to the drawings.

・0 In Figure 1, 1 is a clamp circuit that clamps the blanking section of the luminance signal SY to a constant level, 2R
, 2G and 2B are circuits that respectively matrix the luminance signal from the clamp circuit 1 and each color difference signal of red, green and blue to obtain a primary color signal, and clamp the blanking section of this primary color signal No. 15 to a constant level. The circuits 2R, 2G and 2B have the same configuration, and in the 60 clamp circuit 1, 3
and 4 are transistors for signal transmission, each having an emitter-follower configuration, and an output terminal 6 is led out from the emitter of the transistor 4 via a resistor 5.

T and 8 are transistors that constitute a comparator 9. The collector of the transistor 7 is connected to the power supply terminal 10, and the collector of the transistor 8 is connected to the power supply terminal 10 through a parallel circuit of a resistor 11 and a capacitor 12 for charging and discharging. The base of transistor 8 is connected to DC power supply 13 with voltage EB.
The base of the transistor 7 is connected to the output terminal 6, the emitters of these transistors 7 and 8 are connected in common, and the grounding point 30 is grounded through a series circuit of the resistor 14 and the collector emitter of the transistor 15. , the base of transistor 15 is connected to terminal 16,
The operation of the comparator 9 is controlled by the signal from this terminal 16. Transistor 3 and its emitter 35 This is a transistor that controls the current flowing through the resistor 18 connected to the output side.

A transistor 19 supplies the charging voltage of the capacitor 12 to the base of the transistor 17.

Further, 20 and 21 are transistors constituting a current switch 22 that is turned on and off by a signal from a terminal 23. The bases of these transistors 20 and 21 are connected in common, and the connection point is connected to the terminal 23, and each transistor The collectors and emitters of 20 and 21 are connected to each other, one connection point is connected to the DC power supply 13, and the other connection point is connected to the connection point between the resistor 5 and the base of the transistor 7. Then, the luminance signal SY (FIG. 2A) is supplied to the base of the transistor 3 through the terminal 24, and this is transmitted between the base and emitter of the transistor 3.
The signal is taken out to the connection point between the resistor 5 and the base of the transistor 7 through the resistor 18 and the base-emitter of the transistor 4 in sequence, and its horizontal blanking section is clamped to a constant level in the following manner.

That is, a signal SHD (FIG. 2B) in which the horizontal synchronizing signal is delayed by a time slightly longer than its pulse period is supplied to the base of the transistor 15 through the terminal 16, and this signal is turned on during the pulse period of the signal SHD. Therefore, during this pulse period, transistors 7 and 8 are turned on, comparator 9 is activated, and a constant voltage +EB, which is equal to the base voltage of transistor 8, is obtained on the base side of transistor 7.

This pulse section corresponds to the portion of the horizontal blanking section of the luminance signal SY after the horizontal synchronizing signal, and therefore the level of that section of the luminance signal is set to +EB. A charging current flows through the capacitor 12 during this pulse period, and the collector voltage of the transistor 8 during this pulse period is obtained as the charging voltage of the capacitor 12. If the discharge time constant is set sufficiently large, this charging voltage The held voltage is held for one horizontal period, and even if the transistors 7 and 8 are turned off and the comparator 9 becomes inactive in a period other than the pulse period of the signal SHD, this held voltage is supplied to the base of the transistor 19, and the transistor A constant voltage is supplied to the base of the transistor 17 in accordance with the voltage maintained therebetween, and the current flowing through the transistor 3 and the resistor 18 is controlled to a predetermined value for one horizontal interval.

Therefore, the pedestal level of the luminance signal is clamped to +E, and a luminance signal in which the pedestal level in the horizontal blanking section is clamped to a constant level is obtained on the emitter side of the transistor 4. Further, through the terminal 23, a horizontal periodic signal SF (FIG. 2C) having a pulse width wider than that of the horizontal synchronizing signal obtained by waveform shaping from the flyback pulse (FIG. 2F) is transmitted to the transistors 20 and 21.
The switch 22 is turned on during the horizontal blanking period of the luminance signal SY that includes the horizontal synchronizing signal, and in this period the potential at the connection between the resistor 5 and the transistor 7 is a constant voltage EB, and therefore The level becomes equal to the clamp level, and eventually the horizontal synchronizing signal is removed from terminal 6, and the level of the horizontal blanking section becomes a constant voltage E.
A signal SYO (FIG. 2D) is obtained. This signal SYO is supplied to the bases of input transistors 24R, 24G and 24B of circuits 2R, 2G and 2B, and each color difference signal SR-Y, SG-Y and SB-Y is supplied to the transistors through terminals 25R, 25G and 25B. 26
Supplied to the bases of R, 26G and 26B.

In this case, since the circuits 2R, 2G and 2B have similar configurations, the circuit 2R is replaced by the signal SYO and the red color difference signal SR.
An example will be explained in which the primary color signal SR is obtained from -Y and this is clamped.

The emitters of transistors 24R and 26R are commonly connected via resistors 27 and 28, respectively, and the connection point thereof is grounded via the collector emitter of transistor 29 and a resistor 30, and the signal SYO supplied to transistor 24R and transistor 26R are connected to each other. The red color-difference signal SR-Y supplied to The output terminal 33R is supplied to the base of the transistor 32 through the
It is taken out. Also in this circuit 2R, similarly to the clamp circuit 1, the pedestal level of the red primary color signal SR in the horizontal blanking section is clamped to a constant value. That is, 34 and 35 are transistors forming a comparator 36, and the collector of the transistor 34 is connected to the power supply terminal 10.
The collector of the transistor 35 is connected to the power supply terminal 10 through a parallel circuit of a resistor 37 and a capacitor 38, the base of the transistor 34 is connected to the output terminal 33R, and the base of the transistor 35 is connected to a DC power supply 39. , the emitters of transistors 34 and 35 are connected in common, and the connection point is connected to resistor 40 and transistor 4.
1 is grounded through a series circuit of collector emitters,
The base of this transistor 41 is connected to a terminal 42.

The transistor 43 is a transistor for supplying the voltage charged in the capacitor 38 to the base of the transistor 29. In this circuit 2R, a signal Sc (Fig. 2 E) obtained by waveform shaping the flyback pulse is supplied to the base of the transistor 41 through the terminal 42, and it is turned on during that pulse period and is turned on during this period. The comparator 36 becomes operational, and the horizontal blanking section of the red primary color signal is clamped to a constant level by the charging voltage of the capacitor 38, similar to the clamp circuit 1. in this case,
When the horizontal synchronizing signal is removed by the current switch 22, the luminance signal is affected by transients during switching, so by making the pulse width of the signal Sc narrower than the pulse width of the switching signal SF, The effects of this transient can be removed.

Similarly, in circuits 2G and 2B, a green primary color signal SG and a blue primary color signal SB with the horizontal blanking section clamped to a constant level are obtained at output terminals 33G and 33B, respectively.

These red, green, and blue primary color signals SR, SG, and SB are supplied to the cathode of the cathode ray tube.

As described above, according to the present invention, clamping is performed at the petestal level of the primary color signal obtained by matrixing the luminance signal and each color difference signal in which the horizontal blanking section including the horizontal synchronization signal part is kept at a constant level. This makes it possible to always perform reliable and stable clamping even if there is some phase variation in the clamp pulse, compared to the conventional case where the clamp must be accurately placed at the petestal position after the horizontal synchronization signal part. can do. Moreover, the width of the clamping pulse can be made wider than the pulse width of the horizontal synchronizing signal, so that stable clamping can be performed even with large DC changes in the color difference signal. Therefore, in the past, an amplifier was provided before the luminance signal clamp circuit in order to perform stable clamping due to white balance, but according to the present invention, stable clamping can be performed even if this amplifier is omitted. The white balance will not be distorted even when shooting. Therefore, since the signal level when matrixing the luminance signal and the color difference signal is small, the dynamic range of the output signal can be widened.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram of an example of a video output circuit according to the present invention, and FIG. 2 is a waveform diagram for explaining the same. 1 is a luminance signal clamp circuit, 9 is its comparator, 12
22 is a capacitor for holding the clamp voltage; 22 is a current switch; 2R, 2G, and 2B are circuits that matrix red, green, and blue color difference signals and luminance signals, respectively, and clamp the signals obtained by matrixing; and 28 is a resistor for matritnos, 36 is its comparator, 38
is a capacitor for clamp voltage hold.

Claims (1)

[Claims] 1 The luminance signal is clamped so that its synchronization signal level is at a constant level and the pedestal level is at the above-mentioned constant level, and the clamped luminance signal and each color difference signal are matrixed to form each primary color signal. a video output circuit in which each blanking section of the primary color signal obtained is clamped to a constant level, and each clamped primary color signal is supplied to a color cathode ray tube.