JPS593064B2 - Vertical sync pulse extraction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for extracting divided vertical synchronizing pulses from a television signal.

As can be seen from the composite video signal waveform shown in FIG. It is divided. 5 Extraction of such divided pulses of the vertical synchronization pulse is performed using, for example, the VIR (Particular Interval
When extracting reference) signals on the receiver side, the horizontal frequency pulses are counted by a counter and the starting pulse is set to 10.
This is because it is necessary to use this as a starting pulse when extracting at a predetermined number of pulses from the pulse.

The VIR signal is based on the chroma reference as shown in Figure 2.
Consists of various reference signals such as brightness reference and black reference.
The purpose of transmitting this signal is to prevent the hue, brightness, contrast, etc. of the color image information from deteriorating while it is being transmitted from the broadcasting station to the television receiver in the home, and also to prevent errors in the circuit on the receiver side. Similar deterioration occurs due to
The purpose is to correct this by adding a reference signal (VIR signal) from the broadcasting station, and there are already two or three broadcasting stations in the United States that insert this VIR signal within the vertical retrace period. The divided pulses of the vertical synchronization pulse extracted in the present invention are not only used for extracting the VIR signal, but are also used for extracting stationary field broadcast signals and for various other purposes. However, in this specification, the application of the circuit of the present invention will also be explained by taking as an example the case where it is used for extracting a VIR signal.

By the way, in order to generate a count start pulse that has been adopted for extracting a conventional VIR signal, a composite synchronization signal is integrated and a pulse is obtained from the integrated output.

However, in such a device, the starting points of the 35 pulses are different, and there is a possibility that accurate VIR signal sampling may not be performed.

To explain this point according to Figure 3, in Figure 3, I,
A' shows a part of the composite video signal A in FIG. 1, where A is for an even field and A7 is for an odd field.

Now, if we integrate the synchronization signal of an even field, we get the following equation, but in the case of an odd field, the horizontal synchronization pulse P'1 immediately before the first equalization pulse in the vertical retrace period is more than that of the even field. Since both are close to each other, the integral output voltage 7 is larger than that in the case of wo, and the trigger level starts earlier by that amount, and as a result, the rise time of the output pulse from the pulse generating means in the latter stage becomes shorter. It is faster in the case of the odd field shown in force 1 than in the case of the even field shown, and the two do not match. Therefore, even if this pulse is delayed to form a wide pulse that covers the 19th line, and the number of pulses in the horizontal period during that period is counted, and a VIR signal sampling pulse is generated at the predetermined count, the sampling pulse is The temporal position of occurrence is different between even and odd fields, resulting in the VIR signal not being extracted in either field. Furthermore, when a pulse is generated at a constant level of the integral output, the integral output has a fluctuation as shown in FIGS. Further, it is necessary to provide an adjustment means for adjusting the above-mentioned constant level, and use this to make an appropriate adjustment. The present invention proposes a circuit that can reliably extract vertical synchronizing pulses, especially its divided pulses, with a simple configuration, thereby ensuring reliable extraction of IR signals.

The circuit of the present invention will be described in detail below according to the embodiments shown in the drawings.

In the present invention, as shown in FIG. 4, a capacitor C1 and a collector-emitter of a third transistor T3 are inserted between the base of the first transistor T1 constituting the level detection circuit 1 and a reference potential point, and the third transistor By adding the composite synchronizing signal of negative polarity shown at the beginning of FIG. Transistor T3 is turned off. Furthermore, the resistance R
1 constitutes means for coupling the power supply +Vcc to the connection point between the capacitor C1 and the first transistor T1. Therefore, in each period, a charging current flows from the power supply voltage Vcc to the capacitor C1 through the resistor R1, and the base potential of the transistor T1 rises. However, the base potentials in the three types of pulse periods are not the same, and are high in the vertical synchronizing pulse P3 period having the largest pulse width, followed by the horizontal synchronizing pulse P1 period, and then the equalizing pulse P2 period. That is, as shown in FIG. 1C, the base potential of the first transistor T1 rises only to a low voltage value of E2 and El during the equalization pulse period and the horizontal synchronization pulse period, respectively, and rises to a high voltage value during the vertical synchronization pulse period. It increases to the value E3. Therefore, the base via of the second transistor T2 of the level detection circuit 1 is ? If ×Vcc is selected so that the bias resistors R6 and R7 are equal to R6+R7, the first transistor T1 is conductive only during the vertical synchronizing pulse P3, and the equalizing pulse P2
and is off during the horizontal synchronization pulse P1 period.

Therefore, only a positive vertical synchronizing pulse is generated at the collector of the second transistor T2.On the other hand, the third transistor T3 is not activated during periods other than the equalizing pulse, vertical synchronizing pulse, and horizontal synchronizing pulse. The third transistor C1 turns on and transfers all the charges accumulated in the capacitor C1 to the third transistor C1.
Since the output is emitted through the collector-emitter path of , the integral output is not added up for each pulse as shown in ⑲ and ⑲ of Fig. 3, and a so-called digital pulse output can be obtained. Therefore, in the circuit of the present invention, the vertical pulse can be extracted reliably, and the level setting can be made with Vcc and
It is only necessary to determine the level by the resistors R6 and R7, and there is no need to adjust the level later, which is convenient. Fifth
The figures below show an apparatus that employs the vertical synchronization pulse extraction circuit 2 of the present invention to generate pulses for extracting IR signals.

FIG. 5 is a block circuit diagram thereof, in which 2 is the vertical synchronizing pulse extraction circuit, 3 is a means for supplying horizontal frequency pulses, 4 is a counter for counting the vertical synchronizing pulses and horizontal frequency pulses, and 5 is the above-mentioned vertical synchronizing pulse extraction circuit. means for controlling the supply of pulses to said counter such that after the counter has counted an even number of vertical synchronization pulses, a horizontal frequency pulse is applied to said counter; This circuit generates a pulse with a width of approximately 1H when a count number corresponding to is reached.
Each component of such a device, together with associated circuitry, may further include a sixth
This is embodied in the figure. FIG. 6 shows a circuit configured for an IC, and the capacitor C1 is externally connected to pin 1. A composite sync pulse (see the beginning of FIG. 1) obtained by passing the composite video signal of FIG. 1 through an ordinary sync separation circuit of a television receiver is applied from pin 2 to the base of the switching transistor T1. The output pulse of the level detection circuit 1 turns off the transistor T4 in the next stage and generates a pulse of negative polarity at the voltage division point a on its collector side. That is, transistor T4
Normally, transistor T2 turns on when its base potential falls due to conduction, and point a is at a constant high level potential, but as mentioned above, when a positive pulse appears at the collector of transistor T2, it turns off. This is because point a is at ground potential. FIiJ, six pulses are generated at point a according to the large sawtooth wave voltage shown in FIG. Therefore, only two are shown in FIG. The Zener diode D2 connected to the second pin 2 is introduced as a noise countermeasure.

Next, the counter 4 is constructed by cascading five T-flip-flops, and the figure specifically shows only one of them, T-flip-flop F1, and the others are blocks F2 and F3.
, F4, and F5 are shown, but they all have the same circuit configuration. T. Fritub Flotub F1 was originally S1
is controlled by the set pulse so that Tl. is off and Tll is on, and the emitter current of Tll is flowing to the ground through T6. However, when the negative pulse generated at point a of the vertical synchronization pulse extraction circuit 2 is applied to transistors T6 and T7. , these T6
, T7 are turned off and the emitter current of Tll cannot flow through the collector-emitter of T2, but instead flows into the base of T8. Therefore, T8 turns on and TlO
．． When the base-emitter bias of Tflipflop increases, the T flipflop reverses state, TlO turns on and Tll turns off. When the counter 4 counts two input pulses, the emitter of the first decoder transistor Tl8 becomes a high level input signal, turning on the transistor Tl6 connected to its collector. Therefore, Tl4 of the flip-flop F6 is turned on and Tl5 is turned off. Then, as Tl5 is turned off, T5 is turned on, so that the pulse generated at the collector of the transistor T2 forming the differential pair is invalidated from then on and is not applied to the counter 4, as mentioned above. . However, as the other transistor Tl4 constituting the flip-flop F6 turns on, Tl2 turns off and Tl3 turns on, so the flyback pulse from pin 3 is applied to the counter 4 one after another through Tl3. Become. Thus, for the first two, the vertical sync pulses are applied, and subsequently the flyback pulses are applied to each component of the counter 4, Fl, F2, F3.
, F4, F5's first outputs are Sl, S2, S3 in FIG.
, S4, and S5. In this case, the flyback pulse is added to the counter after counting two vertical synchronization pulses, but the number of vertical synchronization pulses to be counted does not need to be limited to two; it may be four or six; It is fine as long as it is an even number.

However, an odd number of counts will cause a malfunction in either the even field or the odd field, which must be avoided. For example, as shown in FIG. 7, when counting only one vertical synchronizing pulse, in an even field, the flyback pulse H and the extracted vertical synchronizing pulse N are approximately at the same position, so the counter 4 counts only one vertical synchronizing pulse. The input pulse is as shown in Figure 4. However, in the odd field, the extracted vertical synchronizing pulse 5 is shifted from the repeating position of the flyback pulse 5, so the pulse input to the counter 4 is as shown in Figure 4. It becomes one more. When generating an IR signal extraction pulse, it is generated by counting a certain number of times from the start pulse.
In the case shown in FIG. 7, the disadvantageous result is that the VIR signal is not extracted in one of the fields. In this respect, if you count an even number of extracted vertical synchronization pulses and then add the flyback pulse to the counter, the number of counts up to the line where the VIR signal is inserted will be the same for both the even and odd fields.
There is no possibility of malfunction occurring in either field as described above.

However, if two of the even numbers are selected, there is an advantage that reliable operation can be expected even in a weak electric field. In other words, in the case of a weak electric field, the vertical synchronization pulse obtained from the synchronization separation circuit tends to collapse after the third pulse, as shown in Figure 9, but it is a fairly steady pulse up to the first two pulses. It is. Next, when the counter 4 to which the pulses are inputted in this manner counts a predetermined number of pulses, the circuit 6 that generates the VIR signal extraction pulse includes a second decoder transistor T32 and transistors T34 and T35 connected to the collector of the second decoder transistor T32. It is also composed of T36 and T37.

The emitter of the second decoder transistor T32 is connected to receive the outputs Sl, S2, S3, S4, and S5 of the counter 4, so that the count number of 17 can be seen from the waveform shown in FIG. By the way, T
Since the inputs of 32 are all at high level, the second decoder transistor T32 is turned off, so the transistor T34 connected to its collector is turned on, and T35 is turned off, so that the voltage at point b corresponds to approximately 1H. A negative gate pulse (see FIG. 1) is generated. At the same time, the transistor T36 is turned off, so the transistor T37 becomes conductive and generates a positive gate pulse corresponding to approximately 1H at its emitter. However, whether or not to generate positive and negative gate pulses should be determined in relation to the subsequent circuit (not shown), and therefore there are cases where only one gate pulse is required. Needless to say. The second decoder transistor T32 is conductive because at least one of the four inputs is at a low level at a point other than 17 out of 21 count pulses, and therefore the transistor connected to the collector becomes conductive. All the circuit states after T34 are reversed, and the gate pulse described above does not appear. Further, the transistor T33 connected to the base is given a flyback pulse (FIG. 1(f)) from pin 3 and becomes conductive only during the period of the flyback pulse. The period of the flyback pulse corresponds to decoder T32 becoming substantially inactive. Therefore, the gate pulse generated at each emitter of transistors T35 and T37 by counting 4i17 times becomes 1H period excluding the flyback pulse width.

In this way, the decoder T is used only during the flyback pulse period.
The reason why 32 is inoperative is as follows. Generally, a counter can be made into a synchronous counter by taking feedback using an AND circuit or the like, but such a synchronous counter inevitably has a complicated configuration.

For this reason, it is advantageous to employ an asynchronous counter as shown in FIG. 6, but such an asynchronous counter causes a time delay for each bit. FIG. 8 shows as an example the first output waveform of each T flip-flop at the point where the counter 4 has counted 16 pulses, and the changes in S2 to S5 that change according to changes in S1 are shown by dotted lines. As shown in the figure, a time delay occurs, albeit slightly. There is a possibility that the second decoder transistor T32 may malfunction within the signal delay time and generate a gate pulse at an unnecessary location. Therefore, a flyback pulse including such a delay time is used to disable the second decoder transistor T32 only during the pulse period. This eliminates malfunctions caused by minute time delays that occur in asynchronous counters, and even if the flyback pulse period is not activated, the resulting gate pulse has a width sufficient to extract the VIR signal. No problem. In order to eliminate the influence of time delay of such an asynchronous counter, a similar structure is used for the third decoder transistor T3O, which will be described later, and also for the first decoder transistor Tl8, which has already been described, as shown by T3l and Tl9. It has been adopted as such. Third decoder transistor T3O and transistors T29, T28, T2 connected to its collector
7, T26 and VCT2O are provided to cut off the pulse input to the counter 4 at a certain number or more, and if there is no means to cut off the pulse input to the counter in this way, the subsequent counter Due to the operation of 1
This is because the same count contents as the seven count contents are exhibited even during the scanning period, so that gate pulses are generated periodically at unnecessary times. The third decoder transistor T3O is connected to the counter S of each T flip-flop.
1, S2, S3, S4, and S5 are connected to the counter so as to be input to the emitters, so that they become non-conductive at the time of 21 counts. Accordingly, T29 is turned on,
T28 is turned off, T27, T26, and T2O are turned on, and the collector potential of Tl5, which constitutes the flip-flop F6, and the base potential of Tl4 are lowered, and Tl4 is turned off.
15 is turned on to invert the state of the flip-flop. Therefore, the switching transistor 3tT12 is turned on and Tl3 is turned off, and the flyback pulse from the third pin 3 is no longer supplied to the counter 4. A switching transistor T2 is connected to the emitter of the transistor T26 related to the output of the third decoder transistor T3O.
l to T25 are connected in parallel as shown, and T2
6, these transistors T2l, T25
are also conductive and their respective emitters are brought to a low level. This means that each flip-flop F1 to F constituting the counter 4
This means that the first outputs S1 to S5 are reset to the initial state of low level. In FIG. 1, the symbol H indicates the reset pulse in this case. If this reset pulse is too short, the counter 4
Considering that T2 cannot follow it, the transistor T2
A small capacitor C2 is inserted into the emitter of 7. The charge in the capacitor C2 charged by the conduction of the transistor T27 flows through the impedance between the base and emitter of the next stage T26, so the discharge time constant is large. In other words, with this circuit configuration, a sufficiently long time delay can be produced by simply creating a small capacitance within the IC. The reset pulse search thus has a time width sufficient to drive the counter 4. The vertical synchronization pulse extraction circuit of the present invention has the features and effects described above, but when this is used in a VIR signal extraction pulse generation device as shown in FIG. 9, the functions of the VIR signal extraction pulse generation device are improved. It also has the advantage of ensuring that

[Brief explanation of the drawing]

FIG. 1 is a signal waveform diagram for explaining the present invention, and FIG. 2 is a waveform diagram of a VIR signal. FIG. 3 is a waveform diagram illustrating a part of a conventional VIR signal sampling pulse generator. FIG. 4 is a circuit diagram showing a vertical synchronization pulse extraction circuit of the present invention. 5 to 8 show a VIR signal extraction pulse generator using the circuit of the present invention, FIG. 5 is a block circuit diagram thereof, FIG. 6 is a circuit diagram embodying FIG. 5, and FIG. FIG. 7, FIG. 8, and FIG. 9 are explanatory waveform diagrams. 1...
...Differential amplifier, T1...First transistor, T2...Second transistor, C1...
・Capacitor, T3...Third transistor.

Claims (1)

[Claims] 1 A circuit for extracting divided pulses of a vertical synchronizing pulse divided into a plurality of parts by a notch from a television signal, the circuit comprising first and second transistors whose emitters are commonly connected, and the base of the first transistor. and a capacitor connected to a reference potential point; a capacitor connected to the base of the first transistor and a reference potential point; means for coupling a power source to a connection point between the first transistor and the capacitor; The collector-emitter is connected between the base and the reference potential point, and the third pulse is turned off only during the equalization pulse of the composite synchronization signal, the divided pulse of the vertical synchronization pulse, and the horizontal synchronization pulse, which are applied to the base. A vertical synchronization pulse extraction circuit comprising a transistor and means for biasing the second transistor so that an output pulse is generated at the collector of the second transistor when the base potential of the first transistor exceeds a certain value during the divided pulse period.