JPS5930306B2 - electronic microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic microprocessor device, and more particularly to a microprocessor device having a power-up clear function for clearing memory when power is turned on.

Electronic calculators in which the major electronic functions are integrated on one large scale integrated semiconductor chip or on a small number of chips are described in the following US patents: US Pat.

On November 11, 1975, Michael J5 Kotchoman and Charles R. No. 3 U.S. patent granted to Grand
, 912, 532 No. 1 Calculator with Exchange Data Memory Register 8, dated January 20, 1976, by Kusha J. Fitzsia and Gieralt D. U.S. Patent No. 3,934,233, issued to Kusha, 1 Persistent Storage Device for Electronic Computers, dated January 6, 11976, and issued to Jiyoji L. US Pat. No. 3,931,507 to Pranchigam 1. Power Up Clearance in Electronic Digital Calculator 1.

The concepts of these applications have made it possible to significantly reduce the cost of small personal size calculators.

Continuing efforts to reduce the cost of these products include the design of single chip calculators for use in high capacity calculators such as scientific or commercial calculators.
The chip disclosed here not only has sufficient capacity to solve the more complex formulas and functions used in scientific and commercial calculators, including trigonometric and logarithmic formulas, but also has a number of It can also be used in scientific or commercial calculators since it also has several storage registers. The present invention relates to a microprocessor device having a power up clear function, and more particularly to a microprocessor device suitable for use in electronic calculators and the like.

In conventionally known microprocessor devices for electronic computers, there are two methods: using hardware logic circuits;
Alternatively, the power-up clear operation may be performed by providing the program counter with an address that specifies a specific location in read-only memory (ROM) where instructions for clearing the calculator's memory are stored. Ta. SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor device having a power-up clear function, which allows power-up clearing without the need for a particularly complex power-up clear logic circuit or special address insertion into a program counter. An object of the present invention is to provide a microprocessor device having a clearing function. FIG. 1 depicts a type of portable electronic calculator that may incorporate features of the present invention.

The calculator 1 has a keyboard 2 and a display device 3. In one embodiment, the display device 3 consists of twelve digits or characters each having a row of light emitting diodes, a vacuum fluorescent tube, and a liquid crystal or other display device. The display has eight digits for the mantissa, two digits for the exponent, two annotation positions for the sign (one for the mantissa, one for the exponent), etc., and can output data in scientific notation. Usually the display device is 7
Or, it is 8 segments, and a decimal point is displayed in each digit. The keyboard 2 or other such input device has a set of numeric keys 0-9, a decimal point key, and a plurality of function command keys including, for example, exponent, logarithm, and trigonometric functions. Exponential and logarithm function finger ◆ keys are, for example, X2, l/X,
It has l/X, eX, common logarithm of X, and natural logarithm of X.
Trigonometric functions include, for example, the sine, cosine, tangent, and their inverse functions, and the hyperpolytic sine, cosine, tangent, and their inverse functions of X. Other function command keys include store (STO) and recall (RCL).
) keys, each of which stores or recalls a number stored in one of the memory or storage registers on the chip. The exponent key (EE) allows exponent input of numbers displayed in scientific notation. Plus/minus keys are provided to change the sign of the displayed number.Exchange keys (X:Y
) is provided. Conventional function fingers ◆keys are also provided, including clear key (C), clear entry key (CE), plus (4), minus H, multiply (×),
Contains the divide (+) and equal (d) keys. Referring next to FIG. 2, there is shown a functional diagram of a single-chip calculator.

A single chip 10 is shown here in a standard 28 pin dual in-line package. However, single chip 1
12 character display device 11 using 0 segment scanning method
I want you to understand how they are interconnected. Each of the seven segments of the character plus the decimal point to each character position are individually commonly connected to segment scan conductor 14. The individual common lines to each character position are bus 1
5 to the chip 10. Although the details of segment scanning are discussed with respect to FIGS. 3 and 5, it will be apparent to those skilled in the art that the number of segments selected and the number of characters selected are design choices. The chip 10 is an X/
Interconnected with the Y matrix keyboard, row conductors 14' are individually connected to segment scan conductors 14 and column conductors 16'' are individually connected to chip 0 via bus 15.

An X/Y matrix keyboard having five rows of conductors 16'' and eight rows of conductors 14' can accommodate up to 40 switches located at the intersections of the conductors.

However, the number of conductors 14'', 16' and therefore the number of switches is a design choice. It is connected to the DC power supply.In addition, pin 28 is connected to the chip's oscillator frequency control means.
A resistor 13 is connected between 1 and 1. Of course, an external resistor 13 could be provided on the chip 10, but the frequency of the clock oscillator on the chip 10 could be reduced to 1g1. It is better to provide the resistor 13 outside the chip 10 in order to make the adjustment possible. Referring now to FIG. 3, there is shown a functional block diagram of the single chip calculator of the present invention, showing the various circuits provided on chip 10.

Detailed explanations of individual functional blocks are provided in sections 7, 8, 9, 10,
We will discuss Figure 11 next, and here we will limit ourselves to a general functional explanation of the basic device. In the block diagram of FIG. 3, the connections shown by single lines represent a plurality of actual device wirings, and for ease of explanation, a single line may represent a plurality of different functions. The calculator of the present invention has a main program persistent memory (read only memory) (ROM) 30 on chip 10, which has two parts, ROMAROMB. R.O.
The reason why M3O has two parts will be explained below regarding the instruction words in ROM3O. The main program ROM 3O responds to the 11-bit ROM address AIO-AO stored in the program counter 32a by issuing a 13-bit instruction word 112.
-10 is generated and supplied to the instruction word decoder logic 31. Command decoder logic 31 interprets commands received from ROM 30 and generates a plurality of command signals to other circuits on chip 10 in response. These finger signals direct how data is transferred within chip 10 and handled by arithmetic unit 40, and serve other functions, which will be explained with respect to the command signal receiving circuit. do. Program counter 32a has an at-on circuit and is associated with branch logic 32b.

The at-on circuit in the program counter 32a has various functions◆
The ROM address stored in the address register in the program counter 32a is incremented by adding 1 to the address stored in the address register every cycle, and the ROM address stored in the address register in the program counter 32a is incremented.
The instruction words stored in O can be read out sequentially. However, sometimes the same command may be executed repeatedly so that the at-on circuit within program counter 32a responds to a HOLD command, which may disable the at-on circuit and leave the address stored in program counter 32a unchanged. It's advantageous. Branch logic 32b inserts a new address into program counter 32a in response to commands generated by instruction decoder logic 31, so that the program stored in ROM 3O is executed instead of sequentially cycling the instructions stored in ROM 3O. 5 branches can be made to new locations in ROM3O. As can be seen with respect to the discussion of the instruction word set and the details of the branch logic 32b and program counter 32a circuits, the branch instruction received from the instruction word decoder logic 31 may be a conditional branch or an unconditional branch. done automatically. However, in the conditional case, the branch instruction is executed only when the state of conditional latch 41 matches the state of the selected bit within the conditional branch instruction. If there is no match, program counter 32a simply cycles to the next sequential ROM address. Thus, branch logic 32b and program counter 32a circuits are interfaced with condition latch 41. Once the branch is taken, the program counter must be updated with the new ROM address by branch logic 32b.

Typically this new ROM address is derived from a branch instruction, but as we have seen from our discussion of instruction + word sets, R
It can also be derived from an address stored in an auxiliary register called 5 register 34. The R5 register 34 can be loaded with an address corresponding to the press of a specific switch, ie, a key on the keyboard matrix 12 (FIG. 2), or a number supplied from the operation register 38 via the arithmetic unit 40, so that a new ROM address can be loaded with the press of a key. 1 generated in one of the operation registers depending on the specific key
It can be an indirect address. Branch logic and program counter circuit 32 is further interconnected with subroutine stack 33.

The subroutine stack 33 is preferably a 3-level stack with 11 bits per level, and the program counter 3 is activated in response to an unconditional branch command (CALL).
2a, and returns the most recently received ROM address to program counter 32a in response to a RETURN instruction ♦ received from command decoder logic 31. The ROM address loaded into the subroutine stack 33 in response to an unconditional branch command is:
This is the increment address that program counter 32a was scheduled to cycle through. Therefore, when an unconditional branch instruction is encountered in ROM 3O, the program counter 32a branches to the address specified by the unconditional branch instruction and increments that address by 1 for each instruction cycle until another branch or return instruction is received. Increment. When a return command is encountered, the most recently stored address in the subroutine stack 33 is loaded back to the program counter 32a, and the addressing of the program stored in the ROM 30 is returned by 1 to the instruction address according to the last unconditional branch instruction word position. Since the subroutine stack 33 is a three-level stack, three-level subrouting is possible. When the fourth address is loaded into the subroutine stack 33, the first storage address disappears, and the second to fourth addresses remain in the subroutine stack 33. R5 register 34 is an 8-bit register and is not generated by arithmetic unit 40 unless keyboard 0 logic 35 is combined with keyboard scanning circuitry in scan generator/counter 36 to indicate that one of the calculator keyboard keys has been pressed. The two least significant digits are stored, and when a key press is indicated, the address associated with the pressed key is loaded into the R5 register 34.

The keyboard key address loaded into R5 register 34 is then loaded into program counter 32a by a branch 1 command to 1R5, allowing the keyboard to be addressed to ROM 3O. Instead, use the contents of one or two of the operation registers 38 as described above? Branch 1 finger ◆ to R5 can also be used to perform indirect addressing. Since the program counter 32a is an 11-bit counter, when the 8-bit address from the R5 register 34 is loaded into the program counter 32a, O is loaded into the three most significant bits (MSB's). FIG. 6a shows the various operations on chip 10 and the format of the data stored in the storage registers, as well as the operation of the various mask codes used in the various instruction words.

Regarding the data format, the data word is 16 digit DO-D.
It turns out that it is l5. Most significant 3 digits (MSD's) are 1
2 flag bits and 13 digits with low validity (LS
D's) preferably provides 13 digits for numeric data. However, it has been found that the published calculator has sufficient flexibility to use some or all of the 3 MSDs in addition to the 13 LSDs for data storage if required for certain operations. Depending on whether the calculator is operated in hexadecimal or binary coded decimal, four binary bits are required to represent each digit. The data words are arranged in series and each data word has 64 (e.g. 16 x 4
) has binary bits. If you look at Figure 3 again, it is Chip 1.
0 has 4 operational registers (registers A-D) and 16 data storage registers (XO-X7 and Y.

-Y7) 39. Operation register 38 and storage register 39 are each 64-bit shift registers that accommodate a 64-bit format of data words. The 16 data storage registers 39 are separated into X and Y groups, each group having 8 registers connected in series, so that each group of 8 registers has 512 (e.g. 64 x 8
) can be regarded as a bit shift register.

Both groups of shift register memory register input/output (1/O)
It is interconnected with circuit 42. The first bit clocked out of storage register 39 is the lowest significant bit of digit DO. Similarly, the operation register 38 is also a 64-bit register, with the portion 38a having a 16-bit capacity and the portion 38b having a 4-bit capacity. The operation register 38 including the connection point between 38a and 38b is connected to the operation register and the arithmetic unit 40.
The register selection gate 43 is interconnected with a plurality of register selection gates 43 for controlling data exchange between the registers.

As will be discussed in detail later, the separation of the operation registers A-D 38 into the 16-bit and 4-bit parts and the connection to the register selection gate 43 facilitates the left-right shifting of data, since the data stored in the 38b part or the DO digit, e.g. This is because it is desirable for register select gate 43 to be able to selectively pick off the data word stored in section 38a beginning with the Dl5 digit at the beginning of an instruction cycle (state SO). The storage register I/O circuit 42 is a register A.
are interconnected to allow data words to be moved between selection storage register 39 and operation register A. As can be seen in Figure 14b, it is preferred that portions 38a of the registers are each capable of storing serial data into a pair of 30-bit shift registers.

The outputs and inputs of these registers are commonly connected but clocked by different clock pulses. Thus, odd bits are stored in one 30-bit shift register and even bits are stored in the other 30-bit shift register. Arithmetic unit 40 is also configured to clock data twice as fast as it is clocked into one of the 30-bit shift registers. With this configuration, section 38a can be of a conventional shift register design and data can be clocked to the chip twice as fast. Data can be output from register A 38 and stored in select storage registers and stored in register A.

To perform this movement of data words between register A and selection storage register 39, (1). (2) Which group is the specific storage register 39 selected from, X or Y? Does the data word move from register A to storage register or from storage register to registers A-S. The appropriate command from ROM 3O is received by command decoder 0 logic 31, which indicates whether to move. The contents of the address register, register address buffer (RAB) 44, indicate which of the eight registers in the addressed group is selected. RAB44 is a 2-bit address register,
R5 register (minimum 3 valid bits) by appropriate finger ◆
Alternatively, it can be loaded from the 3-bit setting of the instruction word.

The data words stored in the eight storage registers 39 in each group are normally recycled, with each 64-bit data word being moved to an adjacent storage register location during each instruction cycle. Thus 1
X during instruction cycle. The contents of X1 go to X1, the contents of X1 go to X2
Shift to. This shift is of course responsive to the output from clock 45. The storage register 1/O circuit 42 also has a 3-bit counter that clocks to indicate which of the eight data words stored in the similarly addressed group is ready to be read at X7 or Y7. Responsive to oscillator 40. Thus, the 3-bit counter in storage register I/0 circuit 42 increments by 1 for each instruction cycle. When reading or reading a data word into select storage register 39, RAB 44 is initially loaded with a 3-bit binary number indicating which of the eight data words in the group is being addressed. The instruction word then enters the appropriate group, X or Y, into the storage register I/O circuit 42.
1 and instructs an internal counter to count instruction cycles until the state of RAB 44 is matched. It can thus be seen that up to seven instruction cycles are required to shift selected data within an X or Y group to a position where it is read or ready to be read for that group. Thus, the storage register I/0 circuit 42 generates a HOLD command, which indicates that the counter in the storage register I/0 circuit 42 is RAB
44 is matched and the desired data is moved between the appropriate group and register A, incrementing of program counter 32 is inhibited. Arithmetic unit 40 is a serially configured arithmetic unit with a binary coded decimal (BCD) corrector.

The BCD correction device disables the operation unit 40 by an appropriate command and converts it to a hexadecimal base or binary coded 10 as required.
It can be operated on a hexadecimal basis. As mentioned above, the data format preferably has 12 flag bits. These flag bits are used in many problems, for example to preserve the width of the result of a logical operation. Having flag bits in the data words stored in operation registers 38A, 38B and storage register 39 is an important feature of the present invention, which increases programming flexibility in providing instruction words to ROM 3O and further Chip 10 is simplified by eliminating the need for individual or dedicated flag registers or latches previously used and allowing flags to be processed by arithmetic unit 40 rather than by a separate flag logic circuit as in the past. Arithmetic device 4
0 is responsive to the selection flag bit and the selection designation + (Table 1, Section 7) which sets the condition latch 41. Thus, the 12 flags can be individually set, reset, toggled, or tested according to the selection commands (Table 1, Section 7). Furthermore, the three MSDs used for flags can be operated on in hexadecimal using the appropriate instruction words (see Table 1) with the appropriate flag masks (Figure 6). The Set 5 Flag 1 instruction + (see Table 1, Section 7) loads the addressed flag bit h with a binary one; the Reset Flag 5 instruction loads a zero.

1 Toggle 1 changes the zero flag to 1 or the 1 flag to zero.

1 Flag Test 1 instruction will conditionally latch (
COND).

Thus, flag bits can be advantageously used to determine whether a conditional branch instruction will result in a branch. Register A and register B are output to display decoder 46 in response to a display command.

The contents of register A include the digits to be displayed by display device 11 (FIG. 2), and register B is coded with bits indicating the position of the decimal point and whether or not a particular digit is to be blanked. . Register B according to the instruction word included in ROM3O
Another important feature of the invention is the use of register B to store the digit blanking and unblanking codes as well as the decimal point and negative sign codes that are loaded into the A separate leading zero blanking circuit is not required. Display decoder 46 is connected via line 15 to an output register 47 which provides digit scan lines to display device 11. Scanning generator 36
, display decoder 46 and output register 47 cooperate to display display device 11 (second Figure). 4a and 4b, the timing signals generated by the clock oscillator on chip 10 are shown.

The clock oscillator may be of conventional design and is not shown in detail here. The clock oscillator sequentially generates clock pulses φ1, P1, φ2, P2, each pulse having a pulse width of approximately 0.625 μS in this embodiment. The exact frequency of the clock oscillator is typically fine-tuned using an external resistor 13 (FIG. 2). The entire sequence of the above four clock pulses consists of one state time SO, Sl,
S2, etc., and each state time is approximately 2 in this example.
．． Continues for 5μS. One state time represents the time required for two bits of a data word to be clocked out of the register.

Thus, it takes two state time for a 4-bit hexadecimal or binary coded decimal number to be input from the operation register 38 to the arithmetic unit 40. Since a total of 16 digits constitute one data word (as shown in FIG. 6), it takes 32 state times SO-S3l to output all 16 digits from the register. Thus, as shown in FIG. 4b, 32 state times SO-S3l
represents one instruction cycle, and in this embodiment one instruction cycle has a duration of approximately 80 μS. State time is generated by state time generator 48. As will be discussed in turn, the clock is responsive to decoded display commands that slow down the clock during display operations. The period of display operation state time is 10 μS, and the period of command cycle is 3
It is 20 μS. Furthermore, a clock pulse may be provided every time Pl, P2, simply labeled P in FIG. 4a, and another clock pulse may be provided every time φ1, φ2, simply labeled φ.

Furthermore, as shown in FIG. 4a, the selected state time (for example, Sl,
A clock pulse is supplied every selected P or φ time within φ2). FIG. 5a then shows ten decimal digits 0-9 that can be displayed by a seven segment character display with eight segments used as decimal points.

In FIG. 5b, the seven segments are labeled segments A-G and the decimal point segment is labeled P. There is a common cathode 9 for eight segments for each character position as shown in Figure 5b. The 8 segments A-G and P for each character position are connected to segment conductors SA-S respectively.
Commonly connected by G and Sp. Chip 10
No. 565,489, filed April 7, 1975.
We used segment scanning according to the method published in No.
-9 and a decimal point are formed. U.S. Patent Application No. 565,4
By using the segment scanning method of No. 89, the segment amplifiers commonly used in the past can be omitted. Chip 10 can thus be directly connected to display device 11. Again referring to FIG.
4 and pins SEGA-SEGG and SEGP (first
1) through the SA-SG and Sp conductors (Fig. 5b)
are sequentially excited.

Output register 47 receives the cathode 9 (fifth
A 12-bit binary code is loaded indicating whether the scanned segment in the corresponding character position is to be excited via line 15 and pins D1-D12 (FIG. 11). Looking at Figure 6a again, operation register 3
The format of the data words stored in 8A, 38b and storage register 39 (FIG. 3) is shown.

As mentioned above, each data word consists of 16 digits of serial data, each digit consisting of 4 serial bits. The entire data word thus consists of 64 (eg 16.times.4) bits. Preferably, the three most significant digits of the data word contain 12 flag bits and the remaining 13 digits contain numeric data, with the first 11 digits being the mantissa and the least two significant digits being the exponent. As mentioned above, 1 for each 13 digits of numeric data in one data word storage location.
The inclusion of two flag bits is an important feature of the invention, thereby eliminating the need for a separate flag register.

FIG. 6 shows mask codes included in many instruction words in the ROM 3O. Table 1 shows a set of instruction words that can be stored in ROM 30 and decoded by instruction decoder logic 31 (FIG. 3). In this example, R
The instruction word set stored in OM3O is shown in Table 1. 1st
As can be seen from the table, mask field codes (MF) are used in many possible instruction words. The mask field determines which digit of the 16-digit data word is assigned to the arithmetic unit 40 (Figure 3).
Register selection gate 4 determines which digits to recirculate through
3 (Fig. 3). The mask code is necessary because it often occurs that it is desired to perform some operation or flag logic operation on the mantissa only, the exponent only, both the mantissa and exponent, a particular flag bit, the entire data word, etc. In FIG. 6b, 12 masks having codes from 0000 to 1011 are shown with rectangles near the 16-digit data word. The digits enclosed in the rectangle accompanying the specific mask (when the accompanying mask code is received, the command decoder logic 3
1 (by the mask decoder logic 200 (FIG. 8)) to the arithmetic unit 40, and the digits outside the rectangle are passed to the gate 31.
6a-d (FIG. 9). As can be seen in the detailed study of the mask logic (Figure 8), the mask code is timed with the data output from the operational register 38 according to the state time indicated by the state time generator 48 (Figure 3). In this connection, register selection gate 43 (FIGS. 3 and 9) is operated.
Although the mask of FIG. 6b operates on all digits, other mask configurations may be used to select individual predetermined bits, as will be described below. Next, Table 1 in FIG. 12 shows a set of command words written in the ROM 3O, decoded by the command decoder logic 31, and used in other parts of the apparatus.

Table 1 relates to Figure 12 which shows the various command words. If you look at it, you will see that the life word is made up of 13 binary bits (112-10). The 13-bit instruction word length is 213
That is, there may be approximately 8,000 different instruction codes.

However, it is readily apparent that not all of these possible instructions are used. First, if you look at the first two instructions, 1 conditional branch 1 and 1 unconditional branch 1 instruction, 1 is in position 1 and 2.
It turns out that there is. Since all remaining instructions use 0 at position 112, it can be seen that there are approximately 4,000 changes between the first two instructions. ? Unconditional branch? The command is 1 at position 112, followed by position 111]C. ? It has addresses at positions 0, 11o-10. ? Since one unconditional branch address has 11 bits and the program counter 32a has 11 bits, one unconditional branch one instruction can branch anywhere in ROM 3O, including a branch between ROMA and ROMB. On the other hand, one conditional branch instruction has only a 10-bit address because 110 bits are used as conditional bits. If the state of the conditional bit (110) matches the state of the conditional latch, a branch occurs; otherwise, the branch instruction is ignored. Since the address of conditional branch 1 has only 10 bits, when the branch is taken, only the 10 bits with low validity are loaded into the 11-bit address register of program counter 32a. The most significant bit of the program counter does not change. A 0 in the most significant bit (A, O) in the program counter addresses only the instruction word in ROMA in ROM3O, and a 1 in the most significant bit (A, O) in the program counter addresses an instruction in ROMB in ROM3O. Since only the word is addressed, one conditional branch instruction is RO
It only branches within the range of MA or ROMB. An unconditional branch instruction is also considered one call and one instruction as long as the branch is completed and the incremented address (whose location follows the location of the unconditional branch instruction) is stored in the subroutine stack 33. Next, the command word listed next in Table 1, namely 1
Consider branch 1 and 1 return 1 to R5.

Regarding part 5 of Table 1, the operation under mask control is 0 in the 1 and 2 positions, mask field code in the 111-18 positions,
The instruction code is located at the 17-1 voltage position. As shown in Table 1, the instruction code is 2 bits J, 3 bits Kl, 2 bits L
1 and 1, with a bit N field. For special operations, the L and N fields are combined into one 3-bit field (LN field). Table 1 details the operations performed in response to the specific binary codes entered in the J, K, L, and N fields. The mask field i.e. I, l-18 has a mask code of 12 (000
0-0101, 0111-1010, J1101 and 1111) and the associated 4-bit binary number can have 16 codes, only 4 codes can be loaded into the mask field location, namely 0110, 1
011, 1100 and 1110 and they are not decoded as a mask operation.

Two of these four codes, 1110 and 1100,
is decoded by instruction word decoder logic 31.
The 1110 code is a miscellaneous non-mask code, and the instruction word group using the miscellaneous non-mask code is explained in Part 6 of Table 1.

Miscellaneous non-mask operations are at 11, position 02:. I
In addition to having 1110 in the -18 position, 4 bits Q and 4
It has a bit P field. In this instruction set, the Q field is ignored by redecoder logic 31 unless otherwise specified for this instruction set. The P field is decoded to perform the indicated operation, which is generally an operation that does not use arithmetic unit 40. These operations thus include data conversion between storage and operation registers, storage of the 3-bit code in RAB 44 (Figure 3), and storage of the 3-bit code in R5 register 34 (Figure 3).
It is related to the storage of the contents in the program counter 32a in FIG. 1 return 1 life + (Section 4 of Table 1) and return 1 position to 1R5 (Section 3 of Table 1) also have 1110 at the , 18th position, so they can be regarded as miscellaneous non-mask codes.

The return instruction branches to the most recently stored address on the subroutine stack 33. Other non-mask operations have flag operations defined at 1100 in mask field MF.

Details of the flag operation are explained in Table 1, Part 7. A flag operation, which is generally regarded as a non-mask operation, can be regarded as a very detailed mask operation in this calculator, because a specific flag bit of a data word does not simply operate on a specific digit. This is because it is tested or operated using the regular mask code defined in Figure 6. Because flags have typically been stored separately from numeric data in special registers in the latch, flag operations have not been considered similar to mask operations. DETAILED DESCRIPTION OF THE LOGIC DIAGRAM The various parts of the apparatus of FIG. ,10,11,13
Explanation will be given regarding the figure.

The following discussion with respect to FIGS. 7-11 concerns the logic signals available at various points on chip 10. logic 0
corresponds to a negative voltage, or Vdd, and a logic 1 corresponds to a 0 voltage, or Vs
Please remember that this corresponds to s. Furthermore, the seventh
Recall also that the P-channel MOS transistors of Figure 111 conduct when a logic 0 or negative voltage is applied to their respective gates. Logic signals without a bar are 1
Consider true 1 logic, ie, a binary 1 indicates the presence of the signal (Vss) and a binary 0 indicates the absence of the signal (Vdd). The logical signal name with a bar is 1 false - logic. That is, a binary 0dd voltage) indicates the presence of a signal and a binary 1 (Vss voltage) indicates the absence of a signal. 7-11 do not show the clock oscillator of chip 10, ie, the clock that generates clock pulses φ1, P1, φ2, P2 in accordance with the clock signal of FIG. 4a. The clock oscillator is of conventional design and is responsive to the decoded display command signal which reduces the clock frequency as described above. ROM and Program Counter Next, in FIG.
, the test logic and the logic diagram of ROM3O are shown along with the connection circuitry.

The details of ROM3O are not shown in Figure 7, but it is 19
Kuchisha J. dated January 20, 1976. This is a virtual grounding type disclosed in U.S. Pat. No. 3,934,233 issued to Fischer. Using the virtual ground fixed storage device of U.S. Pat. No. 3,934,233, the ROM can be made much smaller than conventional devices by using one ground or Ss line for five or more P diffusions.

Line A. -AlO at time S22. ROM3O at φ1
11-bit addresses are supplied in parallel.
Address line A. -A6 is U.S. Patent No. 3,934,233
Address lines A7-AlO address the Y address decoder of U.S. Pat. No. 3,934,233. line 1, 2-10
is address line A. - Supply instruction words corresponding to addresses occurring on AlO in parallel. The false logical instruction word is S29. φ
2, it is clocked out from the ROM 3O by the gate 111 and inverted to true logic by the inverter 110. That is, in order to sequentially read out desired command words from the ROM 3O during operation of the electronic microprocessor device, the precharge gate 114 performs S2l. φ2
Address line A at. - Precharge AlO to Vdd. In the program counter 32a, a code indicating the address of the ROM 3O where the desired instruction word is stored is on the address line A. -AlO, the address line AlO-M is stored corresponding to S2-2. At φ1, the gate 112 is opened, and the address line A is set by the program counter 32a according to the code in the program counter 32a.
. -A, O are selectively discharged, address line A; A precharge voltage Vdd remains in -AlO corresponding to the code in the program counter 32a. As a result, ROM is connected to address line A. - The desired command ◆word addressed by AlO and recorded at that address is line 1. -112. In other words, S22
．． At φ1, the address is loaded from the program counter 32a into the ROM3O by the gate 112, and the address is loaded into the ROM3O by the gate 112.
The instruction word is read from 3O. Power-up clear latch 162 is preferably incorporated into clock 45 and includes a latch that preferentially enters a first state to pass a logic 1 to the composite gate when power is initially applied to the device. When the clock is turned on sufficiently, the latch changes state, converting the capacitance associated with the reset input to the latch. When latch 162 is in the first state, address line A. - When the AlO is precharged, the composite gate 113 is activated at S22. Since the closed state of the gate 112 is maintained also at φ1, the address line A. -AlO is not discharged and ROM3O is assigned the first position (000000000002). That is, gate 114 controls S2l. of each instruction cycle. φ2
Address line A at.

- When AlO is unconditionally precharged to Vdd and the power up clear logic finally inserts O into composite gate 113, the address previously received by ROM 3O is 000000000002.

The power up clear logic thus effectively branches the ROM internally to the first location. 0 automatically using the ROM precharge gate 114 in combination with the gate 113.
Branching to 00,6 is an important feature of the present invention, allowing the address to be loaded into ROM 30 without the need for dedicated circuitry or jamming the address into program counter 32a after a change in the state of the PUC signal. position 00
According to the instruction word 1y starting with 016, the operation register 38,
Storage registers 39 and the remaining logic circuitry can be prepared for numerical operations.

That is, since the instruction word for initializing all the circuits including the program counter 32a of the electronic microprocessor device is stored in the first location of the ROM 3O, the latch 1
The addition of 62 and composite gate 113 effectively initializes the entire circuit when power is initially applied to the electronic microprocessor device. Program counter 3
2a consists of an 11-bit shift register having 22 inverter stages 115 and stages of precharge gates 116 and forming an address register.

A serial input to the program counter 32a is received on line 117 and a serial output is received on line 118 to the at-on circuit 1.
19. Gate 143 connects 11 stages of program counter 32a in series. Aton circuit 119
is a simplified at-on circuit having a NAND circuit 119a, one input of which is connected to line 118 and its output connected to inverter 119b. Inverter 119b
The output of is connected to another input of the NAND circuit 119a, the gate of the transistor 119c, and the source of the transistor 119d. Furthermore, line 118 is connected to transistor 1.
19c and the gate of transistor 119d. The drains of transistors 119c and 119d are combined to provide on line 120 the previous 11-bit program counter address incremented by one.
The HOLD signal generated by the gate 500 (FIG. 11) and the gate 291 (FIG. 8) is further connected to the connection point between the output of the NAND circuit 119a and the input of the inverter 119b. Prevents the program counter address from being incremented. The output of at-on circuit 119 is connected to normal line 120 and gate 12
1 to the input of program counter 32a on line 117.

Gate 121 is responsive to the output of NAND circuit 130 and R
Normally conductive unless inhibited by an ETURN or KBBRANCH (branch to R5) command.
Program counter 32a can also be loaded with 10 or 11 bits of the instruction word occurring at gate 110 via line 122 and gates 123 and 124. When the conditional branch instruction word is decoded and branch logic 32b determines that the condition is satisfied, the instruction word I is sent via line 122 and gate 123. The new branch address is loaded from the -1, bit to the program counter 32af)AO-A, bit. Unconditional branch instruction word (CALL)
When the instruction word (IO-.I,O) is decoded, gate 124 is made conductive at the same time as gate 123, and 11 bits are inserted into program counter 32a from the instruction word (IO-.I,O). 10 or 11 bits from the instruction word are loaded into the program counter 32a after the previous ROM address +1 is serially recirculated via lines 117, 120 and gate 121. Subroutine Stacks Subroutine stacks 33 each contain 22 bits. Inverter stage 1
11-bit shift registers 33a, 33b with 25
, 33c.

The subroutine stack 33 is the program counter 32a.
The 11-bit address stored therein is recycled through gate 126, except when outputting a return address or receiving an address from program counter 32a. Gate 126 is NAND circuit 135
It typically receives a logic 0 from NAND circuit 137 (ie, is rendered conductive), which provides a logic 1 output only if it receives a RETURN signal from , or a CALL signal from NAND circuit 136 . When the unconditional branch instruction is decoded by branch logic 32b, the CALL signal goes to 0 and line 120
The current ROM address +1 is loaded from the at-on circuit 119 to the subroutine stack register 33a via the gate 127.

The addresses previously loaded into subroutine stack/registers 33a and 33b are shifted by gate 128 into registers 33b and 33c, respectively. Gate 127,1
28 responds to the CALL signal. Even if the address is loaded into the subroutine stack register 33c in advance,
It is erased by the execution of another unconditional branch instruction. 1 return 1 (
RTN) When the instruction is decoded, the NAND circuit 135
The RETURN signal from becomes logic 0 and becomes NAND circuit 1.
30 is a logic 1, interrupting the normal insertion of the updated address via line 120 when gate 121 is non-conducting and sending the subroutine stack register to program counter 32a via gate 129 and line 117. 3
Forcibly insert the contents of 3a.

When the return instruction is executed, gate 131 inserts the contents of subroutine stack register 33b into register 33a, and inserts the contents of register 33c into register 33b. Gate 131 is RETU from NAND circuit 135
Responds to RN signals.

Branch Logic and Conditional Latch Branch logic 32b and conditional latch 41 cooperate to control gates 123 and 12 in program counter 32a for inserting the address portion of the branch instruction word into program counter 32a.
Control 4.

NAND circuit 132 forms a latch circuit for condition latch 41, and ADDERCO from gate 401 (FIG. 10)
Decoder 508c (first
It responds to the LOADR5 signal from Figure 1). The latch is reset by a return instruction or an instruction described below. The composite gate 133 receives the COND and COND signals generated by the NAND circuit 132 and the NAND circuit 14.
PREG signal from 6, I, O, Lτ from ROM3O
, 111, and 112 bits, and the T-view bit responds via an inverter 134. 0R circuit 133a, 13
Both bits 3b output logic 1 only when the state of the condition bit matches the state of 110 bits.

In this way, the output 112 from the 0R circuits 133a and 133b
, 11, bit and PREG signal together with AND circuit 1
33c, which is (1). When 111 and I,2 indicate that a conditional branch instruction has been output from ROM3O, (2). When the I, O bit states and COND match, (3). It outputs a logic 1 only when PREG is a logic 1 indicating that the PREG test circuit is not energized. The accompanying test circuitry and PREG and TRIG signals will now be described. NAND circuit 136 is 112
,〒BIT and PREG, and provides a CALL signal to NAND circuits 137, 138 and gates 127, 128 as long as the test circuit is not excited.〇NAN
D circuit 135 decodes 21 via inverter 159
4a (FIG. 8) and (1). - When a return command is decoded, (2). RETU is buried 1 when the PREG test circuit is not energized.
Responsive to the PREG signal to generate the RN signal.

NAND circuit 138 receives CAL from NAND circuit 136
L and (1). Is the unconditional branch (call) instruction decoded (2)? A TRI that generates a CALL signal that is normally logic 0 except when the test circuit is energized.
Reply to G.

In addition to the CALL signal from the NAND circuit 138, the gate 1
49 via S2O. NA receiving Pl clock signal
The ND circuit 139a is S2O. Composite gate 1 in Pl
39b-. Provides a CALL signal. If the test circuit is energized, the NAND circuit 139a is connected to S2O. S3O. in gate 150 instead of Pl. Responsive to the Pl clock signal. Composite gate 1 if the test circuit is not energized.
39b is S2l. CALL to gate 124 at φ1
Outputs a signal, and if excited, the CALL signal is S3l
, 00R circuit 1 supplied to gate 124 at φ1
33d is the output from the AND circuit 133c and the NAND
In response to the CALL from circuit 138, (1). Condition on conditional branch instruction/110 matches or (2). CAL
The occurrence of an L signal (on an unconditional branch instruction or PREG test mode operation) produces a logic I signal. 0
The output of the R circuit 133d is the normal S2O from the gate 149.
．． It is supplied to the NAND circuit 133e together with the Pl signal (or the S.3O.Pl signal during the TRIG test operation).

The NAND circuit 133e and the gate 140 are connected to S2l. φ
1 (S3O.Pl in test mode) at gate 1
The BRANCH signal is supplied to 23, and the command word I. -1,
Insert the bit into program counter 32a. Inverter 142 outputs a RETURN signal from the RTN signal received from decoder 214a (FIG. 8).

Gate 141 receives the I,2 branch bit, the RETURN signal from inverter 142, and S2O. In response to the φ1 signal, (1). branch + (for example, 112=1) or (
2}. When a no turn 1 instruction occurs, condition latch 141 is reset. Next, considering the timing of the addressing operation of the program counter 32a during the normal operation, the timing of the addressing operation of the program counter 32a
The address written in is incremented within the at-on circuit 119. If gate 143 in program counter 32a is clocked, S2-S21. The address incremented during φ1 is returned to program counter 32a. The incremented address in program counter 32a is thus updated by the state time Sl2 of the instruction cycle and the next S22. Gate 11 that reads the next command ◆word at φ1
2 to ROM3O. Conditional BRAN
CH (conditions are satisfied) operation is ROM3O
During S2-Sl2, the current address in program counter 32a is still incremented by the at-on circuit 119, but the BRANCH instruction is ◆The address part of the word is S2l. Action gate 12 at φ1
3,124 to the program counter 32a, resulting in S22. Insert a new address 1 state time before the new address is clocked into ROM 3O at φ1. This one-state time is sufficient to precharge and conditionally discharge inverter 115, which constitutes the stage of program counter 32a. The incremented address during the CALL operation is subroutine register 3.
3a of the CALL instruction in a manner similar to inputting the BRANCH address. A new address from -1,0 is clocked into program register 32a. The test circuit NAND circuit is S3l. PRE clocked by φ1
G in response to the TEST and K1 signals.

Similarly, NAND circuit 147 responds to TEST and K1, but SO. φ1 produces TRIG, which is inverted by inverter 148 to become TRIG. PREG is generated when it is desired to directly input a ROM address to the program counter 32a via the test keyboard line K1. TRIG is also generated when it is desired to serially read the instruction word at said address from the chip on line K2 during a test operation. Inverter 1
The output from 48 is NAND circuit 133e, 139a/S
．． S2O. S2O. The Pl clock signal is the clock signal used during non-TRIG test operations. T
The RIG signal is applied as an input to the NAND circuit 138 as well as S3O. Pl
It is also supplied to a gate 150 which supplies a clock signal, S
3O. The Pl clock signal is provided during TRIG test operations. PREG is inverted by inverter 151, the output of which is connected to gate 145 in line 117. Gate 145 is conductive except during test mode operation to recirculate the incremented address onto line 117. Thus, gate 145 indicates that during test mode operation the incremented address is sent to at-on circuit 119.
Insertion into the program counter 32a output from the program counter 32a is suppressed. Alternatively, the address on line 117 inserted during test mode operation is received from keyboard line K1 (FIG. 11) via gate 52 responsive to PREG. The output from program counter 32a is on line 118, inverter 153 and gates 601, 602.
(FIG. 13) to the keyboard line K2 (FIG. 11). As shown below, K2 is stored in ROM3 during state time S2-Sl2 of TRIG test mode operation.
Life ◆ word I addressed to O. - Receive 110 bits. Therefore, the output from program counter 32a on line 118 is sent to inverter 153 via gate 154.
2-Clocked by Sl2. Command words 111 and 1
12 bits are also output to K2 and these bits are sent to Sl3.
and Sl4 are output through gates 155 and 156, respectively, which supply the 11 and I,2 bits to the input of inverter 153. When the calculator enters the test mode via the input signals discussed with respect to FIG. Read out.

K via gate 152 once during PREG test mode.
Addresses can be inserted from 1 to the program counter 32a. This insertion into the program counter 32a is performed at the same timing as the update address from the at-on circuit 119. Any branch that occurs at the same time as the PREG test operation address is inserted into program counter 32a (according to a previously addressed instruction word) is inhibited by the PREG input to AND circuit 133c and NAND circuit 136. As the old address is thus shifted out of program counter 32a on line 118, an externally supplied address is input from K1 via gate 152 and line 117 during the same instruction cycle. The incremented address is cleared by action gate 145. Next this externally supplied address is followed by S2
2. It is used for the address of ROM3O in φ1.
(In addition to PREG) When the chip also enters TIRG test mode, S3l. The command word I in φ1.

The 11,0 bits are clocked into program counter 32a through gates 124 and 123 to clock CALLS2lφ1 and BRA during TIRG test mode operation.
NCH'S2l. It will be recalled that the φ1 signal is automatically excited in S3lφ1. Next I. The -110 bit instruction word is shifted out of program counter 32a via line 118, gate 154 and inverter 153 at S2-Sl2.phi.1. At the same time, a new address is input from K1 via gate 152. In this way, an external source can be used for the address of ROM3O during each cycle, and ROM3O can be used at that address.
The code contained in O is read out via K2 and sent to IO-1
10 bits are supplied from program counter 32a and 112 bits are supplied from gates 155 and 156. ROM3O
The entire contents of can be checked in approximately 2,000 instruction cycles, much more than 2,000 cycles if checking the contents of ROM3O requires the calculator to execute all instructions. It is clear that it requires Additionally, the state of condition latch 41 is changed to keyboard line K3 (CONI) via inverter 160 responsive to latch 41 and gates 605-608 (FIG. 13).
(Figure 11).

Similarly, during test mode operation, gates 605 and 6
HOLD is output to the keyboard line K3 via lines 07 and 608 (FIG. 13). Referring now to FIG. 13, the test logic associated with keyboard lines K1-K4 is shown.

The K1-K4 pins in FIG. 13 are the same as the K1-K4 pins in FIG. 11. The address received on line K1 is connected directly to the input of gate 152 (FIG. 7). The command word received from the ROM is outputted to pad K2 via gates 601 and 602. Gates 603 and 604, respectively, TEST and responsive to TEST isolate the instruction word output from line K2 except during test operations. Pin K4 is Vd
A TEST signal is generated in response to the d signal.

Pin K4 provides one input to NOR circuit 609. NO
Another input to R circuit 609 is S28. It is induced from φ1. The output of the NOR circuit 609 is the inverter 610
and is supplied to a NAND circuit 612 via a gate 611. Another input of NAND circuit 612 is responsive to power up clear signal PUC. NAND circuit 61
The output of 2 provides the TEST signal and the TEST signal via inverter 613. Pin K3 is responsive to the HOLD and COND signals generated by the calculator during test mode.

Therefore, the HOLD and COND signals are respectively connected to the gate 605.
, 606 and clocked at state times S3 and S2, respectively, to gate 604 responsive to TEST. The output of gate 607 drives gate 608 to provide a signal to pin K3 to indicate HOLD, COND during test operations. Instruction word decoder 0 logic The instruction word decoder 0 logic is shown in FIG.

In FIG. 8, a decoder 200 for decoding the mask portion of the instruction field decodes the mask field (MF) of the instruction word from the inverter 110 (FIG. 7), that is, bit 111-1.
8 and its complement 11, -18 are received. decoder 200
or B-E of the state-time generator 68 (FIG. 11).
(and its complement ir) output, which provides a binary representation of one of the 32 state times during which the device operates. One data word has 16 digits, and the first digit (DO) is S.

Since the input starts at S2, the input of the second digit starts at S2, and so on. The decoder 200 decodes the bits and masks MANT, LLSD, etc. (sixth
Figure b) is generated. Furthermore, the decoder 200 decodes 112 bits, 112 being logic 0 (then 12 being logic 1)
When a conditional or unconditional branch instruction is output from the ROM 3O (FIG. 7), the decoder 200 is disabled. The decoder 200 is described with reference to FIG.
Decode the second mask code. Recalling that the mask code indicates which bits of the data word are operated on by arithmetic unit 40 and which bits are simply recycled by register select gate 43, decoder 200
When a specific mask field is being decoded by the mask code shown in FIG. . Therefore, the decoder 200 is MF
It responds not only to the field (bits 111-18 of the command word) but also to the binary representation of one of the 32 state times in which the device operates. As mentioned above, since digits are output only during even state times, the decoder 200 outputs lines A or A.
There is no need to respond to the lowest valid bit from the top state time generator 48. Decoder 201 associated with decoder 200 is responsive to I, l-18 bits of the instruction word and its complement 11,-18, and further responsive to R bits 112 of the instruction word.
When a conditional or unconditional branch instruction is output from OM3O (FIG. 7), decoder 201 is disabled.

Decoder 201 decodes the miscellaneous (MISC) and flag operation (FLOP) codes, which also occupy the MF field as described with respect to Table 1, Sections 6 and 7. Decoder 201, MISC
The outputs from (via inverter 203) and FLGOP (along with FLGOP via inverter 211) are provided as inputs to several other decoders to disable or enable signals during miscellaneous or flag operations. I understand. The decoder 210 is the bit I of the life word.

-13 and its complement 1. MISC received from -13 and induced from the decoder 201 via the inverter 203.
This allows it to be used only during miscellaneous operations. The decoder 210 has a stack command + (STAY, STAX, .S
TYA, and STXA) and address buffer life +
(NAB and RAB), as described in Table 1, Section 6. Decoders 204 and 205 decode the bits and digit definition bits of the flag instruction (see fields B and D, section 7 of Table 1), respectively.
Decoder 204 receives the A and λ state times from state time generator 48 (FIG. 11) and the φ1 and φ2 clock pulses (associated with decoder 204).
(added to separate 204b) - and flag life +
(Refer to Section 7 of Table 1) The bits 12 to 13 determine which bit of the 4 bits of one digit is selected, and the decoder 204 responds to (1 ).selection bit and (2).The bit enters the arithmetic unit 40 and provides an enable signal when the time negated by the odd/even condition of the state time determined by the P1, P2 clocks and the state time A matches.

The decoder 205 selects the selected digit (bit 14-1 of the flag instruction).
It is determined by 5. B-E and B-E from the state-time generator 48 (FIG. 11).
In response to the -E output (1). Selected digit and (2). If the time at which the digit enters the arithmetic unit 40 matches, a usable signal is generated. The output of decoder 204 is NANDed by decoder 216 and output onto line 213, and the output of decoder 205 is NANDed by decoder 216 and output onto line 217. Lines 213 and 217 are applied to NAND circuit 207 whose output is connected to the input of NOR circuit 212. Another input to NOR circuit 212 is FLGOP from decoder 201, thus
NO when the flag operation instruction is decoded during the time when the bit selected by the decoder 204 within the digit selected in step 5 is output from the operation register 38 to the arithmetic unit 40.
R circuit 212 provides a logic one. The output from mask field decoder 200 is applied to decoder 202 to perform a NAND operation, resulting in (1). Is the mask operation decoded (2)? A logic 0 is output on line 218 unless state time counter 48 indicates that a select bit should be input to arithmetic unit 40. The outputs of NOR circuits 212 and 218 are applied to the input of NOR circuit 219, and (1) . Arithmetic mask operation decoded by decoder 200 or (2). Logic 1 except during flag bit mask operations decoded by decoders 204 and 205
Output. It can be seen that the arithmetic mask and flag mask are generated somewhat earlier than the selected digit or bit is output from the operational register, giving sufficient excitation time for the MOS gates. The output of NOR circuit 219 is a series of gates 2
20 to produce a signal MSKφ, which is output to the arithmetic unit 1φ time before the corresponding data is input to the adder. The output of the NOR circuit 219 is also inverted by an inverter 222 and sent to the mask delay generator 2.
25, supplies the MASKφ signal to the NAND circuit 230, gate 223, inverter 250, and gate 251. The mask delay generator 225, whose function is more fully described with respect to the operational register select gate 43, has a series of clocked inverters that provide a delayed mask signal in both true and false logic, and the MDφ/P signal is connected to an inverter. 2 than the MASKφ signal supplied from 222.
State time is delayed. The MDφ signal is 1φ time earlier than the regular MDφ/P signal, and the MDP signal is supplied and it is M
The P clock is supplied while the Dφ/P signal is being generated. The decoder 215 decodes the STORE signal (see LN field in Section 3 of Table 1) and the FLGOP signal and I
. -1, (and its complement) ---l-? ---? ---
--1b glaze" Tsugugaiyuu? Exposure---? ? -? 1SHIFT
signal, IR5 signal and 2R5 signal (see Table 1, Section 5 K field). Decoder 206 is MISC
Signal and I. - BCDS in response to 12-bit command + word
and a BCDR signal, which means that the arithmetic unit generates a BCD
Indicates whether or not to make corrections (see Table 1, Section 6).
These signals are sent to separate NAND circuits 2 that form a latch.
Added to 28,229. The output of this latch is HEX
This signal indicates whether the adder adds in hexadecimal or performs BCD correction. The decoder 208 generally selects the instruction word 1.

- Provides T/T and K→Y outputs in response to 14 bits. The T/T signal is generated during a flag operation in which a flag is tested or toggled; occurs in The K→Y signal is inverted by an inverter 252 and applied to the input of an AND circuit 251. AND circuit 2
51 is also responsive to the MASKφ signal from inverter 222 and the delayed MASKφ signal provided by inverter 250. When the K-Y signal and the MASK.phi. signal are thus generated, the AND circuit 251 adds 1 to the lowest significant bit of the lowest significant digit immediately following the beginning of the MASK.phi. signal. The T/T signal is also used to insert a 1 into the appropriate bit position in the Y input of arithmetic unit 40, and T/T is inverted by inverter 224 and applied as an input to NOR circuit 226, as shown below. . Another input to NOR circuit 226 is the output of AND circuit 251. NOR circuit 226
drives a series of gates 231 to insert the 1 into the appropriate bit position within the Y input of arithmetic unit 40. Decoder 2
09 decodes the BRK signal to cause a branch in the branch logic 32b, and the branch position is determined by the contents of the R5 register 34 (FIG. 10). Again in FIG. 7, the BKR signal is provided as an input to NAND circuit 130 and connected to line 12.
Interrupt the regular address recirculation path for update data via 0,117. BKR also inserts the contents of R5 register 34 into line 117 via inverter 158 and
5 to the program counter 32a is closed. Returning to FIG. 8, the NAND circuit 209a
The S/RS signal that sets or resets the flag is generated during a flag operation, and the DISP signal is generated during a display operation. The decoder 214 has 17 command words.
Generates signals used to operate the various register select gates and register recirculation gates in response to the -10 bits, FLGOP, FLGOP, and MISC signals.

The decoder section 214a generates an RTN (return) signal, which is transmitted by the inverter 142 and the NAND circuit 135 (
(Fig. 7). The decoder section 214b is an AX-D
The decoder section 214c generates the X signal and generates the AY-DY signal, which is inverted by the inverter 221. AX-
The DX and AY-DY signals are each connected to a NAND circuit 231a.
- 231b and 232a-232b, and is supplied to the operation register A using the register selection gate 43 (FIG. 9).
-D is interconnected with the X and Y inputs of the computing device. NAND circuits 231a-231d also connect the GMASK signal on line 234 and decoder 215.
in response to the STORE signal generated by the STORE signal.

NAND circuits 232a-232d also connect G on line 296.
Responsive to the MASK signal.

STORE and GMASK regarding the NAND circuit
The purpose of the signals and the movement of data in the various operating registers between operating registers and with respect to the arithmetic unit via register select gate 43 will now be described with respect to FIG. The 214d section of the decoder 214 is 10-1 of the instruction word.
Two bits are decoded and the bits corresponding to the L and LN fields of the instruction word control the operation under mask control (Section 5 of Table 1) to generate the EXCH and Σ→J signals. The Σ→J signal indicates the decoded instruction and the line Σ
Similarly, the Σ→K signal indicates that the result of the arithmetic unit 40 on line Σ5 goes to the register defined by the X field, or either field. Indicates going to an undefined register; in the latter case there will be a binary 10 in the L field, which will not be decoded by decoder 214. (See Table 1, Section 5) The decoder 214e is an FLG
OP and imperative words 11 and I. TGL in response to bit
(TOGGEL) signal is decoded and used to invert the selection flag bit. Ton? ? ? -Miyako--? Day-? ? ? ---
Sue-Yo? ? ? ? ? Peek l---? ? 1EXCH, Σ→K,
The Σ→J, TGL, STORE and S/RS signals are supplied to the decoder 227, and its output is supplied to the AX-DX, AY-DY signals from the inverter 221 and the NOR circuit 23.
7 to decode 238 along with the SR' signal from 7.

The output of the decoder 238 is input to the decoder 239 to generate recirculation signals RA, RB, RC, RD and the adder output ΣA.
, ΣB, ΣC, ΣD. The RB-RD recycle signal is inverted to true logic by inverter 236. The RB-RD signal is supplied to NOR circuits 235b-235d, respectively, along with the RECMASK signal from the NAND circuit 247 that generates the RECB-RECD signal. The recirculating signal 100 is also connected to the 0R circuit 2 along with the EXcI-r signal from the decoder 214 via the NAND circuit 240 which also responds to the
44 inputs.

The output of the 0R circuit 244 is converted to NA via an inverter 248.
The signal is supplied to the ND circuit 247.

The output of NAND circuit 245 is supplied to NAND circuit 246 to generate the RECA signal. NAND circuit 246 also outputs LA from inverter 249 indicating that the contents of one storage register should be output to the operation register.
ADA) signals. ΣA-ΣB of decoder 239
The outputs are respectively supplied to NAND circuits 233a-233d to generate Σ→A-Σ→D signals, which are sent to selector circuit 4.
3 to determine which operation register AD the result of the arithmetic unit 40 on line Σ5 should be transmitted to.

NAND circuits 233a-233d are also responsive to the MD signal from the output of the mask delay generator on line 253. Right shift (SR signal is SHIF of decoder 215
I from the T signal and the decoded instruction word.

A NOR circuit 237 is generated which is responsive to the bit. SR'
The signal is supplied to the decoder 238 and the NAND circuit 23
0 and supplies the SR signal to the register selection circuit 43. The SR signal supplied to the register selection circuit is mask-controlled, and as a result, the NAND circuit 230
It also responds to the MASKφ signal from the output of 22. SR''
The signal is further transmitted via an inverter 254 to an input or 0R circuit 253. 0R circuit 253 is AND circuit 22
Respond to 3.

The AND circuit 223 outputs the logic 0 signal supplied at S3lφ2, the logic 1 signal supplied at A1φ2, and 0R.
Responsive to circuit 294. 0R circuit 294 is NOR circuit 2
12 and a mask signal on line 218.

NAND circuit 247 connects the output of 0R circuit 253 and line 2
MD from mask delay generator 225 via 53
generates a RECMASK signal in response to φ/P, which inverter 248 and NOR circuits 235b-235d
supplied to

The 0R circuit 243 receives the MASKφ output of the NOR circuit 219 and the S from the decoder 214 via the inverter 255.
Responsive to HIFT signal.

The output of the 0R circuit 243 is the mask delay generator 225.
is supplied to the AND circuit 256 along with MDφ from .

AND circuit 257 outputs the output of NAND circuit 241, SHIFT of decoder 215, and MASKφ of NOR circuit 219.
respond to The outputs of AND circuits 256 and 257 are NOR
is supplied to circuit 259 to drive gate 295 and line 29
6 and generates the GMASK signal to the NAND circuit 231a.
231d and 232a-232d. NAND circuit 241 is responsive to the MDφ/P signal on line 253 and the EXCH signal from NAND circuit 240.

The 0R circuit 242 receives the SHIFT signal from the decoder 215 and the command I.

MD from bit and mask delay generator 225
Responds to the φ signal. The MDφ signal is 1φ smaller than the normal MDφ/T signal generated from the mask delay generator 225.
Occurs ahead of time. Output of 0R circuit 242 and NAN
The output of D circuit 241 is supplied to NAND circuit 260 to generate the SLRC' signal.

The SLRσ signal is inverted by an inverter 261 and sent to the SLRC
' signal to a series of gates 262, and line 2
63 and 264, respectively. The SLRC and SLRC signals are connected to gates 321a-32 in register select gate 43 (FIG. 9), respectively.
1d and 320a-320d1 and gate 230,
336a-d to control the right or normal shift of data, as described below. The TGL and EXCH'' signals from decoder 214d are NANDed.
TG supplied to circuit 274 and to arithmetic unit 40 on line 265.
Provides EXCH signal.

The LOADA(LA) signal supplied to inverter 249 is generated as follows. AND circuit 266 is responsive to the STXA and STYA signals from decoder 210. NOR circuit 267 responds to the output of AND circuit 266 and the COMPARE signal from comparison circuit 238 to
Generates A signal. NAND circuit 234 connects the MDφ/P signal on line 253 and the EXCH from inverter 240.
' signal, it supplies the EXCH signal to the appropriate register selection gate 43 (FIG. 9) under mask control.

EXCH' from the NAND circuit 240 is also connected to the inverter 26.
8 to the NAND circuit 269. NAND
Circuit 269 is also responsive to flag set/reset signal S/RS from NAND circuit 209a. NAND circuit 269 controls gate 270 to connect the output of arithmetic unit 40 on line Σ'' to a Σ bus connected to various register selection gates 43 (FIG. 9) and storage registers 39.S/RS signal Also includes a series of gates 271 for inserting a set or reset flag bit (defined by IO) via an inverter 272, and a series of gates 27
It is also provided to the register select gate via gate 292 which is responsive to 1. NAND circuit 273 is decoder 215
The STORE signal generated by the instruction word I.

The ADCON signal is generated to arithmetic unit 40 in response to the bit and FLGOP from decoder 201. ADCO
N is a logical 1 when the arithmetic unit adds data, ie, the X, Y inputs, and is a logical 0 when the arithmetic unit subtracts the data on the Y input from the data on the X input. Register address buffer RAB44 is a 3-bit address register shown in FIG. 8, and has three pairs of inverters 275, the contents of which are S3.
Normally recycled through gate 276 at O.

RAB44 is set to gate 2 by bits 14-16 of the instruction word.
77 and can be selectively loaded via gate 2
77 is controlled by a series of gates 279 responsive to the NAB signal received from decoder 210 via inverter 278 at S3l. Selectively select from the lowest three significant bits of the number stored in R5 register 34 via gate 280 energized by a series of gates 281 responsive to the RAB signal from decoder 210 via inverter 282 in RAB 44 or S3l. can be loaded. The outputs from the three stages of RAB 44 are applied in parallel to the input of comparator circuit 283 in storage register input/output circuit 42. Storage register input/output circuit The storage register input/output circuit 42 shown in FIG. 8 has a three-stage counter 284, and each stage includes two inverters 284a, 2.
84b.

The counter is incremented by the S29 signal every instruction cycle. The output of the three-stage counter is connected to a comparator circuit 283 on lines R, S, T.

Comparison circuit 283 outputs a COMPARE signal which is normally logic 1, and logic 0 indicates that the state of 3-bit counter 284 is R.
It is output only when it matches the 3-bit number in AB44. The output of the comparison circuit 283 is connected to the inputs of four NOR circuits 285a-285d. These four NOR circuits are STAY, STYA, and STAY generated by the decoder 210, respectively.
Connected separately to STAX and STXA signals, comparator circuit 2
It is also connected to the COMPARE signal from 83. Thus, the four NOR circuits 285a-d normally provide logic 0 outputs, but (1) . Decoding of storage register operations by PLS2IO and (2). COMP
When ARE becomes a logic 0, indicating a match between the contents of counter 284 and RAB 44, a selected one of NOR circuits 285a-d provides a logic 1 output. The NOR circuit 285a gates the data in the Y group of the normal storage register 39 in response to the STAY and COMPARE signals.
6a, but the STAY signal plus COM
Upon receiving the PARE signal (for example, both 0), NOR circuit 285a (via inverter 288a)
87a is made conductive and the gate 286a is made non-conductive.As a result, the selected data in the Y group storage register is read onto the open line 289a via the gate 287a and the gate 286a is made non-conductive.
Replace with the data read from b to the selected storage location in group Y.

Similarly, NOR circuit 285b normally recirculates within the X group of storage registers 39 via gate 286b, but causes data words to be read from operational register A into the X group via gate 287b. Here, the gate 287b is the NOR circuit 28
5b.
NOR circuits 285c and 285d each have an inverter 288
c and 288d to gates 287c and 287d to provide an insertion path for data words from selection storage register 39 to operation register A. STAY, STAX, S
The TYA and STXA signals are also supplied to the NAND circuit 290 and supply a logic 1 to the NAND circuit 291 when the storage register instruction has been decoded.

NAND circuit 291 also responds to COMPARE so that the storage register instruction is decoded and transferred to RAB 44 and counter 2.
Logic 0H0LD whenever there is a mismatch between 84 and 84.
supply the signal. The eight storage registers in each XY group of storage registers 39 are conventional shift registers and are not shown in detail here. Operation Register Selection Gate FIG. 9 shows an outline of the operation register selection gate.

As can be seen, the operational register selection gate generally includes a plurality of MOS transfer gates controlled by logic circuits 230-235, 246, and 262. As mentioned above, each of the operational registers A-D is divided into two parts 38A, 38B. Section 38A provides 16 bits to store fifteen 4-bit decimal digits.

Section 38B provides 4 bits of storage for one decimal digit.

Although details of the operation register stage are not shown, the conventional 21 stages can be used especially when the operation register has the configuration shown in FIG. State time S.

In the data word D. -D, 4th digit is 3 of operation register
The data is stored in section 8A, and the 5 digits of D1 are stored in section 38B.
The digits of the data word are clocked to a two-state time, and the state time S
Dl5 and D in 2. -Dl3 digits are stored in section 38A, and if the data is simply recirculated through gates 316a-316d, D14 digits are stored in section 38b.

Each operation register 38 has two outputs, and the X on the line 302
An input or Y input on line 303 is connected to arithmetic unit 40 . The normal output goes out on lines 301a-301d through gates 320a-320d, and the other output goes out on lines 305a-305d through gates 321a-321d. Gates 320a-320d, 321a-321d
The outputs of gates 310a-310d, 311a-311
d to common points 306a-306d before being connected to lines 302 and 303, respectively. Gate 320a-3
20d is the SLRC signal from line 263 (Figure 8), and gates 221a-221d are the S from line 264 (Figure 8).
Responds to LRC signals. The SLRC signal on line 263 is normally a logic 0, but if a left shift command is decoded by the command decoder logic 31, it becomes a logic 1 and the mask delay MD is enabled (e.g., logic 1) or replaced. The operation is displayed and the MD is enabled for use. Thus, gates 320a-320d are normally conductive, but gates 321a-321d are non-conductive except during said operation. The normal outputs of the operation register 38 are connected to common points 306a-306 by lines 301a-301d.
Exit to d. If a data word is not being output from the operating register 38, it is recycled, and during various output operations, data words are also recycled.

The normal recirculation path is through gates 316a of operational registers A-D.
- Pass through 316d. Gates 316a-316d are husband N
It responds to the RECA-RECD signals generated by AND circuit 246 and NOR circuits 235b-235d (FIG. 8).
Recirculation gates 316a-316d connect lines 305a-306
The output of section 38B on d is 38 on 307a-307d.
Connect to the input of part A. D when the entire data word is output to the arithmetic unit 40.

The digit is output from section 38A, and Dl, the digit is output from gate 316a.
-316d to section 38A and output therefrom as the last digit of the data word. D from the arithmetic unit because the arithmetic unit has a two-state time delay. The digit is entered into section 38A after D,5 has been recirculated. During perform, shift, and exchange operations, all or a selection of the data words stored in the operating register 38 can be operated according to the displayed operation (the selection being operated is a mask of the decoded instruction word). (instructed according to the field), the operation register selection gate 4
3 recirculates the non-selected portions of the data words and the selected portions are configured to be shifted, read/read from the arithmetic unit 40, or replaced if required by the decoded instruction word.

Since the normal output of the operation register appears on lines 301a-301d, the MASK supplied by inverter 222 (FIG. 8)
The φ signal occurs when a selected digit or a digit operated under a selected mask (FIG. 6) is output from section 38A. In reality, MASKφ is supplied 1φ time earlier and M
Set the OS gate in a timely manner.

However, gates 321a-321d operate on registers A-D during said right shift for an exchange operation.
Since we control the output from section 8B, the digit we want to unmask is outputted on lines 301a-301d later (by the time it takes to cycle section 38B, for example).
This occurs at the output of part B. Mask delay generator 225 (FIG. 8) thus delays MASKφ by a two-state time to provide the MDφ/P signal, which gate 246 and 235b-23
5d control. Next, the data word under the mask FbI is shifted to the right, for example, the data word M in the operation register A is shifted to the right.
Considering a right shift operation performed under the ANT mask (FIG. 6), the Dl5, DO, and Dl digits are first recycled through gate 316a.

Next, gate 316a opens, and the D3 digits from section 38A of operation register A are output to line 301a by gates 230a, 335a, and 336a and returned to the input of operation register A on line 307a.

During this time, the D2 digit is loaded into section 38B and gate 308
a, 309a to binary 0000 and is temporarily stored there until reinserted into the most significant digit of the data word under mask control, at which time gates 335a, 336a
is turned off and gate 316a is turned on again.
Thus, all digits in the MANT mask, ie D2-Dl2, are 1
It can be seen that the digits have been shifted to the right, the original lowest significant digit has been deleted, and 0000 has been loaded into the most significant j digits.

Gates 336a-336d are MASKφ and SR'(
The RECMASK signal from NAND circuit 230 (FIG. 8) is responsive to the RIGHT SHIFT signal. It can be seen that the recirculation gate normally operates on a two-state time delay mask, but must operate on a non-delay mask during right shift operations. Gate 337a-3
37d are controlled by register select logic 231a-231d responsive to the GMASK signal on line 234 (in this case the delay mass) and the STORE from decoder 215 (FIG. 8), respectively. Gates 308a-308d are NAND
In response to signals from circuits 231a-231d, gate 3
09a-309d respond to the SR signal from NAND circuit 230 (FIG. 8). For example, during left shifting of data in operation register A under MANT mask, Dl,,DO,D
, the digits are recycled by gate 316a. Thus, at the beginning of state time S6, the D digit is ready to be shifted from section 38A of operation register A. This hour line 263 (8th
The SLRC signal shown in FIG. 1 changes to binary 1 after the two-state time delay than the normal MASKφ signal, and the output from section 38B is applied to the X input of arithmetic unit 40 by gates 321a and 310a. The recirculation gate 361a similarly opens with a two-state time delay after the regular mask (for example, MD controls the RECMASK signal generated by the NAND circuit 247).At the same time, the output from the arithmetic unit 40 on the Σ5 line 410 (FIG. 10) is applied to the input of operational register A by gate 270 (FIG. 8) and 312a. Arithmetic unit 40 has a 4-bit delay and no data is being input, so line 30
The 38a part of the operation register A on 7a is output. Since no data is input to the Y input of the arithmetic unit 40, the data input to the X input is not changed during the left shift operation, and the most significant digit under mask control is transferred from the 038B section, which simply functions as a 4-bit delay. After being read out, the gate 316
a re-establishes recirculation mode and the SLRC signal returns to binary 0. Thus 000 to the lowest significant digit under mask control
A 0 is inserted, the most significant digit is deleted, and the intervening digit is a single digit shifted to the left. During the left shift operation described above, gates 310a-310d must be enabled for a mask delay two-state period.

However, during normal arithmetic operations where data is read on lines 301a-301d, gates 310a-3
10d and gates 311a-311d (which control the input of data to the Y input of arithmetic unit 40) must be operable to regular or delayed mask signals depending on the type of operation being performed. . In this way, various selection gates 310a-310d,
NAND circuit 231a- which controls 311a and 311d
231d, 232a-232d (FIG. 8) are connected to NAND circuit 259 (FIG. 8) on line 234 (FIG. 8) for all operations except exchange and left shift enabled by delay mask MDφ/P. GMASK from Figure 8)
The signal enables it to be used for regular masks.

Register select gates 312a-312 control data word input from the output of arithmetic unit 40 on line Σ7 to operational register 38 via Σ line 304 and gate 270 (FIG. 8).
d is controlled by NAND circuits 233a to 233d (FIG. 8), and the line Σ7 is controlled by the two-state time delay of the arithmetic unit 40.
Since the result of the arithmetic unit 40 above is delayed by one digit (two-state time), the NAND circuits 233a-233d can be used only by a delay mask. NAND circuit 231a
-231d is also inhibited by the STORE signal from decoder 209 and decoders 238, 23, defined by the register J field of the instruction word, which receives the data word.
Registers decoded at 9 (FIG. 8) are inhibited from entering the arithmetic unit. Additionally, during a storage operation, the output from one register is applied to the arithmetic unit 40, while the output from the other is inhibited by the STORE signal. The adder thus returns the data word to the other register without changing the input digits, storing the contents of one register in both registers. Gates 234 (FIG. 8), 314, 315 are used during exchange operations.

Considering the exchange between registers A and B under mask control, the digits are normally gated 316a-3 until the delay mask arrives.
16d, at which time gates 321a-d are conducting and recirculation gates 316a, 316b are non-conducting. Since the SLRC signal is a logic 0 when the exchange operation and the delay mask signal occur, gate 32 is now
1a and 321d are electrically connected. Next, the output of the register B is transmitted to the arithmetic unit 4 via the line 305b1 and the gates 321b and 311b.
Added to Y input of 0. Gate 338b connects line 234 (
The delay mask GMASK signal shown in FIG.
It is controlled by the D circuit 232b. Y of arithmetic device 40
In addition to going to the arithmetic unit 40, the contents of the operational register B occurring on the input are passed back to the A register by the gate 315, which is activated with a delay mask by the NAND circuit 234 (FIG. 8). The output of the A register is on line 305a1 gate 32
1a, 314 to line 304. Line 304 (2
1 is normally connected to the Σ5 line of the arithmetic unit 401,
During the swap and flag set/reset operations described above, it is disconnected from the Σ'' line by the action of gate 270 (FIG. 8). Line 304 is disconnected from the arithmetic unit, for example, during the swap operation, otherwise gate 314 disconnects the operating register A. The data applied to line 304 is miscarried by the data from arithmetic unit 40. Thus, the output from operational register A on line 346 is applied to gate 312b.
is selected to the input of operation register B via . gate 27
0 (FIG. 8) is the S/RS signal and the inverter 268 (
NAND circuit 2 responding to EXCH generated in Figure 8)
69 (FIG. 8). Gate 310a-3
10d, which of the operation registers A and D has a common point 306a
-306d to the X input of the arithmetic unit 40 on line 302;
It controls whether it is connected to the arithmetic unit 40 on line 303 via d.

Similarly, gates 312a-312d connect the output of arithmetic unit 40 on line 304 to any of the four operational registers A-D. It is an important feature of the invention that all operating registers can be connected to the inputs or outputs of the arithmetic unit 40, thereby increasing the programming flexibility of the calculator. during said storage and exchange operations, the exchange and storage are performed under mask control;
This enhances the programming flexibility of this electronic calculator.

This new feature can be used advantageously, for example, when it is desired to use all 16 digits of a data word during arithmetic operations. For example, the most significant three digits of a data word (usually used for flag storage; the sixth
(see figure a) can be stored in another operating register 38 or in a storage register 39, the 13 digits of the data word normally available in the arithmetic storage being extended to 16 digits for performing arithmetic operations. This is very important because it ensures that more digits than usual are obtained for the numerical data obtained during a calculation and that the final result is accurate, i.e. the final result is accurate to the decimal 10th position. advantageous, decimal 1
Intermediate answers up to 2 or 13 positions are often required. The new selection gating device 43 shown here allows the use of large capacity registers during such calculations without permanently providing such large capacity registers in the calculator. Arithmetic Device FIG. 10 shows the arithmetic device on the chip 10.

The arithmetic unit 40 receives H from the NAND circuit 229 (FIG. 8).
Indicates whether the calculation is performed in binary coded decimal or hexadecimal in response to the EX signal. The HEX signal is applied to NOR circuit 411 along with logic 1's from S27 to S1. NO
R circuit 411 outputs a HEX signal with false logic indicating whether hex signal BCDR has been decoded by decoder 206 (FIG. 8) or whether the data entering BCD modifier 408 on line 409 corresponds to a flag bit; At that time B.C.
The D correction device 408 is automatically disabled from state time S27 to S1. The output of the NOR circuit 411 is BCD
NAND circuit 407 that disables correction device 408 and NAND that disables invalid BCD code detector
applied to circuit 406. Adder 405 of arithmetic unit 40
acts on three serial data inputs 403, 404, 416.

Inputs 403, 404 correspond to the X, Y inputs, which are selectively coupled to operational registers AD by operational register select gate 43. Another input 416 has the CARRY/BORROW bit from composite gate 417. ADCON provides the SUB signal via (NAND circuit 273, inverter 418 from FIG. 8) and the ADD signal via another inverter 419.

Adder 405 performs the subtraction function using two's complement method.
Two's complement is performed by inverting each bit in the subtrahend and adding a binary one Z to each digit on line 416 unless a borrow operation has been performed on the previous digit.

When operating in addition mode, adder 405 receives a true Y input to gate 421 and gates 422,
423 receives Y input with false logic.

However, if the input is inverted for two's complement subtraction, gate 421 receives the Y input with false logic and gate 422
, 423 are received in true logic. Conversion between true/false logic and inversion for two's complement subtraction is performed by gates 420, 424 and inverter 425. Gate 420 conducts during two's complement subtraction in response to the ADD signal output by inverter 419, and gate 424 conducts during addition operations in response to the SUB signal output by inverter 418. Adder 4
The output of 05 is sent to the two-stage shift register 415 on line 426 and from there to the BCD corrector 40 on line 409.
It is sent to the 1st input of 8. The CARRY signal on line 427 from adder 405 is directed to NOR circuit 428 and composite gate 402. Composite gate 406 connects lines 403,4
Addition of digits input from adder 405 on 04 (or 2
Detection of an illegal BCD code in register 415 (H
NAN (unless disabled by EX)
A logic 1 is output to the D circuit 428. NOR circuit 428 thus outputs a correction signal that is a logic 0 if the CARRY signal is on line 427 or if the incorrect BCD code is detected by composite gate 406. Composite gate 417 is SUB, ADD, CORRECT, C
In response to the /BRESET signal, the C/BRESET signal is NORed with the CARRY signal on line 427 by NOR circuit 429.

The output from composite gate 417 is (1). If adder 405 is operating in addition mode and NOR circuit 428 indicates that CARRY is required, C/BRESET is O or (2) . Adder 405 is operating in subtraction mode and R
A logic 1 if ESET or CARRY is indicated. During two's complement subtraction, whenever the subtrahend is less than the minuend and there is no CARRY indication indicating that the subtrahend is greater than the minuend, a CARRY indication occurs, i.e., a borrow is made and an O is inserted on line 416, resulting in 2. The 1 that would normally be added to the lowest significant bit during complement subtraction is not inserted.

Thus, composite gate 417 has 4JCARR in addition mode.
Y or Not Produces a logic 0 when RESET is displayed or when RESET or CARRY is not displayed in subtraction mode.

The reset condition is indicated by a logic one on C/BRESET. C/BRESET is SO. Generated by NAND circuit 412 responsive to φ1 and the output of NAND circuit 413. NAND circuit 413 responds to MSK(1) from inverter 434 and delay MSKφ supplied by inverter 414. Composite gate 430 is CORREC
T, ADD, SUB, in response to the carry signals on lines 427, A and P1 clocks to determine whether an illegal BCD code or carry condition is detected by gate 428, so that BCD corrector 408 te1
Add 10 to subtract 0 decimal 6.

For example, the addition of decimal numbers X=5, Y=3 in adder 405 produces a binary output of 1000 on line 426, which is valid or CD 8. But if we add X=5 and Y=7, the output is 1100, which is not valid for BCD. When 6 (0110) and 1100 are added by the BCD correction device 408, 0010 is output on the line 410.

Carry is performed by gates 417, 428, 406,
Output 0010 (decimal 2) from BCD correction device 408
is of course the correct result. Since the lowest significant bit of each digit output by the adder 405 does not need to be modified, the lowest significant bit is determined by the composite gate 406 when the φ1 of each even state time is
Correction device 4 before testing incorrect BCD codes in
Enter 08. Composite gate 430 generates a binary 6 or 10 depending on whether an addition or subtraction is being performed.

As mentioned above, the output of composite gate 430 is
is not disabled by HEX, indicating that a hexadecimal operation is requested, but the adder 405 is operating in addition mode and a carry is indicated by the NOR circuit 428, or the adder 405 is not disabled by HEX. is operating in subtraction mode and line 427 indicates that no carry has been achieved.
Insert 0. The C/BRESET line 436 causes the composite gate 417 to input the first signal to be operated by the adder 405 during subtraction.
1 is inserted into the bit, and the insertion of 1 into the first bit is suppressed during addition, thereby suppressing the occurrence of inaccuracies due to the digits preexisting in the arithmetic unit 40 before insertion of the desired data. Composite gate 402 connects SUB, ADD, line 427 and COR
In response to RECr, (1). Does the gate 428 indicate a carry state during addition operation (2)? When line 427 indicates a borrow condition (no carry) during a subtraction operation, it produces a 1 at the output.

The output of composite gate 402 is applied to NAND circuit 401 and ADDERCONDI to condition latch 41 (FIG. 7).
Generates TIONSET. NAND circuit 401 is MAS
C from NOR circuit 437 unless a toggle or exchange operation is indicated, except at the end of a K operation.
/BSTROBE makes it unusable, and in the latter case M
Even if the end of the ASK operation is encountered, NAND circuit 401 is disabled by C/BSTROBE.

NOR circuit 437 is therefore responsive to TGLEXCH from NAND circuit 247 (FIG. 8) and mask trailing edge circuit 438. ADDERCONDITIONSET is logic 0 when there is a carry or borrow in the first digit after the mask.

This may result in an error indication depending on where in the program the overflow occurs, or it may indicate an overflow from a mask field indicating the desired logic state. Therefore, if the tested flag is set, ADDER
CONDITIONSET also produces a logic zero. Register R5R5 register 34 is shown in FIG.

R5 is an 8-bit shift register that can be selectively loaded from the serial output from arithmetic unit 40 on line 410 via gate 467 or from keyboard logic 35 via gate 478 on lines KRl-3 and KR5-. Can be done. (In the latter case, the MSB of each digit of register R534
is loaded with 0 through gate 479 according to the keyboard code shown in Table 1. ) The data stored in the R5 register 34 is sent to the Y input of the arithmetic unit 40 via a line 451 and an inverter 452, or to the program counter 32a (the seventh Figure) or inverter 46
3 to the RAB 44. An important feature of the present invention is that R5 register 34 can provide an address to program counter 32b or RAB 44, thereby allowing indirect addressing of program counter 32b and RAB 44. The R5 register 34 has 16 inverters 454 each consisting of two inverters 454 of 8 stages.

Each inverter 454 constituting one stage is connected through a gate 448 and can be connected through a recirculation gate 455 to recirculate the bits stored in each stage of the R5 register 34.

Gate 450 connects the stages to shift data between stages of R5 register 34 in a shift register mode.
R5 register 34 is connected to line KRl-KR3 and to line 45.
Unless loaded from the keyboard logic 35 in response to the L0ADR5K signal on the 7th, it operates in shift register mode and the lowest valid 2 of the adder output under control of the MDP signal received via the NAND circuits 461, 465a.
Receive and store digits. The R5 register 34 also receives the ゛゜Bra indicated by BKR from the decoder 209 (FIG. 8).
If the ncht0R5K instruction is decoded, it will operate in recirculation mode.

Thus, recirculation gate 455 connects NAND circuit 465as
NAND circuit 45 responsive to BKR and LOADR5
6. The output of the register R534 is sent to the adder 405 via the time line 451, which is enabled by the inverter 452 and the NAND circuit 458 and gate 459.
is also transmitted via line 449 to branch logic 32b.

The NAND circuit 458 and gate 459 are connected to the decoder 215 (
8) in response to the presence of the 1R5 or/and 2R5 signals from FIG. The three least significant bits of R5 register 34 can be loaded in parallel to RAB 44 via inverter 463. The 1R5 and 2R5 signals are applied to the inputs of two NAND circuits 460 and 461.

NAND circuit 461 also receives FL from inverter 462.
GOP signal and mask delay generator 225 (Figure 8)
The MDP signal supplied by the inverter 463 and the M
It also responds to the D signal. In this way, the NAND circuit 461 normally has logic 1, but depending on the MDP signal, 1R5, 2R5,
A logic 0 occurs when FLG0P is all logic 1 and the O output occurs only for 1P time. Logic 0 from NAND circuit 461 is passed through composite gate 464 to gates 465a and 46.
5b, to a latch 465 with a set latch 465, so that the output of gate 465a is a logic one and is passed to gate 465.
The output of 5b is a logic zero. A logic 0 on gate 465b enables gate 466 and therefore gate 467, and R
5 register 34 operates as a soft register, line 4
The first 8 bits read from the arithmetic unit 40 on the 02 are inserted into the R5 register 34 via the gate 467. Latch 465 provides a 0 and R output at the output of gate 465a.
It can be seen that, four state times after the five register 34 is loaded with the least significant two digits output on line 402, it is reset to the normal state by a 1 appearing at the output of 465b. The data output on line 431 is 2 times smaller than the regular mask.
Since the state time is delayed, the NAND circuit 461 is operated by a delay mask. NAND circuit 468 outputs the MSKφ signal from gate 220 received via inverter 434, the delayed MSKφ signal from inverter 469, and NAND
In response to the output of the D circuit 460, the output of the NAND circuit 468 is normally 1, but when the MSKφ signal and 1R5 or 7 positive h occur, P time 0 occurs and, like the NAND circuit 461, the latch 465a is set via the gate 464. do.

The set latch outputs a logic 1 from gate 465a and an O from gate 465b, making the output of gate 458 a logic 0, and NAND circuit 458b outputs logic 1 from gate 465a and O from gate 465b.
a, 460 output. The output of the NAND circuit 458 is sent to the R5 register 3 with the inverter 452 enabled.
4 or 8 bits of data stored in adder 4
05 into the Y input until latch 465 is reset to the normally set state. The latch 465 is (1),
“According to the Wi signal, the R5 register 34
1 digit is loaded into Y input of adder 405 (2), 2 digit is loaded from R5 register 34 to Y input of adder 405 according to input w signal.
Stays in the set state for 2 or 4 state times depending on which digit is loaded. Resetting the latch 465 to its normal state is accomplished by a two-speed shift register 440, which responds to the outputs of the NAND circuits 461 and 468 so that the state produced at the gates sets the latch two or four state times later. Reset latch 465.

1R5 signal is logic 0 from R5 register 34 to adder 40
The two-speed shift register 440 normally requires four bits to cycle one bit, except when indicating that only one digit of four bits is being shifted into the Y input of five and requesting a latch reset after two state times. Requires state time.

The two-speed shift register 440 includes a NAND circuit 470, a series of six inverters 471-476, and another NAND circuit 470, a series of six inverters 471-476, and another
It has an AND circuit 477.

NAND circuit 470, inverters 471-476, and NAND circuit 477 are connected in series with clocking gates 470a-476a arranged in adjacent stages. NA
Gate 470a between ND circuit 470 and inverter 471
The gate 474a between the inverters 474 and 475 is clocked to φ1, and the gate 412a between the inverters 472 and 473 and the inverter 416 and the NAND circuit 4
Gate 476a between 77 can be selectively clocked to φ1 or φ2. Other closing gates 4
71a, 473a, 475a are clocked to P. When gates 472a and 476a are clocked to φ2, a two-state time delay occurs in two-speed shift register 440, causing φ1
A four-state time delay occurs when clocked to . gate 4
Gates 72a and 476a are selectively clocked to φ1 and φ2 depending on the state of 1R5, and gates 472a and 476a are clocked to φ1 and φ2 depending on the state of 1R5.
When 5 is a logic 0, it is clocked to φ2, and when it is a logic 1, it is clocked to φ1. In this way, the closing gates 472a, 476a
is responsive to φ2 provided through gate 441. Gate 441 responds to 1R5 inverter and inverter 44
2 makes it true logic. Clocking gate 472a,
476a is also responsive to φ1 provided through gate 443. Gate 443 is controlled by inverter 444 which is responsive to the output of inverter 442. Scan Generator Counter and Segment/Keyboard Scan 1st
Figure 1 shows a keyboard logic 35, a display decoder 46,
Shown are output register 47, state time generator 48, scan generator counter 36A and segment/keyboard scan 36B.

The scanning generator counter 36A has a 3-bit shift register, each stage consisting of an inverter 501, 502, and outputs U, U, V, V, W, W. Scanning generator counter 36A also has a series of gates 508 responsive to the output of the inverter. The output of gate 508 is connected to the input of inverter 501 of the first stage of the counter. The inverters 501, 502 of each stage are interconnected by a gate 539 clocked by SOφ1, and the counter stages are connected by a gate 540 clocked by S3lPl. Thus the scanning generator counter 3
The number stored in 6A is updated every instruction cycle. The digits loaded into the counter are dictated by the pattern of the feedback logic 508, producing the output shown at A in FIG. Counter 36A sequentially counts 11 counts 1
1 is not executed, and 3 bits 2 from 0 to 7 are executed during 8 instruction cycles.
Produces a digit display. Gate 508 is counter 36A0)U
, an AND circuit 508a responsive to the output, and an AND circuit 5
08a and the counter 36A(:I)W output, and the 0R circuit 508b that responds to the output of the counter 36A (:I)W,
0R circuit 508c responsive to W output and 0R circuit 508
b, 508c.

The initial state of the counter 36A is 5 in each stage of the counter 36A.
RESET on line 505 inserting logic 1 into 01 gate
determined by the signal. As can be seen from Table A of FIG. 11, counter 36A counts 5 through eight different binary stages to produce the following binary sequence. 7, 6, 5, 2,
4,0,1,3, the counter only needs to count eight states, and the eight states need not be in any particular sequence.

Counter 36A is a new feature of the present invention and induces such a non-sequential binary output. Next, Table a shows the state in which the counter 36a counts.

All bits are shifted left by one bit and a new bit is inserted to change each instruction cycle each incremental cycle. New bits are generated in feedback logic 508 or other such feedback logic device. The pattern of gate 508 is described in terms of a 3-bit counter and includes the available signals: the output of each stage and its reciprocal, and the next result produced in response to solving the Cuff equation and decoding octal 6,0,1,3. can be induced by inserting a logical 1 into the least significant bit position of the number of times. On the contrary, 8
When a base 7, 5, 2, or 4 is decoded, an O is inserted into the lowest significant bit position of the generated order. The desired non-sequential state pattern is thus obtained. Next, Table Vb shows the counting state of a 4-bit non-sequential counter, for example. By providing a similar decoding method, i.e., a gate pattern such as the feedback logic 508 or other such feedback logic device, the outputs of the four stages and their reciprocals can be used to convert hexadecimal 0,1 ,3,7,14,13,12,2
A logic 1 can be applied to the lowest significant bit position of the resulting order in response to decoding. The exact pattern of such gates is not shown in detail here, but the pattern can be induced by solving the Cuff equation for the logic states of the feedback logic. Furthermore, the non-sequential counter shown here can also be used for counters having four or more stages. A segment/keyboard scan 36B with an 8-stage shift counter is provided,
It is a ring counter that shifts logic zeros to different stages during each instruction cycle.

Each of these stages has a pair of inverters 509 and 510, and only the first stage has a NAND circuit 509a and an inverter 5.
It has 10. The first stage drives the D segment of the display. The NAND circuit 509a is the final stage inverter 51
0 output and circuit ground clocked to S3lφ1. The eight stages in segment/keyboard scan 36B are connected by gate 514 clocked to S3OPl. Segment/keyboard scan 36B is also connected to the RESET signal on line 505 to insert a logic 1 into all stages of the counter, and gate 511 is used to insert a 1 into the 509 inverter. Gate 511a
inserts O into the first stage 510 inverter and it is NA
This is equivalent to inserting 1 into the ND circuit 509a. 509a
The NAND circuit is responsive to gate 512 to insert a zero into the first stage of the segment/keyboard scan during the next instruction cycle.

The output of each stage of inverter 510 is connected to an output driver 513 whose output is connected to pins SEGA-SEGG and SEGP. Thus, during each instruction cycle following the first instruction cycle, the segment pin (SEG
A-SEGG or SEGP) can be used. The segment driver also serves as a stroping line to strobe the keyboard as shown in FIG. The RESET signal is generated as follows.

DISP from a decoder 209 (FIG. 8) is supplied to a latch circuit having inverters 503 and 504. The output DISP of inverter 503 is NA
It is applied to the input of an edge detection circuit having an ND circuit 507. The edge detection circuit detects the decoded display command and outputs line 5.
The 00R circuit 515, which outputs RESET to the segment/keyboard scan 36B and scan generator counter 36A on the 05, is responsive to the DISP and RELHOLD signals.

NAMD circuit 500 responds to the HOLD signal from NAND circuit 219 (FIG. 8) and the output of OR circuit 515.
Output HOLD from NAND circuit 500 is supplied to at-on circuit 119 of program counter 32A (FIG. 7). When a HOLD signal is generated from the NAND circuit 219 or a display command is decoded due to a non-match between the contents of the counter 284 and the RAB 44, the gate 505
, 515 cooperates with at-on circuit 119 and program counter 32A to stop incrementing the number stored in program counter 32A, which continues until RELHOLD is generated. RELHOLD indicates that scan generator/counter 36A generated from PLA 527 has cycled through its possible eight states. Keyboard Logic The keyboard logic 35 has a decoder 517 driven by an inverter 518 which, via a buffer 516, connects the chip 10 pins K1-K5 to the conductors 16' of the X/Y matrix keyboard 12 (FIG. 2). connected to.

Inverter 518 normally provides a logic one output to decoder 517, and the output of decoder 517 is normally a logic zero. However, the key is pressed and the keyboard row conductor 14 goes to SE.
When being scanned by the output produced on GA-SEGP, a logic 0 is output by one of the inverters 518 and a specific one of the five keyboard lines K1-K5 is output from the decoder 517 to the three output lines KR5-KR7. A single binary representation of . At the same time, the KEYDN (key down) signal from decoder 517 becomes logic 1, indicating that the key has been pressed. Thus the U-W output scanning generator counter 3
When the KRl-KR3 inputs are loaded from 6a to R5 register 34, R5 register 3 is loaded from the output of decoder 517.
4 KR5-KR7 inputs are induced, and lines KRl-KR3 are induced for each key position of the X/Y matrix keyboard 12.
and produces a unique binary input on KR5-KR7. The inputs to R5 register 34 by keyboard logic 35 are shown in Table 1. KR1-KR3 and KR5-KR7 are entered into the R5 register 34 at S3OP1 when the calculator is in display mode after a key press. NAND circuit 51
9 is responsive to DISP, KRYDN and S3Oφ1 clock. The output from the NAND circuit 519 is S3OPl
is output through gate 520 at R5 register 3.
4 to line 457 (FIG. 10) and input the numbers from lines KR1-KR3 and KR5-KR7 indicating the specific key pressed during the display operation to R5.
Load into register 34. Display Decoder Display decoder 46 receives data representing the number to be displayed from operating register A on line 549 and outputs data to inverter 550.
to invert.

Of course, the data from operational register A is in serial format, and at even state time P1, the lowest significant bit (in both true logic) is first loaded into the two input lines of the programmable logic array (PLA) through gate 522; Gate 523 at the same state time P2
The bit with the next lowest degree of validity is loaded into the other two inputs of PLA 52l through the next odd state time (0, P1
), the next bit passes through gate 524 at P1.
It is transmitted to the other two inputs of LA5l2, and the next P2
The most significant bit of the digit is input to one input of PLA 5l2. where to display the decimal point between numbers in response to data from display decoder 46 or operation register B;
It indicates whether a negative sign should be added, which digit should be blanked according to the code shown in the table, and which digit should be decoded by inverters 525, 547, 548 and NOR circuit 526 together with PLAs 52l and 527.

As shown in the table, the least significant bit with a negative sign is clocked into inverter 525 through gate 528 at even state time (E,Pl)P1. Inverter 525
The output of is a false logic Minus signal and is clocked to PLA 52l, 527 at 0, P2 and E, φ1. A logical 1 in the second least significant bit from operations register B indicates that a decimal point has been applied to that digit. This bit is connected to gate 529 and inverter 547.
, 548 to the PLA 527 at E, P2. O in the most significant bit of a digit will display that digit (
In other words, it is not blank). This bit is N
The signal is passed to OR circuit 526, which also receives the DISP signal from decoder 209 (FIG. 8). This bit is clocked to the true logic ENABLE at odd state time P2.
Provides signal to PLA527.

Of course, if ENABLE is a logic zero, the associated digit position will be blanked. (However, decimal point segments are excluded).
The output of PLA 52l is output during 0, P2 and E, φ1. That is, 4 bits of the serial data digit are decoded by PLA 52l and then clocked out to PLA 527.

PLA 527 is also responsive to the UW signal (indicating which segment is being scanned) and its inverse provided by scan generator counter 36a.

PLA 527, 52l thus determines whether to load a logic 1 or logic 0 into output register 47 for each digit received from operation registers A, B during scanning of a particular segment of the display. A logic 1 from PLA 527 loaded into a stage of output register 47 indicates that the particular character segment scanned by segment/keyboard scan 36b in the display character position corresponding to that stage of output register 47 is to be activated. show. On the other hand, 0 indicates that the segment being scanned should not be excited for the digit position corresponding to that column. Decoder 529 is PLA54
The outputs of 7 are NANDed and 12 serial bits of data are supplied to a 12-bit shift register in output register 47. The display decoder 46, which is responsive to the contents of operation register A for numeric information and register B for display information, is a new feature of the present invention and reduces the number of dedicated circuits required for digit blanking, negative sign display and decimal position display. can be reduced. The disclosed device accumulates the contents of register B according to a code stored in a fixed memory supplying the display information, increasing the flexibility of the displayed numbers. This simplifies the simultaneous display of two different numbers, for example one on the right side of the display and one on the left side, adjacent to a negative number displayed differently than on the left side of the display in a conventional display. This simplifies adding a negative sign. P.L.A.
527 also responds to a decimal point blanking signal provided by inverter 551 at 0,P2.

Inverter 551 receives D from decoder 209 (FIG. 8).
Respond to ISP signals. ENA from NOR circuit 526
The BLE signal disables the A-G segment of the blanking display character. The decimal point blanking signal from inverter 551 is applied to programmable gate 536 in decoder 527 to blank the decimal point segment of the display. If programmable gate 536 is not programmed, the decimal point segment in the display will be activated even when the calculator is in a non-display (eg, calculation) mode. This new feature of the invention allows the decimal point segment visible to the user of the electronic calculator to be freely illuminated during calculations. This is particularly useful for long calculations that take more than a second, allowing the user to know that a function has been performed and reducing the apparent calculation time. If the calculator is not long programmed, gate 536 can be programmed to eliminate excitation of the decimal point segment during calculations. Output Register The output register 47 consists of a 12-stage shift register, and each stage has a pair of inverters 530 and 531.

The output register 47 is connected to the PLA 52 via a decoder 529.
7 to be loaded every instruction cycle. HO from NAND circuit 500 during the first instruction cycle of the display cycle
The LD signal inhibits incrementing of the program counter 32a;
The D segment in the display is decoded by display decoder 46 and output register 47 is loaded with code to strobe the D segment of the display. Output register 47
Keyboard/segment scan 36b is caused to begin scanning during the instruction cycle following the decoding of the display instruction since the contents of the display will not be provided to the display until the next instruction cycle. Initially the D segment is activated at the appropriate digit position for one instruction cycle, and during the next instruction cycle the A
segment, then B segment and so on, logic 0
continues as it progresses through keyboard/segment scan 36b. The calculator clock (Fig. 3) is decoder 209.
In response to the decoding of the display command according to (FIG. 8), the clock during the display operation is lowered.

Given the time required to turn on the VLED and the normal clock frequency of the calculator published here, the displayed duty cycle is approximately 65 (F6, so VL
When using an ED display, the clock must be ramped down during display operation. However, if the normal clock frequency is reduced by 1/4, the duty cycle will be approximately 95
%. Even with this reduction in speed, the segments appear to be constantly excited because they are scanned at a speed that is imperceptible to the human eye. To constantly excite the display device, the display instruction word is followed by a conditional branch instruction to branch back to the address of the display instruction, which indicates that conditional latch 41 is set by the LOADR5 signal and the user is inserting new data. It continues until it shows. Furthermore, in this embodiment, since the keyboard line KS7 is not strobed until the first display cycle is completed, two display destructions are used in pairs (A in FIG. 11). Recalling that the keyboard only responds to input during display cycle commands provided by NAND circuit 519, the keyboard will not be sensitive to keys on the KS7 line unless two display commands follow each other. Of course, the trailing edge circuit is NAND circuit 5
19 can be accumulated in the DISP signal to delay the signal 1 command. Each inverter 531 in output register 47 has gate 5 clocked by S3Oφ2.
32 to the inverter 533 or NAND circuit 5
34,535.

Inverter 533 and NAND circuits 534 and 535 are precharged to VSS1 in S3OP1. The stage corresponding to the lowest significant digit D1 of the output register 47 is N.
The depletion mode device 5 is activated by the AND circuit 535.
37 to provide the VDISP voltage to a pin of chip 10 (D1/SEGP), which is connected to the common electrode of the display in the lowest valid character position. NAND circuit 535 is also connected to the output of inverter 510 in the stage corresponding to the P segment of segmenter/keyboard scan 36b. Furthermore, driver 5 corresponding to the P segment
The output of No. 13 is connected to a depletion load device 537 corresponding to the lowest significant digit position of the output register 47. The decimal point segment (P segment), thereby reducing the number of pins used on chip 10, may not be excited at the least significant digit position. Inverter 510
and NAND circuit 535 ensure that current is not simultaneously sourced and sunk at the D1/SEGP pin. Similarly, the stage corresponding to the most significant digit Dl2 in the output register 47 is also connected to its depletion load device 537 via a NAND circuit 534.
and the output of segment D are connected to a common pin.

Thus, NAND circuit 534 is also responsive to the output from inverter 510 in segment D stage of segment/keyboard scan 36b. The remaining digit positions D2-Dll in output register 47 are connected to the appropriate pins on chip 10 via inverter 533 and gate 532, and the output of inverter 531 is connected to depletion load device 5.
Connected to 37. Thus, for the D1 lowest valid character position, all segments in the display except the P segment can be excited, for the D2-011 character position, all segments can be excited, and for the Dl2 character position, the D All segments except Segment are excitable. N
The outputs of AND circuits 534, 535 and inverter 533 are supplied to gate 538 in addition to gate 537.

Gate 538 is connected to the 12 display output pin (D1/SEGP-D
12/SEGD) selectively to the feedback circuit 541.
Connect to. The feedback circuit 541 is a keyboard/
The voltage of the excited VLED connected to the driver 513 in the segment scan 36B is kept constant. The operation of feedback circuit 541 is described in US Patent Application (Attorney's Litigation No. TI).
-6593). State Time Generator The state time generator 48 has a calculator clock φ1, P1.
, φ2 produces a binary representation, of which the calculator's 3
One of the two-state times is true logic on the line A-E and false logic on the line A-E.

Although state-time generator 48 is shown here as having five stages counting 32 possible states, state-time generator 40A can be configured to count 2N possible states, where N is the number of stages in the state-time generator. You'll soon find out that you can zoom in and out. The first stage of state time generator 48 includes inverters 542a, 543a placed in series with gate 544a clocked at time φ1 to form a latch. The 543a gate provides a true logic A output and the output of the 542a gate provides a false logic A output.

The output of gate 544a is connected to inverter 551a by gate 545a. The output of inverter 551a (1) provides a CARRY indication to another stage of state time generator 48 to indicate the CARRY state;
2), Inverter 54 is activated by gate 552a at time P2.
3a is clocked back and used to change the state of the latch. The gates and inverters with the symbol "1a" have the stage in state time generator 48 corresponding to the lowest significant bit. The stages in state time generator 48 corresponding to the more valid bits are (1)
, the sign of the gate and inverter number changes to one corresponding to the more effective bit output, (2) only when the CARRY signal, ie logic 1, occurs at the output of the inverter S55l of all the preceding less effective bit stages. Inverter 5
The output of 51 is identical to the previous stage except that it is clocked at time P2 to the input of inverter 543. Thus, gate 552b is responsive not only to the P2 clock signal, but also to the output of inverter 551a, which is provided by inverter 553a to gate 554a. Similarly, the third stage gate 552c of the state time generator 48 receives not only the P2 clock signal, but also the NAND circuit 553b and the gate 55.
It also responds to the outputs of inverters 551a and 551b via 4b. State time generator 48 operates as follows.

If state time generator 48 is at 00011 hours, inverters 543a, 551a, 543b, 55
1b, 542c, 542d, 542e all output logic 1, and inverters 542a, 542b, 543c, 55
1c, 543d, 551d, 543e, and 551e all output logic 0. However, at time P2, inverter 551a inserts a logic one into inverter 543a, changing the output of 543a to a logic zero. Inverter 553
Since a is outputting a logic 0, the inverter 551b similarly inserts a logic 1 into the inverter 543b, and the gate 55
4a prepares the P2 time signal. In addition, the inverter 551
The outputs of a and 551b are both logic 1, and the NAND circuit 5
Since the output of 53b is a logic 0, inverter 551c inserts a logic 0 into inverter 543c at time P2, and gate 552c conducts at time P2. Thus C
The output is a logic 1, and the B and A outputs are a logic 0. NA″ND
Since the circuits 553c and 553d both output logic 1 and at least one logic 0 is input thereto, the D and E outputs do not change, and the gates 554c and 554d
Other than 552e, the P2 clock is not conducted. The state time generator 48 can be easily extended by adding stages of the type described above and conditionally clocking the P2 pulse to the 552 gate, the condition being a NAND circuit responsive to the output of the inverter 551 in each less significant bit stage. Tested by 553.

The outputs from the state time generator stages on lines A-E and A-E are provided to a decoder 555 to provide an output corresponding to the particular state time required by the logic circuit of FIGS. 6-11.

State-time generator decoder 555 does not show the programmed gates, which are required by the logic circuit of FIG. 711, for example. ,S3O,S3,
Can be programmed to provide an indication of state time. Register configuration As described above, the operation register 38 and the storage register 3
9 generally consists of a long shift register, the stages of which are of known design.

However, if the basic clock frequency is 0.625 μS, the shift register of operation register 38 or storage register 39 must be able to store at a high bit rate, and furthermore, one bit must be clocked from one stage to the next with two clock phases. Must be. Although it is currently known how shift registers can store such bit rates in such a small number of clock phases (for example, the R5 register 34 is such a design), it is possible to halve the bit rate and transfer one bit between adjacent stages. The design of the operation register 38 and storage register 39 stages can be simplified if four clock phases are required to transfer the data. Figure 14 shows 60 and 5, respectively.
Operating register 14a and storage register 14c are shown configured as 12-bit shift registers. However, using the register configuration of Figures 14b and 14d, four clock phases can be used to transfer bits between adjacent stages of the shift register at half the speed of the registers of Figures 14a and 14c. The 30-bit and 256-bit shift register pairs of Figures 14b and 14d having common inputs and outputs are clocked to different phases of the same clock, i.e., one register is clocked to P1 phase, the other to P2 phase, and vice versa. One register can be clocked to the φ1 phase and the other to the φ2 phase, and these register pairs form a phase multiplex register. In both cases, the input and output of the register pair are connected to the intermediate stage of the conventional design. Furthermore, the first
The data flow at the input and output of the register pair of Figures 4b and 14d is equal to that of Figures 14a and 14c, respectively. These register pairs are an important feature of the present invention, allowing the use of conventional shift registers for high bit rates and shift registers having a small number of clock cycles for transferring bits between stages. In conventional four-phase data processors or calculators, each bit of data occupies one state time, that is, the processing of each bit requires four clock phases (φ1,
P1, φ2, P2) can be used.

Such devices are well suited to use precharge/discharge logic without creating race conditions. In order to reduce the number of internal connections associated with data routines and reduce the size of logic associated with computing unit 40, a fully serial data processing design is disclosed. The conventional serial design had a significant drawback: the processing speed was 1/4th that of the 4-bit parallel system for the same clock frequency. However, the processing speed of the present serial data processor is twice that of conventional designs without phase multiplexing registers and two-phase (rather than four-phase) serial leakage devices. The phase multiplex register (odd and even data bits are combined on a single line) has 4
Data bits are output every two phases instead of every phase. Each state time is therefore defined to have two serial bits of data rather than one bit. The series leakage counting device 40 performs precharge/precharge with two phases instead of the conventional four phases.
It operates on the discharge logic.

That is, a total bit and a carry bit are generated every two phases. The timing is the adder 40 on the P1 clock phase.
5 (FIG. 10), and the even bits are input on the P2 clock phase. When data is applied to inputs 403 and 404, adder 405 is precharged to both Pl and P2 clock phases, then discharged to φ2 to output the odd sum and carry bit, and discharged to φ1 to output the even sum and carry bit. Output carry bit. Arithmetic unit 40 has a 4-bit delay from input to output, which is equal to the two-state time and consists of four main parts. adder 405, 2-bit delay shift register 415, modification decoder and numeric generators 406, 428, 429, 430 . , and B
This is a CD correction device 408. Adder 405 is a complete adder/subtracter, and subtraction is performed in two's complement. Since a 2-bit delay is required to test the 3 most significant bits of each digit sum/difference in the correction decoder, a correction number (6 or 10) is generated and applied to the BCD correction unit 408 and added to the adder 40.
The binary sum/difference from 5 is converted to a BCD sum before entering one of the operational registers. Adder 405 and BCD modifier 408 are two-phase series binary complete adders. Using phase multiplexing registers and a two-phase arithmetic unit, a four-phase clock system can accommodate the six clocks normally associated with a 64-bit serial data word.
Instead of 4-state time, only 32-state time can be provided, thereby cutting instruction cycle time in half and doubling processing speed. As described above, according to the present invention, when power is initially applied to the microprocessor device, the first an initial application detection circuit that enters a state and enters a second state after a certain period of time;
a power-up clear circuit having a discharge prevention means for maintaining the gate in a closed state and causing a precharged address line to specify a predetermined address of the instruction word memory when the initial application detection circuit is in a first state; Since the electronic microprocessor device is initialized by an initialization instruction stored at a predetermined address, it is possible to initialize the device with 0U by adding a small amount of circuitry, making integration easier. , reduction in the number of chips due to increased integration, miniaturization of electronic microprocessor devices,
This has the effect of reducing costs.

Table 1 order 1. Conditional Branch - See Figure 12a.

The program counter branches to the location defined by the A field (10 bits) only if the C bit is in the same state as COND in the condition latch. 2. Unconditional branch (CALL)
1. See Figure 12b.

The program counter branches to the position determined by the A field (11 bits). The branched incremental address is stored on the subroutine stack. 3. Branch to R5 1st
See figure 2c.

The program counter branches to the location specified by the R5 register. Q field is ignored. 4. Return - see Figure 12d.

The program counter branches to the location determined by the final address stored in the subroutine stack. Q field is ignored. 5. Operation under mask control - see Figure 12e.

One of the MF-12 masks. See figure 6b. J-00
Operation register AOl operation register B IO operation register C ll operation register D A is added or subtracted from the contents of the register defined by K-000J.

B is added or subtracted from the contents of the register specified by 001J.

C is added or subtracted from the contents of the register specified by 010J.

D is added or subtracted from the contents of the register specified by 011J.

Decimal 1 is added or subtracted from the contents of the register specified by 100J.

The register specified by 101J is shifted one bit to the right or left.

R5 for the register specified by 11eJ (LSD) is added, subtracted or recorded. be remembered.

R5 for the register specified by 111J (both digits) are added, subtracted or memorized be done.

Operation result for the register specified by L-00J Operation result for the register specified by 01K (K = 000-011 only) 10 suppress (K = 000-100 only) or shift operation (K = 101) Operation result for the register specified by 01K Result 11 See explanation of LN field.

N-0 Addition (left shift) 1 Subtraction (right shift) Exchange from LN-110 register to A register (J=0
0 only).

The contents of register A are the contents of the operation register defined by K. (K=000,001, 010 or 011 only).

For exchange orders using masks containing Dl5 Register with mask containing DO Do not continue with the command.

111 Register to register storage.

The contents of the register defined by K are defined by J. is stored in the register to which it is stored.

(K=000,001,010,011, 110 or 111 only) If K is 100, then LSD is in decimal 1. Others in the register specified by J. O is stored in all digits.

(Only mask control digits are performed) 6. Non-mask operation (miscellaneous) - See Figure 12f.

Instructions do not depend on the contents of Q unless otherwise specified. The contents of one Y group storage register defined by P field 0000STYA-RAB are loaded into register A.

0001Q0) NAB-3LSD is stored in RAB.

0010 'Branch to R5' position instruction reference.

See 0011V1 return 1W instruction.

0100STAX-The contents of register A are To the X group storage register defined by RAB loaded.

The contents of the x group storage register defined by 0101STAX-RAB are loaded into register A.

0110STAY-The contents of register A are To the Y group storage register defined by RAB loaded.

0111DISP - Register A1 Register B is output to the display decoder and the keyboard is scanned.

The closed keyboard switch loads K5 and Set the item latch.

1000BCDS-BCD set 1 is the BCD of the arithmetic unit
Make the correction device available.

1001BCDR-BCD reset- is the BC of the arithmetic unit.
The D correction device is disabled and functions in hexadecimal.

RAB-LSD of 1010R5 (3 bits) is stored in RAB.

1011-1111 not used7. Non-mask operation (flag operation) - See Figure 12g.

Flag operations such as toggling, setting, resetting, and testing are performed by the arithmetic unit according to the flag address of register J, digit D1, and bit B.

When the flag is set, the flag test sets the condition latch. No other conditional latching occurs. The o toggle flag changes from 1 to O or from 0 to 1.

[Brief explanation of drawings]

FIG. 1 shows a portable, electronic, hand-held calculator incorporating the invention; FIG. 2 is a functional diagram of a single-chip calculator incorporating the invention; and FIG. 3 depicts a single-chip calculator incorporating the invention. Figures 4a and 4b show examples of the timing signals generated by the clock within the calculator, and Figures 5a and 5b illustrate how the segmented display and calculator are interconnected. Figures 6a and 6b show the format of the data words stored in the operating and storage registers of the calculator, the MASK codes used in the instruction words in fixed storage, and the various masks and data words. 7a-7c are logic diagrams of the calculator's program counter, branch logic, test circuitry, subroutine stack, and fixed storage; FIGS. 8a-81;
The figure is a logic diagram of the operation register, storage register, register address buffer, and counter associated with the instruction word decoder logic and storage register, FIG. 9 is a schematic diagram of the operation register selection gate, and FIGS. 10a to 10d are the arithmetic unit and Logic diagram of the R5 register, Figures 11a-11f, segment/keyboard scan and scan generator counters;
Logic diagram of the keyboard logic, display decoder, output register and state time generator; Figure 12 shows the format of the various instruction words shown in Table 1; Figure 13 shows the test circuit of Figure 7 and K1-K4 of Figure 11. A logic diagram of the circuitry used to connect to the keyboard pins, FIG. 14, shows another embodiment of the register configuration for the operational and storage registers of the present invention. Explanation of reference symbols, 1... Calculator, 2...
・Keyboard, 3, 11...Display device, 10・
...Single chip, 12...Keyboard matrix, 30...ROM, 31...
Instruction word decoder logic, 32...Program counter circuit, 32a...Program counter, 32b...Branch logic, 33...
Subroutine stack, 34...R5 register, 35...Keyboard logic, 36...
... Scan generator, 38 ... Operation register, 39 ... Memory register, 40 ... Arithmetic unit, 41 ... Condition latch, 42 ...・
・Storage register I/0 circuit, 43...Register selection gate, 44...Register address buffer, 46...Display decoder, 47...
Output register, 48...state time generator.

Claims (1)

[Claims] 1 Instruction words are stored in multiple addresses,
an instruction word memory having a plurality of address lines for specifying a desired address; precharging means for precharging the address line during a first predetermined period within each instruction cycle; a program counter that is opened at a second predetermined period after the first predetermined period within each instruction cycle, the program counter selectively discharging the precharged address lines; The electronic microprocessor device further includes an initialization command for initializing the electronic microprocessor device at a predetermined address of the instruction word memory, and a gate for discharging the electronic microprocessor device. an initial application detection circuit that preferentially enters a first state when an application is applied and enters a second state after a certain period of time; and an initial application detection circuit that maintains the closed state of the gate and is precharged when the initial application detection circuit is in the first state. 1. An electronic microprocessor device comprising: a power-up clear circuit having a discharge prevention circuit for causing the predetermined address of the instruction word memory to be designated by the address line as is.