JPS5930276B2 - Envelope signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an envelope signal generation circuit used when adding an amplitude envelope to a musical tone signal in an electronic musical instrument, and particularly to a circuit that generates an envelope signal whose attack level continues for a certain period of time. .

Conventionally, as a circuit for generating a percussive envelope signal, a circuit having a configuration shown in circuit portion 10 of FIG. 1 has been proposed.

This circuit 10 differentiates a key-on signal KON with a differentiating circuit 11, and then passes it through a diode D to form a trigger signal, which sets an R-S flip-flop 12, turns on a gate 13, and sets a capacitor C at a potential. source 14
(+V) and resistor rl are charged from the +VAL terminal of the attack level potential source consisting of 2 through resistor R and gate 13, and the terminal voltage of capacitor C is led to comparison picture 1T through buffer 16 to attack. An attack level detection signal is obtained from the comparison image 1T by comparing it with the level potential VAL and determining whether the difference between the two is within a predetermined range, and this attack level detection signal is used to flip the flip-flop 1.
2, the gate 13 is turned off and the gate 15 is turned on, and the capacitor C is connected to the resistor R.
2 and gate 15, and the output terminal of the buffer 16 rises from the initial level VIL to the attack level VAL in synchronization with the key-on timing, and then gradually rises to the attack level VAL as shown by the dashed line in FIG. A percussive envelope signal Vou attenuates to
t is obtained. Usually an envelope signal.

ut is supplied as a modulation signal to an amplitude modulator, such as a voltage-controlled variable gain amplifier (VCA) 20, which receives the musical tone signal IN as an input, and is used to amplitude-modulate the musical tone signal IN. By the way, as a result of such amplitude modulation, VC
The signal OUT obtained at the output terminal of A20 is V in FIG.

It should consist of a musical tone signal with an envelope as shown in ut, but in reality, the attack level decreases as shown by the broken line VAL5, and the vicinity of the peak becomes gentle, and the sense of attack is lost. There is. This is a musical tone signal 1N and an envelope signal V. This occurs because the phase relationship with ut is not constant, and the former peak and the latter peak are not necessarily at the same position, and this occurs particularly frequently when the frequency of the musical tone signal IN is low.
This has been a problem because even when keys are pressed under the same conditions, the attack feeling differs each time the key is pressed. SUMMARY OF THE INVENTION An object of the present invention is to provide a novel envelope signal generation circuit that solves these problems.

In order to achieve the above object, the present invention has a method in which when an envelope signal reaches an attack level, it maintains that value for a certain period of time (several 10 m8 corresponding to one to several waves of a musical tone signal) and then attenuates it. This makes it possible to obtain a constant, sharp sense of attack.

The invention will now be described in detail with reference to embodiments shown in the accompanying drawings.

FIG. 3 shows an envelope signal generating circuit according to a first embodiment of the present invention, in which the same parts as in FIG. 1 are given the same reference numerals.

18 is a differentiating circuit for differentiating the output of the comparator 17, D is a rectifier diode that passes only the standing differential output (attack level detection signal) EQ from the differentiating circuit 18, and 19 is a variable resistor 19a for pulse width control. A one-shot circuit (0S) triggered by the attack level detection signal EQ,
21 is one-shot output 0S0 and flip-flop 12
The charge control gate 13 is controlled by a control signal G1 consisting of the output Q of the flip-flop 12, and the discharge control gate 15 is an AND gate that ANDs the output Q of the flip-flop 12.
It is designed to be controlled by a control signal G2 formed from the output of the D gate 21.

FIG. 4 shows signal waveforms at various parts of the circuit of FIG. 3, and the operation of the circuit of FIG. 3 will be explained based on this.

When a specific key is pressed, a key-on signal KON is generated from the key switch corresponding to that key, and the differentiating circuit 11
supplied to A pulse synchronized with the rise of the key-on signal KON is taken out from the differentiating circuit 11 via the diode D, and this pulse sets the flip-flop 12. At this time, the control signal G1 consisting of the output Q of the flip-flop 12 turns on the gate 13, so that the capacitor C is charged toward VAL with a time constant of CR. As this charging progresses, the terminal voltage of the capacitor C becomes approximately equal to +VAL, the output level of the comparator 17 changes, and an attack level detection signal EQ consisting of a rising differential pulse corresponding to the change is sent to the differentiating circuit 18 and the diode D2. is retrieved via. The attack level detection signal EQ resets the flip-flop 12 on the one hand and triggers the one-shot circuit 19 on the other hand. Here, the operation time of the one-shot circuit 19 is
That is, the duration T of the output pulse 0S0 is longer than one cycle of the modulated signal (such as the musical tone signal 1N shown in FIG. 1), preferably 2 to 2 cycles, within a range that does not substantially impair the percussiveness of the envelope signal. This is set to be equal to three periods. Therefore, when the output pulse 0S0 of the one-shot circuit 19 and the output Q<15 of the flip-flop 12 are ANDed by the AND gate 21, the A
As the control signal G2 consisting of an ND output, a signal that changes from a low level to a high level after a period of T1 after reaching the attack level LAL is obtained, and the gate 15 controlled by the control signal G at this time is at the attack level. The ON control is performed after a period of T1 has elapsed since reaching VAL. For this reason, the capacitor C is connected to the resistor R, not from the moment the attack level AL is reached, but after a period of T1.
and discharge via the gate 15 with a time constant of CR2.
The potential change due to charging and discharging of the capacitor C as described above is converted into an envelope signal V via the buffer 16. It is retrieved as ut. Normally, the time constant determining resistors Rl and R2 are set in the relationship R, minus R2, so the envelope signal V.
As illustrated in FIG. 4, ut rapidly rises from the initial level LIL to the attack level VAL in synchronization with the key-on timing, maintains the attack level VAIfi- for a minute period T1, and then rises to the attack level VAL.
An overall percussive envelope signal is obtained that gradually attenuates from AL to the initial level IL. This envelope signal V. ut is used as a modulation signal when giving an amplitude envelope to a modulated signal such as a musical tone signal, as explained earlier with reference to FIG. Since the attack level VAL is maintained, at least one wave of the modulated signal is always included in the period T1. Therefore, the actual attack level no longer decreases due to a phase shift between the modulating signal (envelope signal) and the modulated signal (musical tone signal), as in the past.
This means that you will always get a stable, sharp feeling of attack. Next, an envelope signal generating circuit according to a second embodiment of the present invention will be described with reference to FIG.

In the circuit of Fig. 5, the same parts as shown in Figs. 1 and 2 are given the same reference numerals. The resistor is constituted by a voltage-strength variable resistor (VCR) 30, and by controlling the VCR 3O with various voltage values, any desired envelope signal can be easily obtained. In FIG. 5, 22, 23, 24, and 25 are attack level + VALL1 initial level V, respectively.
IL (in this case, ground potential), attack time potential +V
ATl is a potential source having a time potential +VDT, and is connected to gates 26, 27, 28, and 29, respectively. The gate 26 is for applying the attack level potential +VAL to one input terminal of the comparator 17 and the negative side of the auxiliary voltage source ΔV according to the output Q of the marip-flop 12, and the positive side of the auxiliary voltage source ΔV is connected to one end of the VCR 3O. It is connected to the. Further, the gate 27 is adapted to apply an initial level potential VIL to one end of the VCR 3O in accordance with the output Q of the flip-flop 12. Note that the voltage source Δ
V is for ensuring that the terminal voltage of capacitor C becomes equal to +VAL by increasing the charging target voltage of the capacitor charged via VCR3O by ΔV from +VAL. The gate 28 has an attack time potential of +V depending on the output Q of the flip-flop 12.
AT is supplied to the control terminal of the VCR3O via the resistor Ra, and the gate 29 supplies the decay time potential +VDT to the control terminal of the VCR3O via the resistor Ra in accordance with the output Q of the flip-flop 12. It's becoming like that.

The comparator 31 has +V1 (VIL, V,
At the same time, the voltage at one end of the VCR3O is applied to the other input terminal, and the voltage applied to the VCR3O changes from +VAL to VIL.
The output of the comparator 31 changes from a high level to a low level in response to the change.

The differentiating circuit 32 is for differentiating the output of the comparator 32, and the diode D3 is for taking out only the falling differential output from the differentiating circuit 32. This falling differential output is supplied to the one shot circuit 33 as a trigger input, and the negative progressive output pulse from the one shot circuit 33 is supplied to the control terminal of the VCR 3O via the resistor Rb.
The one shot circuit 33 has a variable resistance 33a whose operating time is
It can be set variably as appropriate, and in this example as well, a period corresponding to T described in the previous example is set. Next, the operation of the circuit shown in FIG. 5 will be explained.

First, in the initial state, the flip-flop 12 is in the set state, so the outputs Q and Q are "low" and "high," respectively.
The gates 26 and 28 are off, and the gates 27 and 28 are off.
29 are in each on state. Under such conditions,
An initial level position VIL is given to one end of the VCR3O, and correspondingly, the terminal voltage of the capacitor C is also approximately zero. Next, when the key-on signal KON is generated, the flip-flop 12 is set as described above, and its outputs Q and Q become "high" and "low", respectively. Therefore, the gates 26 and 28 are controlled to be turned on, and the gates 27 and 29 are controlled to be turned off. Therefore, the capacitor C is charged with a voltage of +VAL+Δ via the VCR 3O, and the charging time constant at this time is equal to the product of the resistance value of the VCR 3O defined by the attack time potential +VAT and the capacitance value of the capacitor C. As capacitor C is charged, its terminal voltage increases and eventually becomes equal to VAL.

This terminal voltage VAL is applied to a comparator 17 via a buffer 16.
Since the comparator 17 is applied to the other input terminal of
A match signal is generated when the two inputs match. This coincidence signal is converted into a rising differential pulse via the differentiating circuit 18 and the diode D2, and then is applied to the flip-flop 1.
2 is added as a reset signal. As a result, the outputs Q and Q of the flip-flop 12 are "low" and "high," respectively.
Therefore, the gates 26 and 28 are turned off and the gates 27 and 29 are turned on. Voltage V at one end of VCR3O at this time
The change from AL to VIL is detected by comparator 31.

That is, since the output level of the comparator 31 changes from "high" to "low" in response to the voltage change, this output signal is converted into a falling differential pulse via the differentiating circuit 32 and the diode D. The one-shot circuit 33 is triggered by this falling differential pulse and operates for a predetermined minute period. A negative pulse of a predetermined width generated from the one-shot circuit 33 is applied to the VCR 3O via a resistor Rb, and is controlled to have an extremely high resistance value. Therefore, the capacitor C does not start discharging immediately after the flip-flop 12 is reset, but starts discharging after a period corresponding to the operating time of the one-shot circuit 33 (a period corresponding to the above-mentioned T1). Here, the time constant when discharging the capacitor C is equal to the product of the resistance value of the VCR 3O defined by the decay time potential +VDT and the capacitance value of the capacitor C. Capacitor C
discharges from the attack level VAl, toward the initial level VIL with such a discharge time constant. The above-mentioned potential change accompanying the charging and discharging of the capacitor C is taken out via the buffer 16 as an envelope signal Vou. As this envelope signal VOut, the attack time potential +VAT and the decay time potential +VDT are defined as VAT>V
By setting the relationship to be DT, the fourth
Figure V. A waveform similar to that shown in t can be obtained. That is, according to the embodiment shown in FIG. 5, it is possible to obtain a percussive envelope signal as a whole in which the attack level is maintained for a predetermined period.
If the musical tone signal is amplitude-modulated using this signal as in the previous example, a stable sense of attack can be obtained. In addition,
Various modifications can be made to the circuit of FIG. 5.

For example, the output of the one shot circuit 33 may not be used to control the VCR 3O, but may be used to control the control switch 30X connected between the capacitor C and the VCR 3O, as shown by the broken line X. Further, the one-shot circuit 33 may be driven not by the output signal of the comparator 31 but by the attack level detection signal as shown by the broken line Y in the same manner as in the previous example. It is clear that the same effects as described above can be obtained in these modified examples as well. 6th
The figure shows an envelope signal generating circuit according to a third embodiment of the present invention, and the circuit of this example improves the circuit of FIG. This is how it was done.

In the circuit of FIG. 6, the same parts as in FIG. 3 are given the same reference numerals. The circuit of FIG. 6 differs from that of FIG. 3 in that, first, a potential source 34 with a potential +VBL lower than +VAL is provided, and a relatively small resistance value is provided between this potential source 34 and the capacitor C. The resistor R3, the discharge control gate 35, and the backflow prevention diode D4 are connected.Secondly, a NOR gate 36 is provided which inputs the key-on signal KON and the on/off signal from the damper pedal switch DS. , this NOR gate 3
A gate 37 controlled by the output of the gate 3T and a resistor R4 having a relatively small resistance value connected in series with the gate 3T are connected in parallel to the series circuit of the resistor R and the gate 15. Next, with reference to FIG. 7, the characteristic operation of the circuit shown in FIG. 6 will be explained. Since the one-shot circuit 19 operates during the period T1, the output of the AND gate 21 is at a low level during the period T1, so that the gates 15 and 35 are controlled to be off during the period T1. Now, considering the case where the switch DS is turned off without pressing the damper pedal, the output of the NOR gate 36 is "low" because the key-on signal KON is "high" during key-on. Therefore,
The capacitor C charged to +VAL becomes R, during the period T,
Since all discharge paths of ~R4 are cut off, the output V. ut
maintains the attack level of +VAL during the period T.
When the period T1 has elapsed, the output of the AND gate 21 becomes "
"High", and gates 15 and 35 are both turned on.
Therefore, the charge in the capacitor C is the resistor R2 and the resistor R,
It is rapidly discharged through a parallel circuit with a time constant of C(R2/R3). This discharging is stopped when the discharge potential of the capacitor drops to approximately equal to +VBL, and thereafter, gradual discharging is performed via the resistor R with a time constant of CR. At this time, when the key is released, that is, the key is turned off, the output of the NOR gate 36 becomes "high", so the gate 37 is turned on, and the capacitor C becomes C(R2/R4) as shown by the broken line in FIG. A constant discharge will occur quickly. Even when the key is turned off before the discharge potential of the capacitor C reaches +VBL, the capacitor C is quickly discharged in substantially the same manner as in the above case, that is, with a time constant approximately determined by CR4. The above operation is performed when the damper pedal switch DS is in the OFF state without pressing the damper pedal, but if the switch DS is in the ON state with the damper pedal being pressed, it is always NOR.
Since the output of the gate 36 becomes "low", the gate 37 is controlled to be off, and the capacitor C is discharged regardless of whether the key is off.

That is, as shown by the solid line in FIG. 7, initially C(R2
/R3), and then, when the discharge potential of the capacitor C becomes +VBL or less, it is slowly discharged with a time constant of CR2. As a result, a natural damping sound effect similar to the damper effect in a natural musical instrument such as a piano can be obtained. As mentioned above, according to the circuit arrangement shown in FIG.
3) A two-stage decay curve consisting of a first curve corresponding to CR2 and a second curve corresponding to CR2 can be obtained, and the decay curve can be changed to C in synchronization with key-off by turning the damper pedal switch off and on. (R2/R
Adding a third curve for rapid damping corresponding to 4),
Since it is possible to express a so-called damper effect that gradually attenuates with the time constant of CR2 regardless of key-off, it is extremely useful for achieving subtle musical expressions.

FIG. 8 shows an envelope signal generating circuit according to a fourth embodiment of the present invention.

The illustrated circuit partially utilizes the circuit previously shown in FIG. 5, so parts that are the same as those shown in FIG. 5 are given the same reference numerals. The circuit in Figure 8 basically generates a percussive envelope signal, but (1)
(2) the decay curve consists of two curves with different time constants;
(3) If the key is turned off during decay, a decay curve is obtained that rapidly decays. In the circuit of FIG. 8, reference numeral 40 denotes a voltage generator, which includes four variable resistors 42, 43, 44, 45 connected between a potential source 4 of potential +V and the ground potential point.
Contains. The variable resistor 42 has an attack level potential of +V
The variable resistor 43 derives the attack time potential +VAT, the variable resistor 44 derives the first decay time potential +V, DT, and the variable resistor 45 derives the second decay time potential +V2DT from each movable contact. Each of the variable resistors 42 to 45 is mounted on the panel surface of the musical instrument so that they can be operated as appropriate. 50A and 50B are key switches KSl and KS, respectively.
It is an envelope forming section provided corresponding to 2, and voltage level signals +V, +VB from a common voltage generating section 40.
Envelope signal V based on L, +VAT, +VlDT, +V2O gain.

Oll and VOUl2 are respectively formed. Actually, a large number of envelope forming parts corresponding to the number of keys are provided corresponding to each key, but only two, 50A and 50B, are shown in the figure for convenience. As described above, the voltage generating section 40 includes a plurality of envelope forming sections 50A,
According to the configuration of this embodiment, which is commonly connected to 50B,
Since the voltage levels (+V, +VBL, +VlDT, +V2DT, etc.) of all envelope forming parts can be uniformly controlled on the panel surface, there is no control variation between each envelope forming part, and the advantage is that envelope signals with almost the same waveform can be obtained. be.

Next, the envelope forming section 50A will be taken as a representative example of the envelope forming section, and its configuration and operation will be described in detail.

The envelope generation unit 50A generates a negative progressive key-on pulse NKO based on the on-off signal from the key switch KSl.
A first circuit section 50A1 for forming a negative progressive key-on pulse NKON and a voltage level signal (+V, +V
BL, +VAT, +V, DT, +V2DT, etc.) a second circuit section 5 for synthesizing an envelope waveform based on
It consists of 0A2.

First, in the first circuit section 50A1 for forming a negative progressive key-on pulse NKON, 51 is a key switch K.
An R-S flip-flop 52 is a waveform shaping R-S flip-flop which is set at the key-on timing by the key-on signal KON from Sl and reset at the key-off timing by the signal KOFP which is an inversion of the key-on signal KON. 1 one-shot circuit, 53 an AND gate that ANDs the output 0S1 of the first one-shot circuit 52 and the output KON (key-on signal) of the flip-flop 51 to remove key chattering, and 54 a trigger triggered by the output 0S1 of the first one-shot circuit. A second one-shot circuit 55 outputs an output signal V.

V by comparing Utl (envelope signal) and a potential +VBL lower than the attack level VAL. 56 is an AND gate that ANDs the output 0S2 of the second one-shot circuit 54 and the comparison output EQ2;
7 is a differentiation circuit that differentiates the output 0S1 of the first one shot, and 58 is a key-on signal KON from which chattering has been removed.
59 is an 0R gate that 0Rs the differential output 0S1D and the inverted key-on signal KON'; 6
0 is AND output EQ2・0S2 and 0R output 0S1D+K
This is an 0R gate that generates a negative progressive key-on pulse NKON by 0R'ing ON'. Note that the operating time of the first one-shot circuit 52 is determined in consideration of the time required to eliminate key chattering, and the operating time of the second one-shot circuit 54 is determined such that the output signal VO,... exceeds the level of SL. It is set for a certain length of time. Furthermore, the reason why the differentiation circuit 57 is provided is that when the key is repeatedly pressed very quickly, VOut,
> If it is VBL, there is an inconvenience that the flip-flop 73, which will be described later, is not set because NKON goes to a low level and becomes flat, so in order to eliminate this inconvenience, the differential output 0S1D is used to momentarily set NKON to a high level and set the flip-flop 73. This is to make sure that it is set. By the way, the second circuit section 50A for synthesizing the envelope waveform based on the negative progressive key-on pulse NKON
2, 61, 62, and 63 are attack level potential +VA first reference potential V, and second reference potential V, respectively.
3, with gates 64, 65, and
66.

67 is a gate for supplying the potential +V to one input terminal of the adder 68 in response to the inverted key-on signal KON', and the second decay time potential +V2DT is applied to the other input terminal of the adder 68. ing.

70, 71, and 72 are gates for transmitting the control voltages CV, , CV, , CV, respectively, to the control input terminal of the VCR 3O via the resistor Ra.

The control voltage CV, consists of the attack time potential +VAT, and the control voltage CV2 consists of the first decay time potential +VlDT.
The FhI voltage CV3 is the summed output of the adder 68. The gates 64 and 70 are controlled on and off according to the control signal SCl, the gates 65 and 71 are controlled on and off according to the control signal SC2, and the gates 66 and 72 are controlled on and off according to the control signal SC3. Among these leg signals SCl to SC3, SC3 is composed of the aforementioned negative progressive key-on pulse NKON, while SCl and SC2 are composed of the R-S-T flip-flop 7.
3. It is formed of a logic circuit including an inverter 74 and AND gates 75 and 76. A flip-flop 73 converts the key-on pulse NKON to a differentiating circuit 11 and a diode D.
The attack level detection signal EQl from the comparator 17 is reset by the signal converted into a falling differential pulse in step 1.
It is triggered by AND gates 75 and 76 have input connections indicated by circles M;
generates a control signal SCl which becomes "high" when the output Q of flip-flop 73 and the output of inverter 74 are both "high". Further, the AND gate 76 generates a control signal SC2 which becomes "high" when both the output Q of the flip-flop 73 and the output of the inverter 74 are "high". In addition, in the above circuit, reference numerals 11 and 16
,17,18,30,31,32,33,D1,D2,
The parts marked D3 and C are the same as those shown in the above-mentioned embodiment, so the explanation will be omitted.
Comparator 31 has reference voltage V.

gaV, kuV. It is set to have a relationship such as VAL and VAL, and is designed to detect a voltage change from VAL to V at one end of the VCR3O. Also, V
, may not be V, -V, as long as VBL>V. When V,=V, one of the gates 65 and 66 is omitted, and the remaining gate is connected to the control signal S.
It is also possible to control C2 and SC3 with a signal that is 0R. Next, an example of the operation of the circuit shown in FIG. 8 will be described with reference to FIG. 9.

In FIG. 9p, an envelope signal V is represented by a curve A. Utl is obtained when the key is turned off after the end of attenuation, and is expressed by the force curve B and the envelope signal V. Ull is obtained when the key is turned off during decay. The operation in each case will be described in turn. First, when the key is turned on at time T and the key is turned off at time T2 to obtain an envelope signal expressed by curve A, the operation is as follows.

That is, at time t1, when the output KON (FIG. 9a) of the flip-flop 51 changes from "low" to "high",
The first one-shot circuit 52 is triggered to output pulse 0.
S1, σ101 (Fig. 9B, c) is generated. Along with this, the second one-shot circuit 5 triggered by the pulse σI]
4 generates an output pulse 0S2 (FIG. 9 d) at time Tll, and an AND gate 53 to which the key-on signal KON and pulse 0S1 are input also generates a chittering-free key-on signal KON' (FIG. 9 f) at time T1. ) occurs. The key-on signal KON' is converted into an inverted signal EMOEV (Fig. 9g) by the inverter 58, and then supplied to the 0R gate 59', where the pulse 0S1
The signal 0S1D (FIG. 9e) obtained by differentiating the signal 0S1D with the differentiating circuit 57 is subjected to an 0R operation. 0R calculation output at this time 0S1D+W
The .sigma.ma (FIG. 9j) is generated in such a manner that it changes from "high" to "low" at the time Tll when the operation of the one-shot circuit 52 ends. On the other hand, the output 0S2 of the second one-shot circuit 54 is
Output EQ2 of comparator 55 (Fig. 9h) and AND gate 5
However, at time Tll, the comparison output EQ2 is "high" and the one shot output 0S2 changes from "high" to "low", so the AND output EQ2・0S2( 1) changes from "high" to "low" at time Tll.

Therefore, 0R output 0S1D+Yσma and AND output EQ2
・The signal NKON (k in FIG. 9) obtained as a result of 0Ring 0S2 with the 0R gate 60 becomes [high] at times T and l.
It will change from ``low'' to ``low''. Therefore, time Tl
, the control signal SC3 (n in FIG. 9) was "high" and the gates 66 and 72 were on, but at time Tl,
Then, the flip-flop 73 receives the negative progressive key-on pulse N.
Since it is set in synchronization with the falling edge of KON, AND
The AND condition of the gate 75 is satisfied, the control signal SCl (FIG. 9 1) changes from "low" to "high", and the gates 64, 70
will turn on. Therefore, capacitor C is V
It is charged with a voltage of VAL+ΔV via CR3O, and its terminal voltage rises from the ground potential (3).

The charging time constant at this time is attack time potential +VAT
It is determined by the product of the resistance value of the VCR3O and the capacitance value of the capacitor C according to the control voltage CV, and the rising change in the charging potential of the capacitor C taken out via the buffer 16 is the curve shown in FIG. It becomes as shown in AT. Capacitor C
When the charging potential of increases and becomes almost equal to the potential VBL,
At this time Tl2, the two inputs of the comparator 55 match, so the output EQ2 changes from "high" to "low". This change does not bring about any change in the AND output, and thus in the key-on pulse NKON, since the AND output EQ2.m has already been "low" from the time of Tll. Next, when the charging potential of the capacitor C further increases and becomes almost equal to +VAL, at this time Tl3, the comparator 1
Since the two inputs of 7 match, the match signal EQl (Fig. 90
) is generated from the comparator 17. Coincidence signal Q1 triggers flip-flop 73 and inverts its output state, so outputs Q and Q become "high" and "low", respectively. Therefore, the AND condition of the AND gate 75 is not satisfied, and the AND condition of the AND gate 75 is not satisfied.
Since the AND condition of D gate 76 is satisfied,
The control signal SCl changes from "high" to "low", and the control signal SC2
(Fig. 9 m) changes from "low" to "high".
As a result, gates 64 and 70 are turned off, and gate 65
, 71 are turned on, but the capacitor C does not immediately start discharging toward the V2 (ground potential) level. That is, at time Tl3, the potential at one end of VCR3O is +
The voltage changes from AL to V, and the voltage change at this time is detected by the comparator 31. The output level of the comparator 31 changes from "high" to "low" at time Tl3, and the output signal at this time is converted into a falling differential pulse via the differentiating circuit 32 and diode D3. Trigger the one shot circuit 33. The operating time of the one-shot circuit 33 is set to be equal to a minute period T1 corresponding to one to several waves of the modulated signal by adjusting the variable resistor 33a. A negative-going pulse output having a pulse width corresponding to , is generated and applied as a control voltage to the VCR 3O via the resistor Rb. Therefore, CR3O is controlled to have an extremely high resistance value during period T1, preventing capacitor C from discharging even though gate 65 is on. Therefore, the terminal voltage of the capacitor C, and thus the output signal VOut, is at the attack level +V during the period T1.
AL will be maintained. When the operation of the one-shot circuit 33 is completed, the VCR3O is connected to the gate 71 and the resistor R.
The capacitor C has a resistance value that corresponds to the control voltage CV2 supplied via a, that is, the first decay time potential +VlDT, and the capacitor C has a resistance value that corresponds to the VCR.
Discharge via 3O.

The discharge time constant at this time is equal to the product of the resistance value corresponding to the relatively high potential +V, DT and the capacitance value of the capacitor C, and the attenuation (discharge) curve is as shown in 1DT in Figure 9 p. Become. The terminal voltage of capacitor C drops and the potential +
When it becomes equal to VBL, at this time Tl4, the comparator 5
The two inputs of 5 match, and the output EQ2 changes from "low" to "high".

For this reason, AND output EQ2・0S2 and 0R output NK
ON changes from "low" to "high", and the control signal S
C2 changes from "high" to "low", and control signal SC3 changes from "low" to "high". That is, at time T, 4, gates 65 and 71 are turned off, and gates 66 and 72 are turned off.
is turned on, and the discharge time constant is switched. At this time, the control voltage CV, applied to the VCR3O, is during key-on and the signal KON' is "low", so the gate 67 is off. 2nd Deike time potential +V2D
T (generally, V2DT minus NlDT). Therefore,
After time Tl4, the capacitor C is discharged according to a time constant determined by the product of the resistance value corresponding to the relatively low potential +V, DT and the capacitance value of the capacitor C. The attenuation (discharge) curve at this time is as shown in 2DT in FIG. 9p. After the capacitor C is discharged to the V (ground potential) level, a key-off operation is performed at time T2, and the signals KON, KON', KON', and 0S1D+kσ change their levels as shown in FIG. 9. .

According to FIG. 9, the negative progressive key-on pulse NKON
It can be seen that is generated independently of the key-off timing T. However, as a special case, if you repeatedly press the key so that the key is turned on again before the key-on pulse NKON returns from "low" to "high," the key-on pulse NKON will change after the first key-off.
The second key-on instantly raises the level to a high level. In this case, for example, if a second key-on occurs during attenuation according to curve 1DT, the pulse of differential output 0S1D momentarily makes the key-on pulser KO lower "high", and at the falling edge at that time, Flip-flop 73 is reset, thereby recharging with voltage VAL+.DELTA.v and subsequent sequence operation. As a result, Figure 9 p
An envelope waveform corresponding to the second key-on as shown by the broken line A' is obtained. Next, the operation of key-on at time T and key-off at time T4 in order to obtain an envelope signal expressed by curve B will be described.

In this case, the period from T, to T4 is
3l, t32, t33, t, and 4, the same operation as at each of the above-mentioned time points Tll, tl, tl3, and tl4 is performed, and a charging/discharging power curve similar to the above-mentioned curve A is obtained. However, after time T4, the inverted key-on signal KON' changes from "low" to "high";
The gate 67 is turned on, and the adder 68 receives the potential source 4.
1, the potential +V is supplied. For this reason, the control voltage CV
3 is the sum of the second decay time potential +V2DT and the potential +V, and the resistance value of the VCR3O is relatively small corresponding to the sum potential. Therefore, after time T4, capacitor C is discharged quickly with a relatively small time constant, and an attenuation (discharge) curve as shown at 2DT' in FIG. 9p is obtained. As described above, according to the embodiment of FIG. 8, the envelope signal V is suitable for simulating a piano sound, as shown in FIG. 9 p(7)A and B.

You can get Utl. In the above explanation, the envelope signal generation circuit (in the case of Figures 3, 5, and 6) or the envelope forming section (in the case of Figure 8) is provided for each key, but the actual number of keys is A number less than (
In the case of an electronic musical instrument having 10 or less musical tone forming channels, such an envelope signal generating circuit or envelope forming section can be provided for each musical tone forming channel.

The operating time T1 of the one-shot circuits 19 and 33 is determined as appropriate depending on the frequency of the input musical tone signal (modulated signal) as described above, but the operating time T1 of the one-shot circuits 19 and 33 is determined as appropriate depending on the frequency of the input musical tone signal (modulated signal). In an electronic musical instrument provided with an envelope signal generating circuit or an envelope forming section for each tone forming channel, an operating time T1 is set for each key corresponding to its frequency. It is preferable to variably control the operating time T according to the key voltage, key code signal, etc.).

Furthermore, in electronic musical instruments that use a touch sensor to detect keystroke speed or strength, etc., the attack level (VAL), attack time (VAT), and one-shot operation time (T1) are determined according to the output signal of the touch sensor.
) etc. may be controlled.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional amplitude envelope addition circuit, Figure 2 is a signal waveform diagram for explaining the operation of the circuit in Figure 1, and Figures 3 to 11 are all This is for explaining an embodiment of the present invention, and FIGS. 3, 5, 6, and 8 are circuit diagrams of envelope signal generation circuits, and FIGS. 4, 7, and 9 are signal waveforms. It is a diagram. 12...R-S flip-flop, 13,15
...Gate, 16...Batsuhua, 17
......Comparator, 19,33...One-shot circuit, R,, R2, 3O...Resistor for determining time constant, C...Charging/discharging capacitor .

Claims (1)

[Claims] 1. In an envelope signal generation circuit that generates a percussive envelope signal that rises from an initial level to a predetermined attack level in synchronization with the key-on timing and then decays to the initial level by utilizing charging and discharging of a capacitor. first circuit means for generating a pulse having a duration of , the duration of which starts corresponding to the timing of reaching the attack level and ends independently of the key-off timing; and the duration of the pulse. second circuit means for controlling the charging or discharging of said capacitor to maintain said attack level during said pulse duration and for controlling said capacitor's discharging or charging to decay from said attack level to said initial level after the end of said pulse duration; and third circuit means for controlling the envelope signal, and the duration of the pulse is set to be longer than one period of a modulated signal whose amplitude is modulated by the envelope signal.