JPS593000B2 - Data protection circuit in semiconductor memory devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data protection circuit that prevents the memory contents from being destroyed when power is turned on and off in a semiconductor memory device using a semiconductor memory device, particularly a non-volatile semiconductor C-type memory device. be.

A case will be described below in which an N-channel insulated gate field effect transistor with a floating gate structure is used as a nonvolatile semiconductor memory element. 5 First, to explain this nonvolatile semiconductor memory element (hereinafter referred to as a memory element), this memory element stores information by changing its threshold voltage vt to two different values by the method described later. The stored information is read out by identifying the different threshold voltages vt using an appropriate method.

FIG. T is a symbolic diagram schematically showing the structure of such a memory element. 1 is the control gate, ? 2 is a floating gate, 73 is a source, and 15T4 is a drain. The potential of the source T3 or drain T4 of this memory element is set to the silicon substrate potential Vss level,
Moreover, when a voltage of about 25 to 30 V is applied to the control gate Ti over several layers, the vt of this memory element becomes a large positive value! 0, the memory element becomes an enhancement type. Also, set the control gate Ti to Vss level,
While either the source 73 or the drain 74 is left open, a voltage of approximately 25 to 30 V is applied to the other for several hundred tons.
When ts is applied, vt of this memory element has a negative value of '5' and has a large absolute value, and the memory element becomes a depletion type. The former case is called data writing, and the latter case is called data erasing. Note that the value of vt of an enhancement type or depletion type memory element depends on the magnitude of the applied voltage, the pulse width, the area ratio of the control gate 71 and the floating gate 12, the thickness of the insulating film, and the specific resistance of the silicon substrate. The value is further determined by the conditions of the manufacturing process. Data is stored by changing the vt of the memory element5 in this way, but this changed vt value remains unchanged even when all power is turned off, that is, it has a non-volatile function. ing.

Now, as mentioned above, in order to cause the data writing or erasing action and to rewrite the stored contents, a power supply for applying a voltage of about 25 to 30 V is required.

On the other hand, peripheral circuits such as address drivers, decoders, and input/output circuits that control the operation of such memory elements do not require such high voltages as mentioned above, but instead use ordinary N-channel enhancement/depletion voltages such as +5V or +10V.
A power supply for OSIC etc. is sufficient, and if 25 to 30
If a power supply of about V is used, there are problems such as increased power consumption, the necessity of channel cutting, and the risk of dielectric breakdown of the transistors used. For this reason, a nonvolatile semiconductor memory device (hereinafter referred to as a memory device) using the above-mentioned memory element has a first power supply of about 25 to 30V for writing and erasing data, and a power supply of at most 15V for peripheral circuits. Generally, the device is equipped with a second power source of about 100 kHz. In such a memory device, there is no problem if the first power source is turned on after the second power source is turned on, and the second power source is turned off after the first power source is turned off. Conversely, if the first power source is turned on before the second power source is turned on, or if the second power source is turned off before the first power source is turned off, writing/erasing is controlled. The circuit malfunctions and the control gate 71 of the memory element
Alternatively, a voltage that causes writing or erasing to be applied to the source 73 or the drain 74 may change the stored data, that is, data may be destroyed. As described above, the present invention detects when the second power supply is at a low value exceeding the allowable range while the first power supply is in the on state, and prohibits writing/erasing. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is intended to provide a data protection circuit for a memory device that prevents data destruction, and the present invention will be described in detail below with reference to drawings showing embodiments thereof. FIG. 1 shows one embodiment of a protection circuit according to the present invention.

In the figure, T,l, Tl2, T,3, and Tl4 are enhancement-type transistors, and the drain and gate of Tl2 are normally connected to the second transistor at a relatively low voltage VDD.
The source is connected to the gate and drain of T, l and the gate of Tl3, and the source of Tll is at the potential V8S of the silicon substrate, and the voltage is divided by the transistors Tll and Tl2. Circuit section 1
0a is configured. The drain and gate of T1 are normally connected to a first power supply with a relatively high voltage Vgg, and its source is connected to the drain of T13, and the source of T1 is connected to the silicon substrate potential V88. The transistors Tl3 and Tl4 constitute a control circuit section 10b. And this control circuit section 1
An output terminal is provided at the drain of the transistor Tl3 or the source of the transistor Tl4 of 0b, and the control voltage C
v is output. Note that β11, β12,
β13 and β14 are transistors Tll? Tl2woT
l3? This is the gain factor of Tl4. MT is a memory element and constitutes a part of a memory device, and its control gate and drain are connected to a control gate line GL on which a voltage for writing is to be carried and a drain line on which a voltage for erasing is to be carried, respectively. DL is connected (・ru.

Tl5 and Tl6 are transistors constituting the write/erase control section 10c of the circuit of the present invention, and the gates of both transistors Tl5 and Tl6 are connected to the transistor Tl6.
The drain of transistor T3 or the source of transistor Tl4 are connected to input the control voltage Cv, and the potential of the sources of both transistors Tl5 and Tl6 is set to Vss. Furthermore, the drains of the transistors Tl5 and Tl6 are connected to the control gate line GL and drain line DL, respectively. Thus, the zeta protection circuit according to the present invention as described above uses the voltage V of the second power supply.

The voltage D is divided by the transistors T1 and Tl2 of the voltage dividing circuit section 10a, and the divided voltage V1 is applied from the drain of T, or the source of Tl2 to the transistor Tl of the control circuit section 10b.
It is input to gate 3. That is, the control circuit section 10b
is an inverter made up of transistors Tl3 and Tl4, and the voltage V1 is input to the inverter.
If the ratio between gain factors β11 and β12 and the ratio between gain factors β13 and β14 are set to appropriate values, the voltage Vgg of the first power supply and the voltage Vgg of the second power supply
. When O are both at the normal operating voltage or within a certain tolerance range, the output voltage V1 of the voltage divider circuit section 10a is at a high level corresponding to the voltage value of the second power supply, so Tl3 becomes conductive and the control circuit section The output voltage of 10b, that is, the control voltage C
v becomes a low level close to Vss. On the other hand, while the voltage Vgg of the first power supply is a normal operating voltage or within a certain tolerance range, the voltage V of the second power supply. When D is at a low value exceeding the allowable range, such as zero, the voltage dividing circuit section 10a
Since the output voltage 1 is at a low level corresponding to the current voltage value of the second power supply, Tl3 becomes non-conductive and the control voltage Cv becomes a high level. Now, as mentioned above, the voltage V of the second power supply. When O is at the normal operating voltage or within the tolerance range, the control voltage C is at a low level and the transistors Tl5,
T, 6 becomes non-conductive, and a voltage for writing and a voltage for erasing can be applied to the memory element MT via the control gate line GL and drain line DL, respectively. On the other hand, when the power is turned on, the second
When the first power source is turned on before the first power source is turned on, or when the second power source is cut off before the first power source is turned off when the power is cut off, etc., the first power source is in the on state and the normal If the voltage of the second power supply is at a low level exceeding the allowable range even though the voltage is at a voltage of , Tl6 are rendered conductive, and application of voltage to the memory element MT via the control gate line GL and drain line DL to the memory element MT is prevented. That is, even if a voltage signal is applied to the control gate line GL and drain line DL for some reason in such a case, it will not be applied to the memory element MT, and data can be protected. Second
3 and 3 show voltage dividing circuit sections 10a2 and 10a3, respectively.
Another embodiment of the circuit of the present invention constructed using transistors is shown with the write/erase control section omitted.

The one in Figure 2 is an enhancement type transistor,
Further, the structure shown in FIG. 3 uses a depletion type transistor, and both have the same effect as the structure shown in FIG. FIG. 4 shows another embodiment of the present invention used in a memory device in which the second power supply has two voltages, one with voltage DD4l and one with voltage VDO42, with the write/erase control unit omitted. This is what is shown.

In this case, one voltage dividing circuit section 10a41, 10a42 is provided for each of the two second power supplies, and a two-input NAND gate is used as the control circuit section 10b4. Then, the voltage V4l obtained by dividing the voltage VDD4l by the voltage dividing circuit part 10a41 and the voltage dividing circuit part 10a42
The voltage V42 obtained by dividing the voltage VDD42 is used as an input signal to the NAND gate serving as the control circuit section 10b4. In this circuit, when the first power supply is in the on state and the voltage Vgg is at the normal operating voltage, the voltage VOD4l and/or VDD42 of the second power supply becomes an unacceptably low level. V4l and /
Or, since V42 becomes a low level, the control circuit section 10b4
The control voltage C, which is the output of the control voltage C, becomes high level and inhibits writing and erasing to the memory element as in the case of FIG. Furthermore, in the embodiment shown in FIG.
However, as shown in FIG. 5 or 6, the level of the write voltage W applied to the control gate of the memory element or the erase voltage E applied to the drain or source of the memory element It may also be configured to indirectly reduce the

That is, in FIG. 5, W/EG is a write voltage/erase voltage generation circuit, and its output is connected to a control gate line, a drain line, etc. via a transistor T52 whose gate receives a control pulse CP. . The write/erase control unit 10C5, which is a part of the circuit of the present invention, is composed of one transistor T, l whose drain is connected to the output terminal of W/EG and whose source is Vss, and a control voltage C is applied to its gate. That's what I do. In the case of such a configuration, when both the first power supply and the second power supply are at the normal operating voltage, the control voltage Cv is at a low level, so T5l becomes non-conductive, and writing is performed by applying a control pulse CP to T52. The programming voltage w or erasing voltage E is extracted to perform writing and erasing on the memory element, whereas when the second power supply is at a low level exceeding the tolerance range, the control voltage C is at a high level, so T5l
becomes conductive, and even if an erroneous signal similar to a control pulse is input to T52, the write voltage w or the erase voltage E will not be cut out, and unnecessary writing to the memory element will occur. No erasure occurs. Next, in FIG. 6, W/EGC indicates a control circuit for creating a write voltage/erase voltage, and its output, a control pulse, connects the drain to the first power supply V? The control voltage Cv is input to the gate of the transistor T62 connected to the gate of the transistor T62 and the drain of the transistor T6l constituting the write/erase control section 10C6, which is the = section of the circuit of the present invention. input, and its source is set to be V88.

Therefore, in the case of such a configuration, when both the first power source and the second power source are at the normal operating voltage, the control voltage Cv
Since T6l is at a low level, T6l becomes non-conductive, and by inputting a control pulse to the gate of transistor T62, the write voltage w or erase voltage E for a predetermined time width is output from the source of T62. On the other hand, when the second power supply is at an unacceptably low level, the control voltage C
Since v is at a high level, T6l is conductive, and an erroneous signal similar to a control pulse is not applied to the gate of T62, so the write voltage w and erase voltage E are not output from the source of T62, causing unnecessary interference to the memory element. No writing or erasing is performed. As described in detail above, the present invention provides an advantage in that the voltage of the power supply for writing and erasing data in a memory element is high enough to cause writing and erasing, while the voltage of the power supply for the circuit that controls writing and erasing is high enough to cause writing and erasing. To prevent unintentional writing/erasing due to malfunction and causing changes in the memory contents of the memory device when the level is lower than the allowable range, and in particular,
Since the storage contents are prevented from being destroyed when the power is turned on and off, there is no need to consider the order in which multiple power sources are turned on and off, and there is a practical benefit in improving the reliability of the nonvolatile semiconductor memory device.

In the above explanation, a case has been described in which an N-channel insulated gate field effect transistor with a floating gate structure is used as a non-volatile semiconductor memory element, but the present invention is not limited to N-channel, but can also be applied to P-channel insulated field effect transistors. Needless to say, the present invention can also be applied to a case where a gate type field effect transistor is used.

However, in the case of the P channel, a power source with a polarity opposite to that used in the case of the N channel, that is, a negative polarity must be used.

[Brief explanation of drawings]

The drawings show embodiments of the present invention, and FIG. 1 is a circuit diagram of a zeta protection circuit according to the present invention, FIG. 2, FIG.
FIG. 4 is a circuit diagram showing another embodiment of the present invention with the write/erase control unit omitted, and FIGS. 5 and 6 are the write/erase control units in other embodiments of the circuit of the present invention. FIG. 7 is a symbol diagram of a memory element. Tll? Tl2fu Tl3? Tl4? Tl5ヲTl6゛゛゛''Transistor, MT---Memory element, 10
a... Voltage divider circuit section, 10b... Control circuit section, 10c... Write/erase control section.

Claims (1)

[Claims] 1 A first power source that uses a semiconductor memory element and is used to change the threshold voltage of the semiconductor memory element in order to write and erase data in each semiconductor memory element, and a first power supply that controls the operation of each semiconductor memory element. In a semiconductor memory device comprising a second power supply for power supply, when the voltage divider circuit outputs a voltage corresponding to the voltage of the second power supply and the first power supply are in an on state. and a control circuit section that outputs a control voltage of a low level or a high level in response to when the output voltage of the voltage divider circuit section changes to a higher level or a lower level than a predetermined level, respectively, 1. A data protection circuit for a semiconductor memory device, characterized in that the first power supply is configured to inhibit writing or erasing of data in each semiconductor memory element when the voltage reaches a high level.