JPS592995B2 - decoder warmer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to PLA (programmable logic array) and ROM (read memory) in MOS type semiconductor integrated circuits.
It is concerned with improving the performance of decoder circuits, which are one of the components of RAM (Random Access Memory) and RAM (Random Access Memory).

Hereinafter, the present invention will be explained based on examples.

FIGS. 1a and 1b show a first embodiment of a decoder circuit according to the invention. In Figure 1a, 1 to 7 are MO
S-FET (insulated gate field effect transistor), A
o, Al, A2....... is address input, C
1 is a bootstrap capacitor 10, and 20 is a high voltage generation circuit. The operation of FIG. 1a will be explained with reference to FIG. 1b5. Now enter address A. , Al, A2...
Assume that the voltage of * is OV and MOS-FETs 2, 3, and 4 are in the off state. A terminal A connected to the gate of the MOS-FET 1 is connected to the clock φA via the high voltage generation circuit 10. Here, the high voltage 10 generating circuit 10 has an output voltage of terminal A such that φA
= When it is VDD, it is 0V, and when φA is 0V, it is about 2XVD.
This is a circuit device that determines the voltage at terminal A so that it becomes D. As a result of the voltage at terminal A becoming approximately 2×VDD, the voltage at terminal B becomes 1
The maximum voltage value of the output signal 5 rises to VDD, as shown in 3 of FIG. 1, and the signal response is faster than ι. On the other hand, terminal D is connected to terminal B via a transfer gate of MOS-FET 5, and the gate of MOS-FET 5 is connected to clock φA and a high voltage zero generation circuit 20. Here, the high voltage generating circuit 20 has a voltage at its output terminal C as shown in 4 in FIG. 1b, φA
-VDD, VDD-Vth (vth is MOS-FE
(represents the threshold voltage of T5), vDD when φA=0V
This is a circuit device that determines the voltage at terminal C so that +vth and 1'5. As a result, the voltage at terminal D is VDD
(Fig. 1b, 5), and MOS-FET6, 7
When the clock φx is applied to the driver circuit composed of the bootstrap capacitor Cl and the bootstrap capacitor Cl,
'O tsup effect is further enhanced to produce a faster output signal waveform (
Figure 1 b, T) can be obtained. Increase the voltage of the output signal of terminal B mentioned above to VDD, and apply it to the gate of MOS-FET5, whether it is a transfer gate or
A feature of the present invention is that the voltage of the output signal at the terminal D is increased to VDD by applying a voltage 35 h.

In other words, the voltage at terminal D will rise to VDD! 51, the bootstrap effect of the driver circuit connected to the terminal D becomes higher, and as a result, a high-speed decoder output signal can be obtained.

As described above, according to the present invention, a high-speed decoder circuit can be provided, and PLA. The operational performance of semiconductor integrated circuits such as ROM or RAM can be improved. FIG. 2 shows an embodiment in which the high voltage generating circuit 10 of the embodiment shown in FIG. 1 is further embodied.

In Fig. 2, 12 to 15 are MOS-FETs, CBL
is a bootstrap capacitance, CO1 is a parasitic capacitance, and 11 is a delay circuit. As shown at 1 and 2 in Fig. 1b, φA-
In order for the voltage at terminal A to be ]2・VDD at 0V,
It is desirable to increase CBl/COl as much as possible. Further, the delay circuit 11 is a circuit for effectively increasing the bootstrap effect by raising the voltage at the terminal A to ]VDD in advance when φ is switched from VDD to 0V. FIG. 3 shows an embodiment in which the high voltage generating circuit 20 of the embodiment shown in FIG. 1 is further embodied.

In Figure 2, 21 to 23 are MOS-FETs, CB2
is the bootstrap capacitance, and CO2 is the parasitic capacitance. Now, the threshold voltages of MOS-FETs 5 to 7 and 21 to 23 are assumed to be Vth. When φ1-VOO, the voltage at terminal C becomes DD-Th, and when φA-0, CB2×VOD/(
When the values of CB2 and CO2 are determined so as to approximately satisfy the relationship: CB2+CO2)=2×Vth, the voltage at terminal C becomes DD+Vth (FIG. 1B, 4).

As the MOS-FET in the above embodiments, either a p-channel MOS-FET, an n-channel MOS-FET, or a combination thereof can be used.

Further, as the FET, a shotgun type FET can be used, and it can also be used in combination with a p-channel or n-channel MOS-FET. Furthermore, the substrate may be an insulating substrate such as sapphire.

[Brief explanation of the drawing]

FIGS. 1 to 3 are diagrams illustrating embodiments of the present invention.

Claims (1)

[Claims] 1 comprises a gate circuit to which a plurality of address input lines are connected, and a drive circuit connected to the output line of the gate circuit via a transfer gate, the maximum value of the output signal of the output line of the gate circuit is A decoder characterized in that the value of the power supply voltage V_D_D is the value, and the maximum voltage value applied to the gate terminal of the transfer gate is the sum of the threshold voltage Vth of the transfer gate and the power supply voltage V_D_D. circuit.