JPS5929836B2 - electronic clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electronic watches, and particularly to time adjustment for electronic watches.

Conventionally, the time adjustment method for electronic watches has been able to adjust the time only to an error of ±30 seconds from the hour.

For example, if the time to be set is 8:00 minutes OO seconds, the time will be set to 8:00 minutes 00 seconds only when the display time is between 8:00 minutes and 29 seconds, and when it is between 7:59 minutes and 30 seconds. was possible.

In this type of system, when the display time is 8:00:30-59 seconds, it becomes 8:01:00 at the same time as the time setting operation, and when the display time is between 7:59:00-29 seconds, it is the same. The disadvantage is that the time can only be adjusted within a very limited range of time, such as 7:59:00 seconds.

SUMMARY OF THE INVENTION An object of the present invention is to provide a time adjustment circuit for an electronic timepiece that is capable of adjusting the time even when the error from the correct time is larger than before.

The electronic watch of the present invention detects, for example, 59 minutes Y seconds (0xY≦59) or 00 minutes Y seconds in the time display, and when the time adjustment switch is pressed on the hour in either of these states. generating a control signal, which control signal causes I
Sunagawa's sexagesimal counter that counts the Hz signal is reset to 00 seconds, and especially when it is 59 minutes Y seconds, the above 6
The output of the 0-decimal counter in the next stage is caused to count only one minute-use sexagenary counter, that is, it is triggered in 1-digit only to obtain 00 minutes, and the next stage's hour-use 12-decimal counter is triggered only in 1-digit number. This is to correct the time to 00 minutes 00 seconds on the hour.

That is, according to the electronic watch of the present invention, when the time display on the watch body shows 59 minutes Y seconds, the provided time adjustment switch should be operated together with the hour signal of +1 o'clock OO minutes OO seconds. , the time circuit block, ie, the 12-decimal counter in the electronic clock, carries up the hour, and resets the minute circuit block, ie, the sexagesimal counter, and the second circuit block, ie, the sexagesimal counter, to 00 minutes.
0 seconds, the watch body immediately begins to move and is set to the hour with great accuracy.

Also, when the time display on the watch body shows the hour 00 minutes Y seconds, by operating the switch together with the hour signal of 00 minutes 00 seconds, the Y seconds will be set to 00 seconds and the circuit blocks for hours, minutes, and seconds will be activated. At 00 minutes 00 seconds, the watch body immediately begins to move and the time is set extremely accurately.

In either case, deviations of up to ±1 minute from the hour X:00:00 (Y is ±60 seconds) can be corrected with a one-touch operation.

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 is a diagram showing a time display segment, and FIG. 2 is a block diagram showing an embodiment of the present invention.
Segment of 1 unit weight in minute display b3゜d3. e3. AND circuit 1 which receives each display output of f3 as input, and 10 which displays minutes.
There is an inverting circuit 2 which inputs the display output of the segment b2 of the position, and an AND circuit 11 which gates each output of the AND circuit 1 and the inverting circuit 2. The device is configured so that the detection output is generated when the displayed minute state is 59 minutes.

Also, an AND circuit 3 inputting each display output of the segment t32g3 of the minute display and the segment of the 10th segment of the minute display e2. AND circuit 4 whose input is the display output of F2
There is an AND circuit 12 which gates the outputs of these AND circuits 3 and 4, and the output of this AND circuit 12 is such that a detection output is generated when the minute state of the clock's time display is 00 minutes. It is configured.

Further, when the time adjustment switch 13 is closed, the point 14 changes from a low level to a high level.

The signal is input to the AND circuit 17, but this circuit 1
A delay circuit 15 having a delay time τ (SEC) is inserted between the other input of circuit 7 and point 14, and the outputs of AND circuits 11 and 12 are input to the other input of circuit 17. Since the output of the OR circuit 16 is input, the output of the circuit 16 is at a high level, and a single pulse with a pulse width of τ(SEC) is generated at the output of the listening circuit 17.

As mentioned above, gate 11 represents the state at hour 59 minutes Y seconds, and gate 12 represents the state at hour 00 minutes Y seconds, both of which are normally in a low level state. , K hours 59 minutes Y seconds, the gate 11 changes from a low level to a high level, and when K hours 00 minutes Y seconds, the gate 12 changes from a low level to a high level.

Therefore, when one of the gates 11 or 12 is at a high level, that is, when the clock indicates either hour 59 minutes Y seconds or hour 00 minutes Y seconds, closing switch 13 will cause gate 1-1. 17, a single pulse with a pulse width τ is generated as described above, and the sexagesimal seconds counter 19 is reset, so that Y seconds become 00 seconds.

Here, when the output of the gate 11 is at a high level, the AND circuit 20 that ant gates the output of the gate 11 and the output of the gate 17 is opened, so the one pulse that is the output of the gate 17 is also guided to the OR gate 21. Hexadecimal counter 2
2 for only 1 minute.

Since the output of gate 11 is at a high level, it means that the time is 59 minutes and Y seconds on the clock display, so the minute sexagesimal count is 22.
is immediately reset to 00 minutes by the 1 minute trigger, and at the same time the 1 hour trigger hits the hour decimal counter 23 from 22.
As soon as you close it, it becomes +1:00 minutes OO seconds.

Further, as described above, when the time display indicates hours 00 minutes Y seconds, the display immediately changes to hours 00 minutes 00 seconds when the switch 13 is closed.

Further, FIG. 3 shows another embodiment of the present invention, in which Nant gates 32 and 3 are used to form one pulse.
3 R-S flip-flops are used.

A frequency having a pulse width τ (SEC) is always inserted into the gate power 31 of the gate 33.

When the clock display shows either hour 59 minutes Y seconds or hour 00 minutes Y seconds, the output of the gate 16 is at a high level, so the switch 13 is closed and the threshold 14 changes from a low level to a high level. A short pulse is obtained by the delay circuit 15 and the impark and AND circuit 17.

The NAND circuit 30 which receives this short pulse and the gate 16 as input becomes a low level.

Therefore, although the output of the gate 33 is always at a high level, a single pulse with a pulse width τ is generated as shown in the time chart of FIG. 4, and the second sexagesimal counter 19 and the minute sexagesimal counter 22 are reset. OO min 00
seconds.

And when the clock shows 59 minutes Y seconds, game -1
Since the output of -1'l becomes a high level, the gate 34 opens, so the one pulse generated at 33 passes through 34 to the gate 35.
This also triggers the time decimal counter 23 for one hour, resulting in +1:00:00 seconds.

FIG. 5 shows a block diagram of another embodiment of the invention.

In the figure, gate 12 and gate 16 in FIG.
The gate 11 is configured as a two-man gate that produces one pulse as shown in FIG.

And the hour, minute, and second status of the clock body is hour 00 minutes Y seconds.
K hour 1 minute Y seconds, K hour 2 minutes Y seconds...K hour 10 minutes Y
seconds, K hours 11 minutes Y seconds...K hours 20 minutes Y seconds, K hours 21 minutes Y seconds...K hours 51 minutes Y seconds...K
Hour 57 minutes Y seconds, K hours 58 minutes Y seconds, that is, hour 59
If you close the switch 13 when the time is other than minutes and seconds, the values will change to hour 00 minutes 00 seconds, K hour 1 minute 00 seconds, K hour 2 minutes 00 seconds, K hour 10 minutes 00 seconds, K hour, etc. 11 minutes 00 seconds,
・・・・・・K time 20 minutes 00 seconds, K time 21 minutes 00 seconds,・
. . . K hour 51 minutes 00 seconds, .

The case of K hours 59 minutes Y seconds is the same as above.

As an example, in the case of an all-electronic watch, the accuracy is ±0.2 seconds per day, approximately ±5 seconds per month, ±30 seconds per half year, and approximately ±1 minute per year. However, if the time correction circuit of the present invention is employed, the time can be corrected with a single touch even if the error is as large as ±1 minute, or in other words, even if the correction interval is long.

This is the greatest feature of the present invention.

[Brief explanation of the drawing]

Figure 1 shows the time display segment of an electronic watch, Figure 2 shows the time display segment of an electronic watch.
The figure is a block diagram showing one embodiment of the present invention, Fig. 3 is a block diagram showing another embodiment of the present invention, Fig. 4 is a time chart in Fig. 3, and Fig. 5 is a block diagram showing another embodiment of the present invention. 1 is a block diagram showing an embodiment of the present invention. In the figure, 11 is an AND gate that detects that the time is 59 minutes and Y seconds; 12 is an AND gate that detects that the time is 00 minutes and Y seconds; 1-113 is a time adjustment switch;
is one terminal of the switch, 15 is a delay circuit of τSEC,
16, 2L34 are OR gates, 17, 20, 35 are AND gates, 18 is one pulse of τ, 19, 22 is 60
decimal counter, 23 is decimal counter, 30 is Nando game
t-131 is a continuous wave with a pulse width of τ(SEC), 32.3
3 is an R-8 flip-flop constructed of Nant gates.

Claims (1)

[Claims] 1. A first detection means for detecting 59 minutes of the time display; a second detection means for detecting 00 minutes of the time display;
a time adjustment switch; a first gate circuit that generates a first control signal when a detection output of either of the first and second detection means and an output from the switch are present; The first flip-flop is set to one state by the output from the gate circuit and set to another state by the constantly supplied pulse signal, and measures the second time.
a counter, means for resetting the first counter in response to the negative state of the flip-flop, and means for counting the output of the first counter and being reset in response to the negative state of the flip-flop. a second counter for counting minutes; a second gate circuit for inputting the non-detection output of the first detection means and the signal of the flip-flop in the - state; An electronic timepiece comprising: a time counter that performs counting and is incremented by one increment by the output of the second gate circuit.