JPS5928740A - Communication system - Google Patents

Abstract

PURPOSE:To attain surely excellent communication quality, by converting an input binary digital signal into separate blocks and transmitting them, and reproducing them into the original signal at the receiving side so that noise on a transmission line is spread in time and concentrated noise is brought into random noise. CONSTITUTION:A binary digiral series having a clock period T applied to a signal input terminal 8 is converted into a parallel digital series at the period NT at each block by using N-digit as one block at a series-parallel converting circuit 9 and applied to an input terminal group of a transmission signal converting circuit 11. A signal value of the input terminal group of an optional block is imaged linearly at the circuit 11. Each block of N-digit of the binary digital input series is converted into a transmission signal block of PAM pulse train in M-digit and transmitted to a transmission line 16. The receiving signal of the transmission line 16 is demodulated at a receiver 17 and the original transmission signal is reproduced. A receiving synchronizing device 18 detects a block synchronizing signal and generates various clocks required to operate a series- parallel converting circuit 19 and a parallel-series converting circuit 24. The parallel binary digital series is converted into the N-digit series having the clock period T at the circuit 24, and outputted to a signal output terminal 25.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a communication system that reduces burst errors caused by impulse noise and momentary interruptions added to a transmission path.

Background of the Technology In digital communication systems intended for data transmission and PCM transmission of broadcast program signals that require high quality, it is important to reduce random code errors as well as burst errors. This burst error is caused by, for example, impulsive noise in digital transmission using balanced cables in existing telephone networks, fading in wireless transmission, and other types of noise, such as large, instantaneous noise such as interruptions, etc.
The code d is missing for a short period of time, resulting in a continuous code mb, which is a major problem.

Random code errors that occur due to random noise such as thermal noise and crosstalk noise that occur in the transmission system can be solved by designing the transmission system with a sufficient S/N ratio to ensure the desired transmission quality. It becomes possible to deal with it. However, in order to provide a transmission system with a sufficient signal-to-noise ratio even for short-term but large-amplitude impulse noises, it is necessary to either dramatically increase the transmission power or significantly shorten the transmission distance. The necessary practicality is lost. For this reason, a smear/desmear method is known as a conventional countermeasure against this type of noise. (For example, R, A, iF'ain
wrigAt: 'On the Potentia
lAdvantage of aSmearing-
Dasmaaring Filter Tachniq
μ-Impulse No.
1se Problamy in Datα5yzta
yy', IRE Trans.

on COM, Syz, ,P,562. Dec,
1961) The operation will be briefly explained based on FIG. 1 showing the block configuration of this method.

On the fading side, data No. 16 applied to input terminal 1
The signal .multidot. is converted into a signal that matches the transmission line by the transmission line 1a root 2, and is sent to the transmission line 4 after passing through the smear filter 3f. On the other hand, on the receiver 16 side, the signal from the transmission line 4 passes through the desmear filter 5, is added to the receiver, and the reproduced data signal is output to the output terminal 7.

Here, it is assumed that the amplitude transfer characteristics of the smear filter 6 and the desmear filter 5 are both constant with respect to frequency. Figure 2 shows the delay time characteristics. ■ is the characteristic of the smear filter, ■ is each characteristic of the desmear filter, and ■ is the combined characteristic of smear and desmear. As shown in the figure, the characteristics vary linearly in opposite directions with respect to frequency, and the smear/desmear overall characteristics are assumed to be constant with respect to frequency. The Boolean signal passes through both filters 6.
5, it is converted back to the original one-word waveform, or
Impulse noise etc. added on the transmission path 4 is given a different amount of delay depending on the frequency by the desmear filter 5 on the receiving side, so it is spread on the time axis and converted to random noise, so it is not converted into data signal. The impact will be reduced.

Prior Art and Problems In order to clearly demonstrate the effectiveness of the conventional smear/desmear method, it is necessary to realize a delay characteristic with a steep slope on the frequency axis, and the delay difference within the band is considerable, and the amplitude Since the smear/desmear filter pair was required to have strict characteristics such as constant transmission characteristics, the scale of the device was prohibitive, and the adjustment was complicated, making it difficult to realize and not put into practical use.

Purpose of the Invention In order to solve these drawbacks, the present invention blocks an input digital sequence such as a data signal, performs linear mapping on the digital sequence in each block, and converts it into blocks of other sequences. The sequence is time-spread within the block period and transmitted, and on the receiving side, the original digital sequence is regenerated by performing inverse mapping on each received block in υ time and reproducing the original digital sequence2. On the other hand, the random noise is time-spread within a block period to become random noise, and will be explained in detail below with reference to the drawings.

Embodiment of the Invention FIG. 6 shows a first embodiment of the present invention, in which 8 is a binary digital series 1h input terminal, 9 is a serial/parallel conversion circuit, and 1
1 is a transmission signal conversion circuit, 10-1.10-2°...
..., 1o-N and 12-1.12-2.・・・・・・、
12-M are an input terminal group and an output terminal group of the sending fs 1m converter circuit 11, respectively, 15 is a parallel-to-serial converter circuit, and 14
15 is a transmitter, 16 is a transmission line, 17 is a receiver, 18 is a reception synchronizer, 19 is a serial/parallel conversion circuit,
21 is a received signal conversion circuit, 20-1, 20-2, .
..., 20-AI and 22-1.22-2.・
..., 22-N are an input terminal group and an output terminal group of the received signal conversion circuit 21, 23-1, 23-2,
. . . , 23-# identification circuit group, 24 a parallel-to-serial conversion circuit, and 25 a signal output terminal. Next, the operation will be explained in detail.

The binary digital series u(k) (-"<J<~) with a clock period T applied to the signal input terminal 8 is converted into a serial/parallel converter 9 by the serial/parallel converter 9, with each block having a period of N digits. The logic values &1" and '0" are sequentially converted into parallel digital sequences by the NT, and the logical values &1" and '0' become ・1" and 1-, respectively.
Output as a 1″ binary signal and use No. 4 conversion circuit 11 for transmission.
0 input terminal group 101+10-2. ...Added to 10-N. Now, the transmission signal conversion circuit 110 input terminal group 10-1, 10-2 .・・・・・・
・The signal values at 104 are uHr ul r
......, uH(usE(1+-1), i=
1.2, . ......, 12=J
Signal value ν1° hair 2. ..., νyo takes all the values expressed by the following formula.

vM= sM, u, 15M2u2+-=-+ 8MN
uNJ, 8II +...+ 8MN are transmission signal values at the input terminal group, respectively.

- and i respectively ul(l-1, 2,...,
#) Column vector whose elements are v buff - 1, 2, ... + M), l5 - 1 is 8゛ (i = 1.2 ...
..., N, No 1, 2. Equation +11 is expressed as follows as a transmission signal conversion matrix whose elements are . . . , M).

M=[S:]・w fil
'Output terminal of transmission signal conversion circuit 11! N12-1.12
-2゜..., parallel signal sequence v at 12-&
The blocks I + vM r..., vM are processed by the parallel-to-serial converter 16 to form a serial series of N digits with a clock period r' (selected slightly shorter than r), that is,
υ1. . . . , the pulse k is converted into a block of Rettahals train (PAN pulse train) whose width is changed by using ~ as the amplitude value. In the transmission synchronizer f14, a block synchronization signal is inserted into the block of this PAM pulse train to obtain a transmission signal block whose length is exactly NT. Through the above operations, each block of N digits of the binary digital input series is sequentially converted into a transmission signal block in which a block synchronization signal is added to a block of N digit PAM pulse train. The transmission signal block series created in this way is modulated by the transmitter 15 into a format compatible with transmission on the transmission line 16.
will be sent to.

The received signal from the transmission line 16 is sent to the receiver 17 and the original transmitted signal is regenerated. The reception synchronizer 18 detects the block synchronization signal included in this reproduced signal and establishes block synchronization, and also connects the serial/parallel conversion circuit 19 . Various clocks necessary for operating the parallel-to-serial conversion circuit 24 are generated.

The PAM pulse sequence in the reproduced signal is converted into a parallel signal sequence vl + v! by the serial/parallel conversion circuit 19 in turn, with each block having N digits from the block 411 as one block, every cycle NT. +......, converted to vM, receiving t= +, input terminal group 20- of r number conversion circuit 21
1, 20-2,...

Added to 20-M. The received signal conversion device 21 converts a column vector V having 8 V7 (i=1 +2+..., n) into rt,' (L-1121...
...2M, No 1, 2. . . . N) is the element of the selling element J, u2, ......The first shift of the face is connected to its output terminal group 22-1, 22-2,...
..., output to 22-H every cycle NT. These output signal values u, l''2 +...+uN are detected by the identification circuits 23-1, 23-2, . . ., respectively.
. , 25-N, positive/negative identification is performed, and the logical value is converted to 11'' when positive and 10'' when negative. This parallel binary digital series is converted into a series of N digits with a clock period T by a parallel-to-serial conversion circuit 24. The received signal conversion device 21 outputs a conversion output of 1LI + ” every period NT.
2 +...,Ul, a continuous binary digital sequence 1L(k)(-~
<k<10~) is output to the signal output terminal 25.

Is this the operation of the present invention?Next, the binary digital sequence u(k) applied to the signal input terminal 8 on the transmitting side is correctly reproduced on the receiving side, and is also affected by the noise received on the transmission path. The conditions for the transmission and reception signal transformation matrices [S] and [R] that minimize code errors will be described.

When noise is received on the transmission line 16, the received signal converter 210 input terminal group 20-1, 20-2. ..., the vector τ of the received parallel signal sequence added to 20Jf is now .

It is expressed as υ=τ+, rl(3). Here, public is the vector of the transmission parallel signal sequence output from the transmission signal converter 11 described above, and k is the PAN received by the receiver 17. From Equation 41+11', (2+ and (3)), which is a noise vector with noise amplitude 'nj ('-1+2 +..., M) as an element, the parallel signal series of the output of the received signal conversion circuit 21 is obtained. The vector is ◇ u = [R) [S) - 10 [R] (4)
From equation (4), the element u1 (k'''1 + 2 +・
・・・・・・+N), “i,”nl ”−”k
2”nl ”””'+”kMH'nM (5
' becomes. Here, 9 purple of matrix [S], [R] is &=1
．． 2. ......If we satisfy the following relationship for N, that is, if we set k to be a unit matrix with N rows and 8 columns, then CRX 5,11-M, then υ according to equation (5) As is obvious, UK is A.

(force"k="k"k+ ・en, 10rk
2 “W2””””rAM”WM. In the above equation, the first term represents the rs acid component, and the second and subsequent terms represent the noise components added in the transmission path. Therefore, if we set the condition of equation (6),
Although the second output u1 of the received signal conversion circuit 21 includes noise, the second input signal u1 of the received signal conversion circuit 11
k will be played.

Next, this noise component will be considered. As described above, the noise added in the transmission path includes stationary random noise such as thermal noise and non-stationary impulsive noise. First, the matrix [S], [7
? ] will be described, and within these conditions, the conditions for reducing impulsive noise disturbance, which is the aim of the present invention, will be clarified.

Formula (the noise component included in ul from the force is ah(k-L2+
・・・・・・．

At), then '=ri+''nj''k2''nl+''''10''kM'' BM (expressed as 8').

Let us now assume that the noise added in the transmission path is stationary random noise, and that the A) of the PA) d pulse sequence received by the receiver 17 is
The noise amplitudes e□ (l=1.2...+'') added to each IN digit PAI pulse train have low correlation with each other, so they are approximated as uncorrelated. In other words, the average value of X is generally expressed as Then, it is approximated as follows.In the above equation, Pl represents the noise power as the root mean square value of ~, and is constant due to the stationarity of the noise regardless of the value of i.

Based on the above assumptions, we obtain the power P of ak using the formula (8
1, clearly from +91, Pa = '% - (rL "L+・"""":y
) ・PnOrJ.

On the other hand, the amplitude of the PA)d pulse train output from the parallel-to-serial conversion circuit 16 is shifted ()-1+2+...+"
), the transmission power P8 can be obtained by calculating the equation +1). Here, the transmission binary sequence u6 (a-1+2
+...

Since N) are generally random and have no correlation with each other, and take the value of '1' or '-1', the following holds true.Therefore, P8 is the formula f1), (clearly from iυ,) pB,= s2. 10s'2+・=・+a=
H no no no
No N.

The matrix (
By selecting the elements of [, the cost is the smallest compared to binary identification of ξ and reproduction of uk. This P6 has the formula OI, r&I, rk2.・・・・・・＋”
Although the kMO values can be made arbitrarily small by approaching zero, it is not practical to make the transmission power P8 arbitrarily large in equation (6). Therefore, in practical terms, the transmission power P8 of equation 02 is −
It is possible to select the elements in the rows and columns [S] and [R] so as to minimize the noise power P given by the formula under the condition of formula (6), with the restriction that the value is less than a fixed value λ1. It becomes necessary.

Further, if P changes depending on the value of k, the rate of charge when reproducing πk differs depending on the input, which is undesirable. For this reason, it is also necessary to make P and k equal to each other regardless of k.

To summarize the above, s p +r =, 10...+82N≦λ2. (
)=1.2.・・・・・・＋ ” ) α floor No. 1
No no r:, +r:2+--+rj, == rll +r
:2+ ・・・・・・+rnr (k,'=1 +2+
.../V) Q41 It is good to minimize P under the following conditions.

Formula 01, 03. From Q41, it is clear that the following inequality holds true. Here, it is clear that the equality sign holds true: s! +aF +...+sN-λ2, (No 1, 2......, AI) QQ horn door
limited to cases of Next, 2〇! The well-known S in the second equation of 9
When the chwarz inequality is applied and the condition of equation (6) is taken into consideration, the inequality 3m N AI is established. Here, if the equal sign holds true,
ry −p with μ as a constant 8. h , ()=1+ 2+ --
, Af l &=i, 2! +--1/V) (
Limited to +119.

The above 2 (61, C141, α (to) and the betting conditions,
If we do some simple calculations and summarize, we get the value of .

From the above, the SN that keeps the transmitting 16 signal power below the constant value λ2
The matrix (5'l) that maximizes the ratio (s/IV - VP6
), k is chosen so that it is equal to -λ2 and forms an orthogonal system.

However, Jl≧N, and the length of the vector is the square root of the sum of the squares of each pseudotree of the vector.

<Condition 2> The matrix [R] is selected so that, when the transposed matrix of C5J is represented by [S]', [R]=π[S]1.

becomes.

Since it is the noise-power that
It means the SN ratio of the transmission system consisting of C'
/lv). Expressed as (?N)^=-(-'/y). (stomach)
”kN.

From the above equation, in the case of M = H, (s/N) 8 - (shift. and 1) Even if transmission is performed using the linear mapping of the present invention, the SN ratio at that time will be the same as the SN ratio of the transmission system itself. It can be seen that they are not equal. In the case of M>N (D, the required frequency band of the transmission system or the signal band of the input sequence u(&) is expanded to νN times, and therefore the SN ratio (S/N) of the transmission system It should be noted that . generally changes.For example, in the case of a wireless transmission path, where the noise power Pn added on the transmission path is proportional to the transmission band, (,5/N). is C5/N).
Since the signal-to-noise ratio is improved by a factor of 1/N, the overall signal-to-noise ratio does not deteriorate as in the case where M=H, and the improvement can be achieved by a factor of u/y. On the other hand, in the case of a wired transmission path, the noise powers P and L generally increase rapidly as the transmission band increases, so compared to the case where M=H, the noise power P and L increase (C5/N). Therefore, even considering the SR ratio improvement of M/N times (5/
N) decreases.

'XLk From the above, if the transmission path is wireless or optical fiber, M
≧N, and in the case of wired k (= N, it becomes clear that transmission using the linear mapping of the present invention is possible without deterioration of the S/N ratio against random noise.fC6 Next, the present invention's We will describe the conditions necessary to reduce the impulsive noise disturbance that we are aiming for.

Now, for simplicity, the duration of the impulse 49 noise added on the transmission path is extremely short, and the first digit (7-L2+... It is assumed that noise with amplitude a 1y is added only to digits . . . , M) and no noise is added to other digits. At this time, as is clear from equation (8), the impulsive noise component a contained in the received binary signal u1 of the reproduced first digit is Ik k)
It becomes υ. PX the power of impulsive noise
(= e near), then aJA force P, engineering, becomes by applying the condition of formula (■).

The impulsive noise power P□ received on the transmission path is given by the above formula for each digit of the received binary signal, P, (&-i+
2+...+N). Here, if the sum of the noise power allocated to each digit is P, then using the 2010 condition, Pr N P, P, □, -7・(7)'''
(c) becomes.

Formula ψa,c! 3, the sum of the noise power is constant, and the reception 2
The first digit, second digit, etc. of the value signal.
・.

B for the Nth digit? , : s2□:・four bows 8,
It can be seen that the horn noise power is distributed at a ratio of 2N. If this distribution is made uniformly for each digit, the noise power of each digit will be reduced, and therefore the error p rate during binary discrimination will also be reduced, eventually making it possible to reduce impulsive noise disturbance. The conditions for this are as shown in equation (9): λ2-s7. Ten, slz+
Considering the relationship ・・・・・・+8,2N, it is clear that λ2 Blk= 11 (k=112+ ・・・・・・,N,
No 1, 2. ...1M) L241. Next, if impulsive noise is added to the PAM Hals sequence over consecutive Clearly, the following equation holds.

Now, the impulsive noise Mif&, - is mapped and transmitted on the transmission path with the time width τ)I pulse train (the power of the clock cycle is -1, so this impulsive noise is p, at pulse transmission power, P Since is the impulsive noise power,
λ”/px Vi means the SN ratio with respect to the impulsive noise of the transmission system itself during the impulsive noise period r.

Therefore, only the transmission by -order mapping can be improved. For example, assume that a binary digital sequence of 64 kA// is transmitted through a linear mapping, and r = 10 p
When z, M = 2,000, the amount of improvement in the S/N ratio is 10 Boy (acceptable) = 34.9 dB,
Normally strong impulsive noise can be transmitted without any errors.

That’s it, 2〇! It has been found that if the condition (1) is satisfied and the value of 31 is selected to be sufficiently large, impulsive noise interference can be significantly reduced. Here, there is a problem that the condition of Equation 4 is somewhat strict and reduces the degree of freedom in selecting one matrix [sj, [R].

In order to reduce impulsive noise disturbance, it is necessary to
The impulsive noise received by the AN pulse train is reproduced and received 2.
It is best to distribute the noise as uniformly as possible to each digit of the value code, that is, to spread the noise on the time axis.Also, as already mentioned, each digit has sj, : s, 22:...
...:8. Noise power is distributed according to the ratio of IN, and the total sum of the noise power is constant. From this, the following condition 6 is obtained, which is a matrix C51 to reduce impulsive noise interference, [20 is the condition for jO].

<Condition 6> The square values of each element of the row vector of the transmission signal conversion matrix [sj (column vector of the reception signal conversion matrix [R]) are selected to be as equal as possible and to have a small number of zeros.

<Condition 1> for the matrices C5J and [[ described above.

If conditions 2 and 6 are all satisfied and the value of M is selected sufficiently large, the S/N ratio will not deteriorate against random noise received on the transmission path, and it will be significantly resistant to impulsive noise. An improvement in the SN ratio can be expected.

Next, a detailed construction method of the main parts of the practical example of the present invention shown in FIG. 6 will be described. On the transmitting side, the part that performs the functions of serial-to-parallel conversion, transmission 1g signal conversion, and parallel-to-serial conversion is called the transmitting signal conversion section, and similarly, on the receiving side, it performs serial-to-parallel conversion,
The section that performs color signal conversion, identification, and parallel-to-serial conversion functions is called a received signal conversion section. In realizing both conversion sections, there are two methods: one using analog processing and the other using digital processing.
Complementary classes exist.

FIG. 4 shows an embodiment of a transmission signal converter using analog signal processing. The binary digital series applied to the signal input terminal 8 is transferred to an N-stage shift register 35 and a latch circuit group 36 that latches the output of each stage of the shift register 35 for each block period with N digits as one period. -1
, 66-2, . 37-1.37-2. ......, 57-N is a changeover switch group, which is controlled by the logic output of each digit in the above parallel series, and has +1V and -' corresponding to the logic outputs "1" and "0", respectively. Input the voltage of IV to terminal group 10-
1°10-2, ..., output to 10-N.

According to the above, the input binary digital series has been converted into a binary parallel series of +1V and -1r with N digits as a block. Next, the transmission signal conversion is performed using a resistor network having a resistance value as shown in FIG.
..., realized by 38-M. Input terminal group 10-1.
10-2. ......, the voltage at 10-# is 24 H, u %, output terminal group 12-112-2, respectively.
．．・・・・・・The voltage at 12-M is V++
υ2. .......

Assuming τ, in the case of μ) 1, as is well known, 8 1
8 to 2 8kN=-(8h+
"t+8&21L--...+8hN%)
QJ5 (&=1.2...l A/ )
It is exactly the same as the relational expression for transmission signal conversion of Tonashi equation (1) except that it has a negative sign. Since this negative sign is also added to the reception 16 signal change time, which will be described later, the reproduced received signal has a positive sign, and the υ problem does not occur.

When the transmission signal conversion is realized using a resistor network as shown in FIG. 4, each resistance value can only be positive, so 8g 7 (t -1r 21 · , N, no 1 . 2
．．・Song・lAf) If there is a negative value, it will not be possible to realize it. FIG. 5 shows a partial circuit for converting the transmitted signal to solve this problem. The input terminal (k=1.2...
..., /l/) Connect a resistor to 10-&, 8.
For k<0, the phase inversion amplifier 41- becomes effective.

In the above manner, the output group 12.-1, 12-2,...
. . . , a parallel signal sequence ν, which has been converted into a transmission signal and is output to 12-M.

v! + “”” r VM is gate pulse GP,
, GP, , -..., analog gate circuit group 39-1.39-2°..., controlled by GP,
39-Af, the signals υ are each converted into narrow pulses, which are added together and output to the output terminal 40. Figure 6 is a time chart of gate pulses, GP.

By using M-phase pulses with a width T' as the IGPM, a series PAM pulse train with a clock period T' is obtained at the output terminal 40, which corresponds to the pulse train shown in FIG. is added to the period device 14.

FIG. 7 shows an embodiment of a received signal converter using analog signal processing. A signal from receive synchronizer 18 of FIG. 6 is applied to input terminal 42. This signal is the M-phase sampling holding pulse SHP, , SHP, , -song-,SHP.

Sampling and holding circuit groups 43-1 and 43 each operate at
A group of sampling and holding circuits 44-1.4 whose respective outputs operate with a common sampling and holding pulse SEP whose period is the block period again.
4-2. .......

44-M is sampled and held.

FIG. 8 shows the sampling holding pulses SEP, , SEP,
,...

Although the SHPM and SHP time dates are shown, it is assumed that the digit phase and block phase of each pulse are phase-synchronized with those of the FAI pulse train applied to the input terminal 42 by the reception synchronizer 18.

These sampling and holding pulses are applied to the sampling and holding circuit groups 43-1, 43-2, . . . in FIG. ..., 43-Af and 4
4-1, 44-2,...

44M, the series PAAI pulse train at input terminal 42 is a parallel PA of M digits.
) d pulse and input terminal group 20-1, 20-2.
.......

20-M. This parallel PAM pulse sequence is
Resistor network and Rinke amplifier group 45-1, 45-2, ・
..., the received signal is converted by the received signal conversion circuit configured by 45-N, and the output terminal group 22-1.22-2
, . . . , 22-N to output parallel regenerated received binary sequences. The operation of this reception signal conversion circuit is exactly the same as that of the transmission signal conversion circuit, and if the resistance value of the resistance network is selected as shown in the figure, the input terminal group 20-1, 20-2
．． ......, 20-M and output terminal group 22-1.2
2-2. ......, the voltage at 22-H is 88Vll"!l...+9M and "l+"!, respectively.
+・・・・・・,～, then μ)1, uk= −(r&I V, +r12u2 +−−+r
kMvM) @(k=1.2...
, N) holds true. This relational expression is exactly the same as expression (2) using a vector and a matrix except that a negative sign is added. Since a negative sign is added during transmission conversion, this negative sign is canceled and a binary parallel sequence with the correct code is eventually reproduced. Incidentally, rIy having a negative value can be dealt with by using the same configuration as that already described in FIG. 5 for the transmission signal conversion section.

Output terminal group 22-1.22-2. ..., 22-N
The reproduced binary series Aya, J, .
23-# logical value ``1''.

This series is converted into a serial binary digital series by a parallel-to-serial conversion circuit 24 using an A1-stage parallel-in/serial-out shift register, and is output to a signal output terminal 25. It turns out.

It has become clear that by adopting the configuration described above, it is possible to realize transmission and reception signal conversion by analog signal processing. Next, a configuration method using digital signal processing will be described.

FIG. 9 shows an embodiment of a transmission signal converter using digital signal processing. The binary digital series applied to the signal input terminal 8 is transferred to an N-stage shift register 65 and a latch circuit group 3.
6-1.36-2. ..., 36-/V,
Immediate values “1” and “0” are converted into binary conversion circuit group 46-1.46
-2. .......

11” digitized to binary by 46-N.

They are converted into binary values G and iQ of "-1", respectively. This digitized parallel binary series "! + ' is added to the input terminal group 20-1, 20-2, ..., 20-H
G + .
2-1.22-2. ..., 22-M digitized signal value average, v2. ...Outputs +vM.

The digital calculation transmission signal conversion circuit 47 is a digital calculation first.

wired logic (
W/irgd R, logic), or software (5of wa) using a processor.
re ), and these can be easily realized using well-known methods. Output terminal groups 22-1, 22-2, .=., 22-H obtained as above
The signal value series "l r υR+ . . . , rice" are each converted into binary digitization, so they constitute a word consisting of a plurality of pits.

Therefore, it is easily converted into a serial signal value series by the word-structured parallel in/serial out shift register 48, and further converted into a p, or pulse train having an analog amplitude by the DA converter 49 and output to the output terminal 40. Ru. This output PAN pulse train is the same as that shown in Figure 3.
It will be added to 4.

FIG. 10 shows an embodiment of a received signal converter using digital signal processing. Each analog amplitude value of the PAdd pulse train applied from the reception synchronizer 18 in FIG. 6 to the input terminal 42 is converted into a digital signal by the AD converter 50. This digitized PAM pulse train consists of M
Like the stage shift register 51, the latch circuit groups 52-1 and 52-2 have a word configuration.

. . . 52-M converts the input into a parallel pulse train and digitally executes the input 11. A digital performance transmitter 11 configured similarly to the digital performance transmitter @genchange circuit 47 of FIG. 9. It is converted by the Haku code conversion circuit 56,
Output terminal groups 22-1, 22-2, songs..., 22-H
The digitalized signal value series uI+''M+・knock・, 1LN is output.

The sign bit indicating the sign bit of each signal value has a logic value of “1”,
Digital identification circuit group 54-1 outputting as '0''
, 54-2.・・・-・-, 54, #, 111, signal value series J+"Y+..., squares are 2 of 1 bit each
The 9-element serial binary digital series is converted into a binary series, and is reproduced by the parallel-to-serial conversion circuit 24 using an N-stage parallel-in/serial-out shift register.
5 will be output.

The configuration of the transmitting and receiving signal converter based on the digital signal processing described above can be realized using AD, DA converters, and digital logic circuits, so it can be said that it is well compatible with LSI implementation of the device. Naturally, it is also possible to have a mixed configuration in which the transmitting signal converter is implemented using an analog signal processing method, and the receiving 18 signal converter is implemented using a digital signal processing method.

Note that the transmission synchronization device 14 in the first embodiment shown in FIG. Transmitter 15. Since various well-known methods can be applied to the configuration method of the post-reception unit 17 and the reception synchronization device 17, a detailed explanation thereof will be omitted.

FIG. 11 shows a second embodiment of the present invention, which is similar to the first embodiment of FIG.
Functions of the transmission brocade conversion circuit 11 and parallel-to-serial conversion circuit 16 in the embodiment and the reception signal conversion circuit 21° identification circuit group 2
3-1.23-2. ..., the functions of 23-# and the parallel-to-serial conversion circuit 24 are realized by different configuration methods. The same symbols as in FIG. 6 indicate the same parts.

In FIG. 11, 26-1.26-2. ..., 2
6-N is a group of transmission-order mapping coefficient signal input terminals, 27-1
, 27-2 , ..., 27-N is the arithmetic unit group, 2
8 is a blessing vessel, 29-1, 29-2,...
, 29-AI is a group of reception-order mapping coefficient signal input terminals, 30
-1.30-2. ..., 60-M is a boarding device group,
61 is an adder, and 62 is an identification circuit. Next, the operation of this embodiment will be explained in detail with respect to the parts that are different from the embodiment of Measure 1.

Transmission-order mapping coefficient signal input terminal group 26-1, 26-2
.

. . . , the transmission-order mapping coefficient signal groups to be added to 26-N are 8, (,t), 8, respectively. Ct),...
・l &N(t), each of these signal groups is a periodic function with a period NT, and is selected as follows for one period from 1=0 to t=NT.

Tata, g(t)-u. (t)-140(t-7”)l
(uo(t): unit step function) 2 gI in this example, (l=L2+...AI, no 1
,2. ......, N), therefore, the matrix [S] is expressed by the formula (1
)' matrix [S], <Condition 1>, <
Condition 2> and <Condition 6> shall be satisfied.

Input terminal group 10-1, 10-2,..., 1
A parallel fd number series, U, where one block is O≦t≦NT in o-N.

. . . , and the transmission fN-order mapping coefficient signal group 11 + (/IS*Ct) + . . . IJN (t
) or multiplier group 27-1.27-2°, respectively.
, 27-N, and the results are added to adder 2.
8, the output 8(t) becomes as shown in the following equation using equation (11).

8(t) −(JIBJ+Jl,, u2+−・=・・→
-111H2t,,)6(t)+(8,,u,+8.,
u, +-・-+8□, u,)e(t-T')+(8M,
rt, +5M2rt2+-=-+8. ,u,)e(t-
(AI-1)T')=v,g(<)+u,g(t-r'
) 10-=-+vMe(t-(M-i)r') 0
1 As is clear from the above equation, the output signal 8(t) is the parallel signal series 1L1. It can be seen that it is equivalent to linearly mapping the town, .

The same is true for the receiving side 1-, and the receiving-order mapping coefficient signal groups are respectively rt (t) + r2 (t) + ”・
”r rM(t), and each of these signal groups has a period NT
is a periodic function, and one period from 1=0 to t=NT is selected as follows.

10-・-'(t-(N-1)r)
) However, #'(t) -140(t) -1L. (
<-T), (140(t): unit step function) 1
rtj(t-1+ 2 +...
・.

N, no 1, 2. ...2M), therefore the matrix [R
] is the same as the matrix [R] in equation (2), and satisfies <condition 1>, <condition 2>, and <condition 6>.

Input terminal groups 20-1, 20-2. ......, 20
- Parallel input with 0≦t≦NT in M as one block ♂
Number series vl+ν2. .......

8υ7 is converted in exactly the same way as in the case of transmission signal conversion, and the output R(t) of the adder 61 is converted to R(t) using equation (2).
= w, e' (t) + u, e' (t-r
) +-・-+uNe'(t-(/V-1)r) (3
1). Therefore, the output signal R(t) is obtained by linearly mapping the parallel signal series Δ Δ υI + v2 + . Therefore, the identification circuit 62 has a clock period T and R
By identifying the sign (t) of the PA)t pulse sequence, the original serial binary digital sequence can be reproduced.

Next, a method of generating a -order mapping coefficient signal will be explained. 1st
FIG. 2 shows an embodiment of a bleached first-order mapping coefficient signal generator.

Gate pulse GP, , GP, ,...lG
PM K Yoshi gate circuit group 56- controlled respectively
1, 56-2.

..., 56-M signal input terminal group 55-1, 5
By applying a constant amplitude signal 81 to 5-2, . . . , 55-AI, and applying .
7, the −order mapping coefficient signal Bt, (t) (k−1+
2 +...+N) is obtained.

FIG. 16 shows a time chart of the transmission 1g-order mapping coefficient signal generator, and the gate pulse GP as shown in the figure.

Obviously, if GP, , ..., GPM are used, the amplitude 8. A transmission −order mapping coefficient signal g having a pulse width T′1 period NT and a pulse width T′1 period NT.
k(t) is obtained. A reception-order mapping coefficient signal generator can also be easily realized in the same manner as in this embodiment.

Although the second embodiment of the present invention has been described above using a method using analog signal processing, a method using digital signal processing is also possible. In this case, input terminal group 10
-1, 10-2. ......, binary digitized binary series "I + 1L2 + ......
・Adding a face, the transmission-order mapping coefficient signal 8k(') (k
= 1 + 2 +..., N) amplitude 81k.

82,...+'Mk is also converted into binary digitization, and the multiplier groups 27-1, 27-2, 27
By using a digital multiplier for -N and a digital adder for the adder 28, a digitized serial signal (Mu code sequence) is obtained at the output of the adder.
By performing A conversion, a transmission analog P,4AI sequence is obtained.

On the receiving side, it is good to perform AD conversion of the analog PAM series from the receiving synchronizer 18, convert it into a digitized parallel series in the serial/parallel conversion circuit 19, and then execute the same digital calculations as on the transmitting side. It turns out.

The -order mapping coefficient signal generator has the same configuration as that shown in FIG.
For Mk, etc., a binary digit number is used, and gate circuit groups 56-1, 56-2, .・・−
. . , 56-M, it can be easily realized. This digital signal processing method has the characteristic of being well compatible with LSI implementation of the device.

FIG. 14 shows a sixth embodiment of the present invention, in which the block configuration of the second embodiment shown in FIG. converter 6
4 has been added. Same symbol as in Figure 11 if
, Ibj shows the same part. Figure 15 (, Z) is non-direct +%
+ The analog output characteristic for the digital input of the DA converter 66, FIG. 15(b) shows the non-direct M1. Examples of digital output characteristics for analog input of the AD converter 64 are shown. Next, the operation of this embodiment will be explained.

The binary digital sequence u(k
) is converted into parallel blocks for every N digits in the same manner as in the second embodiment shown in FIG. 11, linearly mapped to another block, and sent out from the adder 28 as a serial PAAI/:Rus sequence. Here, the superstition fim number conversion circuit 11
Input terminal group 10-1.10-2.・=-, parallel input signal series added to 10-N and transmission-order mapping coefficient signal input terminal group 26-1.26-2. . . . , the amplitude value Fi of the transmission-order mapping coefficient signal group applied to the group of transmission-order mapping coefficient signals 26-N is converted into binary decimel, and the multiplier group 27-1, 27-2 . ...
. . , 27-N and the adder 28 perform digital operations. Therefore, the amplitude of the PAM pulse train from the adder 28 is digitized. As shown in FIG. 15 (α), this digitized amplitude is expanded as the input becomes smaller and converted into a non-linear DA converter 3.
5 into an analog amplitude. The RAM pulse sequence having the expanded analog amplitude thus obtained is transmitted to the transmission line 16 through the fading synchronizer 14 and the transmitter 15. On the other hand, the received information from the transmission path 16 is transmitted to the receiver 1
7 and receiver same Luj installation [RAM sent 1g after 1B
A pulse sequence is regenerated. The expanded amplitude of this RAM pulse sequence is digitized to be equal to the original amplitude by a nonlinear AD converter 64, which compresses and AD converts the smaller the input, as shown in No. 15 (b). As described above, the non-linear AD converter 64 outputs the FAI pulse sequence having the original amplitude that has been converted into binary digitization. The reception-order mapping coefficient signal input terminal group 29-1, 29-2, . . . , 29
-M is added with a reception-order mapping coefficient multiplier group whose amplitude value has been converted into binary digitization, and multiplier groups 30-1, 30-2,
..., 30-A/ and the adder 31 perform digital arithmetic, the RAM pulse sequence having the above-mentioned digitized amplitude is serial-parallel converted by the same operation as in the second embodiment. , and is further subjected to reception-to-order mapping and output from the adder 61 as a digitized serial series. A nine-element binary digital series u(k) is reproduced by the digital identification circuit 62 which outputs the positive and negative sign bits of this series series as logical values of 1" and '0", respectively.

As described above, this embodiment uses the non-linear DA converter 66 on the transmitting side! In the second embodiment, the amplitude of the JRAM pulse sequence is expanded and transmitted, and the nonlinear AD converter 34 with the opposite characteristics on the receiving side compresses the amplitude and converts it into a PAM pulse sequence with the original amplitude. This operation restores other signals without amplitude distortion, but the amplitude of both random noise and impulsive noise added on the transmission path is compressed on the receiving side. Since the amount of noise is reduced and the amount of noise is reduced, even higher quality communication can be obtained. Furthermore, since the block lengths N and M for applying the -order mapping can be set small to provide a certain impulsive noise tolerance, there is an effect that the scale of the apparatus can be reduced.

The configuration of this embodiment has been explained based on the second embodiment, but in the first embodiment, the transmission (d signal converter 11
．． The feared signal converter 21 is constructed with a digital arithmetic circuit 1
, a non-linear converter, a 4-transformer, and a non-linear AD converter are applied to the transmitting side and the preparing side, respectively, to realize the same operation as in this embodiment.

As described in detail, in the communication system of the present invention, the input binary digital sequence is divided into blocks, and each block is transformed into another block by applying a linear mapping, so to speak, on the time axis. The signal is time-spread and transmitted, and the signal is time-focused using inverse mapping to reproduce the original (A 3), but the noise received on the transmission path is time-spread, so the signal is time-spread and transmitted.
This has the advantage that temporally concentrated noise such as pulse noise can be randomized and good communication quality can be ensured.

In addition, the method of the present invention can be easily realized by using digital signal processing technology, and therefore has high compatibility with LSI integration, and has the major advantage of being able to provide a method that is excellent in terms of reliability and economy. There is a point.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a conventional smear/desmear method, FIG. 2 is a delay time characteristic diagram required for a smear/desmear filter, and FIG. 6 is a block diagram of a first embodiment of the present invention method. Fig. 4 is a block diagram of an embodiment of a signal converter using analog signal processing.
A partial circuit diagram of signal conversion, FIG. 6 is a time chart of gate pulses, FIG. 7 is a block diagram of an embodiment of a reception signal conversion section using analog signal processing, and FIG. 8 is a time chart of sampling and holding pulses. FIG. 9 is a block diagram of an embodiment of a transmission 1g signal conversion section using digital signal processing, FIG. 10 is a block diagram of an embodiment of a reception signal conversion section using digital signal processing, and FIG. 11 is a block diagram of an embodiment of a receiving signal conversion section using digital signal processing. Second
FIG. 12 is a block diagram of an embodiment of the transmission-order mapping coefficient signal generator. FIG. 16 is a time chart of the transmission-order mapping coefficient V and the signal generator.
Fig. 4 is a block diagram of the sixth embodiment of the method of the present invention, and Fig. 15 (α) shows the non-direction I%! FIG. 15(b) is a characteristic diagram of the analog output with respect to the digital input of the DA converter. FIG. 15(b) is a characteristic diagram of the digital output with respect to the analog input of the nonlinear AD converter. 1... Input terminal, 2... Transmitter, 6... Smear filter, 4... Transmission line, 5... Desmear filter,
6...Receiver 1d machine, 7...Output Yi78 child, 8...
Signal input terminal, 9...Serial-to-parallel conversion circuit, 10-1.1
0-2. ......, 10-u... input terminal group,
11... Transmission signal conversion circuit, 12-1.12-2.・
..., 124... Output terminal group, 16... Parallel-serial conversion circuit, 14... Transmission synchronizer, 15... Transmitter, 1
6... Transmission line, 17... Receiver, 18... Reception synchronizer, 19... Serial/parallel conversion circuit, 20-1゜20-
2,...,2CJ-M...input terminal group, 2
1... Reception signal conversion circuit, 22-1, 22-2,
..., 22-N...output part group, 23-1゜2
3-2. ......, 23-N... identification circuit group,
24... Parallel-serial conversion circuit, 25... Signal output terminal,
2/)-1, 26-2,..., 26-N...
Transmission-order mapping coefficient signal input terminal group, 27-1.27-2
,..., 27-N... multiplier group, 28...
・Adder, 29-1.29-2゜..., 29
-M...Reception-order mapping coefficient signal input terminal group, 30-1
．． 30-2. ......, 30-M... multiplier group,
61...Adder, 62...Identification circuit, 56...Non-direct ffMDA converter, 64...Non... Changeover switch group 1.58-1.38-2. ..., 3B-M・
...Operation amplifier group, 39-1.39-2. ..., 59
-M... Analog gate circuit group, 40... Output terminal, 41-k - Phase inversion amplifier, 42... Input terminal,
43-1.43-2. ..., 43-A/... sampling holding circuit group, 44-1.44-2.・・・・・・、4
4-M...Sampling holding circuit group, 45-1.45-2.
......, 45-N- and Minoh amplifier group, 46-1. 46-2. ..., 46-N... Binary conversion circuit group, 47... Digital calculation reception signal conversion circuit, 48.
・・Parallel in-serial out shift register, 4
9...DA converter, 50...AD converter, 51...
Shift register, 52-1. 52-2. ..., 52-M... latch circuit group,
53...Digital calculation reception signal conversion circuit, 54-1
．． 54-2. ..., 54-N digital identification circuit group, 55-1, 55-2. ......, 55-m
...Signal input terminal group, 56-1, 56-2,...
..., 56-M... gate circuit group, 57... output terminal. Patent Applicant Nippon Telegraph and Telephone Public Corporation Agent Patent Attorney Gobe Tamamushi (6 others) No. 8 No. 9 Figure 10 Figure 1! i Figure 11 Figure 12 Figure 13 t'-8r-NT

Claims (1)

[Claims] fl) On the transmitting side, a binary digital series with a clock period T is sequentially converted into a binary parallel series with N digits as a block, and a linear mapping is performed on the parallel series of N digits. A parallel series of N digits is created, the parallel series of N digits is again converted into a serial PAM pulse series, and sent out to the transmission path, and on the receiving side, the received serial px
The pulse sequence is reproduced and sequentially converted into a parallel sequence of N digits as a block, and the N digit parallel sequence is subjected to a linear mapping inverse to the transmitting side to create an N digit parallel sequence. A parallel binary digital sequence is created by identifying the sign of each digit in the parallel sequence, and the binary digital sequence of the transmitted clock period T is converted into a serial sequence. A communication method characterized by playback. (2) On the transmitting side, a series PAM pulse sequence having a binary digitized amplitude is created by digital calculation, and a series PAM pulse sequence having an expanded analog amplitude is generated by performing nonlinear DA conversion on the binary digitized amplitude. Non-linear AD conversion converts it into a PAM pulse sequence and sends it to the transmission path, and on the receiving side, reproduces the received serial PAAf pulse sequence having the expanded analog amplitude, and compresses and digitizes the expanded analog amplitude. create a series P, 4M pulse sequence with the binary digitized amplitude;
The serial PAf pulse sequence is converted into a parallel sequence, and a linear mapping operation opposite to the linear mapping performed on the transmitting side is applied to the parallel sequence by a digital operation to reproduce the transmitted binary digital sequence. A communication system according to claim 1, characterized in that: (3) On the transmitting side, a binary digital sequence with a clock period T is sequentially converted into a binary parallel sequence with N digits as a block, and the signal of each digit of the N digit parallel sequence and the signal of each digit with a period NT are N -order mapping coefficients tg having a period of N digits are each delivered, and the 8
The serial PA obtained by adding the multiplication results
The N pulse sequence is sent to the transmission path, and on the receiving side, the received serial PAM Hals sequence is regenerated and sequentially converted into a parallel sequence with N guidites as a block, and the signal of each digit of the parallel sequence of N guidgits is generated. and a primary mapping coefficient signal of M inverse mapping coefficients with a period NT and N guisits in one period, respectively, and a clock obtained by adding the M multiplication results. A communication system characterized in that the transmitted binary digital sequence is reproduced by identifying whether each digit of the serial sequence with period T is positive or negative. (4) On the transmitting side, the digital calculation yc and the
A series PAAI pulse sequence having a binary digitized amplitude is created, and a nonlinear D is applied to the binary digitized amplitude.
A conversion is performed to convert it into a series PJ pulse sequence having an expanded analog amplitude, and the pulse sequence is sent to a transmission path, and on the receiving side,
The received serial PAJf pulse sequence having the expanded analog amplitude is regenerated, and the binary digitized amplitude is subjected to non-linear AD conversion that compresses the expanded analog amplitude and converts it into a digital signal. A linear mapping operation that is opposite to the linear mapping that was performed is performed by digital calculation, and the transmitted 2
7. The communication system according to claim 6, wherein a hexadecimal digital sequence is reproduced.