JPS5928721A - Detecting circuit of continuous alternating signal peak value - Google Patents

Detecting circuit of continuous alternating signal peak value

Info

Publication number
JPS5928721A
JPS5928721A JP57139037A JP13903782A JPS5928721A JP S5928721 A JPS5928721 A JP S5928721A JP 57139037 A JP57139037 A JP 57139037A JP 13903782 A JP13903782 A JP 13903782A JP S5928721 A JPS5928721 A JP S5928721A
Authority
JP
Japan
Prior art keywords
signal
peak value
level
circuit
continuous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57139037A
Other languages
Japanese (ja)
Inventor
Morishige Aoyama
青山 森繁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57139037A priority Critical patent/JPS5928721A/en
Publication of JPS5928721A publication Critical patent/JPS5928721A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses

Abstract

PURPOSE:To detect a peak value of a continuous AC signal with high accuracy and good linearity, by providing a comparator, a monostable multivibrator and an integrating circuit and the like to a level comparison circuit of a continuous AC signal peak value detecting circuit so as to detect the peak value up to a high frequency region. CONSTITUTION:An input continuous AC signal 1 is applied to a level comparison circuit 9, the signal is compared with an analog signal 4 from a D/A converter 11, and when the level of the analog signal 4 is higher than the level of the signal 1, an output 13 is applied to an up-down counter 10. A clock signal 12 is inputted to the counter 10, an output from the counter 10 is applied to the D/A converter 11 to detect the peak value of the signal 1. This comparison circuit 9 is constituted of the comparator 14 and the monostable multivibrator 15 or the comparator 14, the integrating device 16 and the 2nd comparator 17. Further, the level of the analog signal 4 is made almost equal to the peak value of the signal 1, the peak value is detected up to a high frequency region and the peak value of the signal 1 is detected with high accuracy and good linearity.

Description

【発明の詳細な説明】 本発明は磁気ディスク検査装置における記録再生出力の
エンベロープ検出・出力値検出などに用いられる連続交
流信号波高値検出回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a continuous alternating current signal peak value detection circuit used for envelope detection, output value detection, etc. of recording/reproduction output in a magnetic disk inspection apparatus.

磁気ディスク検査装置において記録再生出力のエンベロ
ープを検出する回路として#、1従来、第1図にブロッ
ク図で示すように入力連続交流信号1を整流回路2によ
シ整流し、それを積分回路3によりs分することによっ
て入力信号振幅と同レベルのアナログ出力4を得るよう
に構成されたものが用いられていた。整流回路2として
は第2図に示すようにトランジスタ5.6のベース・エ
ミッタ間の非線形性を利用した回路がしばしば用いられ
ていた。しかしながらこの整流回路を用いた場合には入
力信号波高値対出力レベルの直線性が特に低レベルの信
号に対しては悪く、磁気ディスク検査装置において記録
再生出力に対応する入力信号波高値が低レベルから高レ
ベルまで変動範囲が大きい場合には検査精度が悪くなる
という欠点があった。また入力信号波高値対出力レベル
の直線性が良い整流回路として第3図に示すようなダイ
オード7と演算増幅器8とを用いた整流回路もよく用い
られていた。しかしながらこの回路は演算増幅器の周波
数特性の限界によJ) l QM)lz以上の高周波数
の信号に対しては正しく動作せず、磁気ディスク装置屏
の高密度化・高周波数化に対応できなくなってきた。
Conventionally, as a circuit for detecting the envelope of recording and reproducing output in a magnetic disk inspection device, as shown in the block diagram in FIG. A configuration was used in which an analog output 4 having the same level as the input signal amplitude was obtained by dividing the input signal by s. As the rectifier circuit 2, as shown in FIG. 2, a circuit utilizing nonlinearity between the base and emitter of a transistor 5.6 has often been used. However, when using this rectifier circuit, the linearity of the input signal peak value versus output level is poor, especially for low-level signals, and in magnetic disk inspection equipment, the input signal peak value corresponding to the recording and playback output is at a low level. There is a drawback that the inspection accuracy deteriorates when the variation range is large from 1 to 3. Further, as a rectifier circuit with good linearity of input signal peak value versus output level, a rectifier circuit using a diode 7 and an operational amplifier 8 as shown in FIG. 3 was also often used. However, due to the limits of the frequency characteristics of operational amplifiers, this circuit does not operate correctly for signals with high frequencies of J) l QM) lz or higher, and cannot cope with the increasing density and frequency of magnetic disk drives. It's here.

本発明の目的は前記従来の回路の欠点を除去し、磁気デ
ィスクの記録再生出力の如き連続交流信号の波高値を高
周波数領域壕で直線性良く検出する連続交流信号波高値
検出回路を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional circuits and provide a continuous AC signal peak value detection circuit that detects the peak value of a continuous AC signal such as the recording/reproduction output of a magnetic disk with good linearity in a high frequency range. There is a particular thing.

本発明による連続交流信号波高値検出回路は、ディジタ
ル信号をアナログ信号に変換するDA変換器と、前記ア
ナログ信号と入力連続交流1信号の波高値とを比較する
レベル比較回路と、そのレベル比較回路の出力によって
クロック信号の力0n−計数・減yl創数の制御がなさ
れ前記ディジタル信号を出力するアップ・ダウン・カウ
ンターとを備え、前記アナログ信号のレベルが前記入力
連続反流信号の波高値とほぼ等しくなるように構成され
たことをり寺僧とする。
The continuous AC signal peak value detection circuit according to the present invention includes a DA converter that converts a digital signal into an analog signal, a level comparison circuit that compares the analog signal with the peak value of an input continuous AC signal, and the level comparison circuit. and an up/down counter that outputs the digital signal by controlling the power of the clock signal and outputting the digital signal, and the level of the analog signal is equal to the peak value of the input continuous countercurrent signal. It is assumed that the temples are composed so that they are almost equal.

以下、本発明の実施例を図面に基すいて駅間する。Hereinafter, embodiments of the present invention will be explained based on the drawings.

第4図は本発明による連続交jlf、信号波高値検+I
+回路の実施例であり、9はレベル比較回路、10はア
ップ・ダウン・カウンター、11けDA変換器を示す。
Fig. 4 shows continuous alternating jlf and signal peak value detection +I according to the present invention.
This is an embodiment of the + circuit, with 9 indicating a level comparison circuit, 10 an up/down counter, and an 11-digit DA converter.

また第5図6、その回路の動作をsi、”Jlするだめ
の波形図である。これらの図において、入力連続交流信
号1の波高値と、DA変換器のアナログ出力直流電圧4
とはレベル比較回路9で比較され、直流電圧出力4が入
力連続交流18号の波底値よシ大きい時は高レベルとな
シ、小さい時n低レベルとなるような出力13を得る。
In addition, FIG. 5 is a waveform diagram for explaining the operation of the circuit. In these diagrams, the peak value of the input continuous AC signal 1 and the analog output DC voltage 4 of the DA converter are shown.
is compared in a level comparison circuit 9, and an output 13 is obtained in which when the DC voltage output 4 is larger than the wave bottom value of the input continuous AC signal 18, it is at a high level, and when it is smaller, it is at a low level.

このレベル比較回路9の例としては第6図のように比較
器14と単安定マルチパイプレーク−15とにより(1
4成された回路あるいは第7図のように比較器14と積
分回路16と第2の比較器17とにより構成された回路
などを用いることができる。レベル比較回路9の出力1
3が高レベルの時にはアンプ・ダウン・カウンター10
はクロック信号12を減ηi1“数し、低レベルの時に
は力ロ′n帽数する。更にそのカウンター10のディジ
タル出力kl: D A変換器11によりアナログ信号
に変換されこれを該波高値検出回路の1白流′市圧出力
とする。
As an example of this level comparison circuit 9, as shown in FIG.
It is possible to use a circuit configured with four circuits or a circuit configured with a comparator 14, an integrating circuit 16, and a second comparator 17 as shown in FIG. Output 1 of level comparison circuit 9
When 3 is high level, amp down counter 10
The clock signal 12 is decremented by the clock signal 12, and when it is at a low level, the power is decreased by the number η1. 1 White current' city pressure output.

このような構成の回路によりDA変換器11のアナログ
出力4のレベルが入力連続交流信号10波高値より大き
い場合にはレベル比較回路9の出力が高レベルとなり、
アップ・ダウン・カウンター10のディジタル出力が次
第に減少し、これに従ってDA変換器11のアナログ出
力40レベルが次第に低下する。逆にDA変換器11の
アナログ出力40レベル乃1人力連続交流信号10波高
個より小さい’M分にはレベル比較回路9の出力が低レ
ベルとなり、アンプ・タウン・カウンター10のディジ
タル出力が次第に増力口し、これに従ってDA変換器1
1のアナログ出力40レベルが次第に上がυ、最終的に
は入力交流信号1の波高値とDA変換器11のアナログ
出力40レベルが等しくなった所で平衡が保たれる。
With the circuit having such a configuration, when the level of the analog output 4 of the DA converter 11 is higher than the peak value of the input continuous AC signal 10, the output of the level comparison circuit 9 becomes high level,
The digital output of the up/down counter 10 gradually decreases, and the level of the analog output 40 of the DA converter 11 gradually decreases accordingly. Conversely, when the analog output of the DA converter 11 is at 40 levels, or when the continuous AC signal is less than 10 wave heights, the output of the level comparison circuit 9 becomes a low level, and the digital output of the amplifier/town counter 10 gradually increases. DA converter 1 according to this
The analog output 40 level of the input AC signal 1 gradually increases to υ, and eventually balance is maintained when the peak value of the input AC signal 1 and the analog output 40 level of the DA converter 11 become equal.

クロック信号120周波数は回路の安定度と応答速度を
考慮すれば入力交流信号10周波数と同程度であること
が望ましいが、応答速度が遅くとも良い楊自には入力交
流信号周波数より低くしても良い。
Considering the stability and response speed of the circuit, it is desirable that the frequency of the clock signal 120 is about the same as the frequency of the input AC signal 10, but it may be lower than the frequency of the input AC signal if the response speed is slow. .

このような連続信号波高値検出回路の出力レベルの精度
はカウンター10及びIJA変換器11のビット数によ
って決まる。たとえUj8ピントのカウンター及びDA
変換器を用いた場合にはDA変換器の最大出力レベルに
対して256分の1のオ)3度で直線性良く波高値を検
出できる。
The accuracy of the output level of such a continuous signal peak value detection circuit is determined by the number of bits of the counter 10 and the IJA converter 11. Even Uj8 pinto counter and DA
When a converter is used, the peak value can be detected with good linearity at 1/256 of the maximum output level of the DA converter, ie, 3 degrees.

またこの回路が正しく動作するだめの入カイに月の周波
数範囲は比較器14の応答特性によってt5は決まる。
Further, t5 is determined by the response characteristics of the comparator 14, which is the input frequency range for this circuit to operate correctly.

例として周波数301〜111z  の信号を変調度0
〜100%、変調周波数100kHz で振Φ’、J’
、 ’JJ。
As an example, a signal with a frequency of 301 to 111z is modulated with a modulation depth of 0.
~100%, vibration Φ', J' at modulation frequency 100kHz
, 'J.J.

i!1.W Lだ信号を入力信号とし、クロック信号の
周波数を15 MHz 、カウンター及び1−) A変
換器のビット数を8ビツトとした時、1%以下の1vI
v度で入力信号の波高値のエンベロープに対応するアナ
ログ出力が得られた。
i! 1. When the input signal is WL, the frequency of the clock signal is 15 MHz, and the number of bits of the counter and 1-) A converter is 8 bits, the 1vI is less than 1%.
An analog output corresponding to the envelope of the peak value of the input signal was obtained at v degrees.

なお以上の説明では本発明による連続交p11.悄月波
高値検出回路を磁気ディスク検を装置1′″庫″に使用
するための回路として説明したが、磁気テープなど他の
磁気記憶体検査装置にも使用することができる。また一
般のAM復芯j器としても用いることが可能である。
In addition, in the above explanation, continuous intersection p11. Although the wave peak detection circuit has been described as a circuit for use in the magnetic disk inspection device 1'', it can also be used in other magnetic storage inspection devices such as magnetic tape. It can also be used as a general AM decentralizer.

以上のように本発明による連続交bIf、信号波高値検
出回路は高い周波数領域せで高い精度で直線性良く連続
交流信号の波高値を検出することができる。
As described above, the continuous alternating current bIf and signal peak value detection circuit according to the present invention can detect the peak value of a continuous alternating current signal with high accuracy and good linearity in a high frequency region.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の連続交流信号波高値検出回路を示すブロ
ック図、第2図、v、3図は第1図中の整流回路の例を
示す回路図、第4図は本発明による連続交流信号波高値
検出回路の実施例を示すブロック図、第5図は第4図の
回路の動作を示す波形図、第6図、第7図は第4図中の
レベル比較回路の例を示す回路図である。 1・・・・・・入力連続交流信号、2・・・・・・整流
回路、3・・・・・・積分回路、4・・・・・・アナロ
グ出力、5,6・・・・・・トランジスタ、7・・・・
・・ダイオード、8・・・演算増11す^器、9・・・
・・・レベル比較回路、10・・・・・・アップ・ダウ
ンΦカウンター、11・・・・・・I)A変換器、12
・・・・・クロック信号、14.17・・・・・比’I
Q:r、l 5・・・・・・単安定マルチパイブレーク
−116・積分回路。
FIG. 1 is a block diagram showing a conventional continuous AC signal peak value detection circuit, FIGS. 2, 3, and 3 are circuit diagrams showing an example of the rectifier circuit in FIG. 1, and FIG. A block diagram showing an embodiment of the signal peak value detection circuit, FIG. 5 is a waveform diagram showing the operation of the circuit in FIG. 4, and FIGS. 6 and 7 are circuits showing examples of the level comparison circuit in FIG. 4. It is a diagram. 1... Input continuous AC signal, 2... Rectifier circuit, 3... Integrating circuit, 4... Analog output, 5, 6...・Transistor, 7...
...Diode, 8...Calculation increaser 11, 9...
... Level comparison circuit, 10 ... Up/down Φ counter, 11 ... I) A converter, 12
...Clock signal, 14.17...Ratio'I
Q: r, l 5... Monostable multi-pie break-116/integrator circuit.

Claims (1)

【特許請求の範囲】[Claims] ディジタル信号をアナログ信号に変換するDA変換器と
、前記アナログ信号と入力連続交流信号の波高値とを比
較するレベル比較回路と、そのレベル比較回路の出力に
よってクロック信号の加算計数・減算引数の制御がなさ
れ前記ディジタル信号を出力するアップ・ダウン・カウ
ンターとを備え、前記アナログ信号のレベルが前記入力
連続交流信号の波高値とほぼ等しくなるように構成され
たことを特徴とする連続交流信号波高値検出回路。
A DA converter that converts a digital signal into an analog signal, a level comparison circuit that compares the analog signal with the peak value of the input continuous alternating current signal, and control of the addition count and subtraction argument of the clock signal by the output of the level comparison circuit. and an up/down counter for outputting the digital signal, the continuous alternating current signal peak value being configured such that the level of the analog signal is approximately equal to the peak value of the input continuous alternating current signal. detection circuit.
JP57139037A 1982-08-10 1982-08-10 Detecting circuit of continuous alternating signal peak value Pending JPS5928721A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57139037A JPS5928721A (en) 1982-08-10 1982-08-10 Detecting circuit of continuous alternating signal peak value

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57139037A JPS5928721A (en) 1982-08-10 1982-08-10 Detecting circuit of continuous alternating signal peak value

Publications (1)

Publication Number Publication Date
JPS5928721A true JPS5928721A (en) 1984-02-15

Family

ID=15235977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57139037A Pending JPS5928721A (en) 1982-08-10 1982-08-10 Detecting circuit of continuous alternating signal peak value

Country Status (1)

Country Link
JP (1) JPS5928721A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4870869A (en) * 1986-08-12 1989-10-03 Shigeo Nagatani Rotor composite engine
US7092828B2 (en) 2002-05-31 2006-08-15 Fujitsu Siemens Computers Gmbh Method for detecting communication impulses of a fan motor and circuit arrangement for carrying out said method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4870869A (en) * 1986-08-12 1989-10-03 Shigeo Nagatani Rotor composite engine
US7092828B2 (en) 2002-05-31 2006-08-15 Fujitsu Siemens Computers Gmbh Method for detecting communication impulses of a fan motor and circuit arrangement for carrying out said method

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