JPS5928069B2 - solid-state imaging device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a solid-state imaging device.

A conventional solid-state imaging device is shown in FIGS. 1 and 2. First of all, Fig. 1 is an equivalent block diagram of what is called a MOS type imaging device, where 1 is a digital scanning circuit, 2 is a photodiode, 3 is a MOS switch connected to each photodiode 2, and 4 is connected to a large array of photodiodes 2. M that was done
A signal output line (hereinafter referred to as a video line) is connected to the drain of the OS switch 3, 5 is a video line capacitance, and 6 is a load resistance. The operation of this device is such that when the switches 3 of the photodiodes 2 arranged in large numbers are sequentially turned on in the scanning circuit 1, the signals of each photodiode 2 are outputted to the video line 4.

Then, the output signal charge is received by a load resistor 6 to obtain an output voltage. For this operation, the output voltage is approximately inversely proportional to the video line capacitance 5. Therefore, the device shown in FIG. 1 has the disadvantage that as the video line capacitance 5 increases, the output voltage decreases. Furthermore, since the video line capacitance 5 increases as the number of photodiodes 2 increases, there is a drawback that a large number of photodiodes 2 cannot be arranged. Fig. 2 is a block diagram of what is called a CCD type imaging device, where 11 is a CCD analog shift register (hereinafter referred to as CCD), 12 is a part that performs photoelectric conversion and is called a photocell, and 13 is a photocell 12 and CC.
A part called a transfer gate is a switch installed between DII, 14 is a source follower type preamplifier that converts the charge transferred by CCDII into voltage, and 15 is a CCDI
A reset transistor clears the charge transferred from I, 16 is a load resistor, and 11 is a capacitor at the gate of the source follower type preamplifier 14.

The operation of this device is to transfer the signal charges of a large number of arrayed photocells 12 to the CCD II corresponding to each photocell 12 at once by turning on the transfer gate 13.

Then, the transferred charges are transferred to the CCD II output section by the CCD head pulse and outputted by the source follower type preamplifier 14. The source follower type preamplifier 14 operates to detect a signal by changing the potential of the gate of the preamplifier 14 as signal charges are fed thereto.

The gate capacitance Cfs of the preamplifier 14 is one to two orders of magnitude smaller than the video line capacitance Cv shown in FIG. Therefore, in the device shown in FIG. 2, the output voltage is large and the sensitivity is improved. However, the device shown in FIG. 2 has the disadvantage that the amount of charge that can be stored in the photocell 12 is limited by the amount of charge that can be transferred by the CCD 11, resulting in a small amount.
Furthermore, since the internal potential structure is a CCD structure, blooming tends to occur, and since the CCD11 itself senses light, it has the disadvantage that blurring of the image is likely to occur. This invention was made in view of the above points,
It is an object of the present invention to provide a solid-state imaging device that can increase sensitivity and obtain a clear image of good hair without image blur.

Embodiments of the present invention will be described below with reference to the drawings. Third
The figure is a circuit block diagram of a first embodiment of the present invention.

In this figure, 21 is a MOS type imaging device, which has a digital scanning circuit 22, a photodiode 23, and a MOS switch 24 connected to each photodiode 23. 25
is a signal output line (hereinafter referred to as a video line) of the MOS type imaging device 21, which is connected to the drain of a MOS switch 24 connected to a large number of photodiodes 23 arranged.

The arrow 26 indicates a CCD analog shift register (CC
27 shows the first gate (called D) of the CCD.
input gate) and 28 are gate electrodes of the next stage and subsequent stages of the CCD.

Is 29 the video of the MOS type imaging device 21? A line bias gate (first gate) that controls the bias of the input line 25, and a storage gate (second gate) 30 that temporarily stores signal charges are provided between the video line 25 and the CCD.

Further, 31 and 32 are switch gates, and the switch gate 31 (third gate) is the line bias gate 2.
9 and storage gate 30, switch gate 32 (
the fourth gate) is the storage gate 30 and the first gate of the CCD.
It is provided between gates 27.

FIG. 4 is a sectional view of the main parts of the above device, and in the figure, 25, 25,
27, 29-32 correspond to FIG.

Further, 33 is a P type board, 34 is a P+ channel stopper,
35 is an infrastructure layer for controlling potential, 36 is a thermal oxide film, 37 is a gate oxide film, 38 is an N+ diffusion layer of the video line 25, 39 is a PSG intermediate insulating film, 40 is a passivation film, 41 is for light shielding. This is an At film. The operation of the device configured in this way is as follows.

That is, the MOS type imaging device 21 operates as before,
The charge output at this time is injected into the CCD, and a signal output can be obtained from the output amplifier (not shown) of the CCD. The operation is like this, but the main parts of the above device are:
It is located at the part where the output charge of the MOS type imaging device 21 is injected into the CCD.

Therefore, the operation of that part will be explained in detail below. FIG. 5 is a timing chart of its operation, in which a is a timing pulse of the MOS switch 24 of the MOS type imaging device 21, b is a timing pulse of the switch gate 31, c is a timing pulse of the switch gate 32, and d is the first pulse of the CCD. This is the timing pulse for gate 27.

Line bias gate 29 and storage gate 30
DC voltage is applied to. Figure 6 a to g are the fifth
It is an internal potential diagram corresponding to t1-T7 of a figure.

In FIG. 6, a corresponds to time t1 in FIG. 5, and the photoelectrically converted signal charge φ is accumulated in the capacitance of the photodiode 23. In FIG. Next, when the MOS switch 24 is turned on at time T2, the signal charge Qs is transferred to the video line 2.
5 is almost injected.

In this case, the potential change of the video line 25 follows q=CV, and is the value obtained by dividing the signal charge Qs by the video line capacitance C. (Figure 6b). Then, when the MOS switch 24 is turned off at time T3, most of the signal charge Qs has been transferred to the video line 25. (FIG. 6c) Next, when the switch gate 31 is turned on at time T4, the signal charge Qs is transferred from the video line 25 to the bottom of the storage gate 30.

In this case, since the potential of the video line 25 is determined by the line bias gate 29, it is kept at a constant value. If there is no line bias gate 29, it is determined by the potential of the switch gate 31. (FIG. 6d) Then, when the switch gate 31 is turned off at time T5, the signal charge Qs on the video line 25 is transferred below the storage gate 30.

(Fig. 6e) Thereafter, when the switch gate 32 is turned on at time T6, the first CCD
Signal charge Qs is transferred below gate 27.

(Figure 6 f) Then, when the switch gate 32 is turned off at time T7, the signal charge Qs has been transferred to the bottom of the first gate 27 of the CCD.

(FIG. 6g) The signal charges injected under the first gate 27 of the CCD are output in the same way as in the conventional CCD.

FIG. 7 is a circuit block diagram of a second embodiment of the present invention, in which an unnecessary charge absorbing electrode is added to the storage gate portion of the first embodiment of FIG.

In FIG. 7, 21 to 32 are the same as in FIG. 3. 4
2 is an unnecessary charge absorption gate (fifth gate), and 43 is an unnecessary charge absorption drain.

FIG. 8 is a pattern plan view of the main parts of the second embodiment, and parts corresponding to those in FIG. 7 are given the same reference numerals.
Further, 44 is a metal wiring of the unnecessary charge absorbing drain 43;
5 is a contact hole between the N+ diffusion layer 38 and the video line 25, and 46 is a contact hole between the unnecessary charge absorbing drain 43 and the metal wiring 44. FIG. 9 is a sectional view taken along the line I-H-I in FIG. 8.

Each part corresponds to FIG. 8 and FIG.
The same reference numerals as in the figure are given. Among the operations of the second embodiment, the method of injecting charges from the MOS type imaging device 21 to the CCD is the same as that of the first embodiment. 1st
The difference in circuit operation from the embodiment is that the MOS type imaging device 21
This is the operation at the time before reading the signal from. The operation timing diagram is shown in FIG. In FIG. 10K, a to d correspond to a to d in FIG. 5. Figure 10e
is the clock timing of the unnecessary charge absorbing gate 42. The operation is the same as in the first embodiment between times t1 and T7.

On the other hand, at time Ta, the switch gate 31 is on and the unnecessary charge absorption gate 42 is on, so the video line 25 of the MOS' type imaging device 21 is connected to the unnecessary charge absorption drain 4.
The lower potential K of the line bias gate 29 is set by a bias of 3 (4 in the case of N channel).

Therefore, in this state, even though the pixel signal is not extracted due to light leakage, the charge is transferred to the video line 2.
5, it is absorbed by the unnecessary charge absorbing drain 43, and a state free of unnecessary charges can be maintained at all times. Time Tb is MO
The unnecessary charge absorption gate 42 is turned off during the time when preparations are being made to receive the image signal from the S-type imaging device 21.

Therefore, even if charges are next injected into the video line 25, they will not be absorbed by the unnecessary charge absorbing drain 43. Then, charge injection from the MOS type imaging device 21 to the CCD is completed from time t1 to T7. Then time TO
Then, the unnecessary charge absorbing gate 42 is turned on again in order to absorb unnecessary charges injected into the video line 25.

Photoelectric conversion is performed by repeating this timing.

FIG. 11 shows a third embodiment of the present invention, which shows that a diffusion layer may be provided after the switch gate 31, and a diffusion layer 47 is inserted between the switch gate 31 and the storage gate 30. There is.

FIG. 12 is a pattern plan view of the third embodiment, FIG. 13 is a sectional view taken along line 1--H--1 in FIG. 12, and FIG. 14 is a sectional view taken along line I-- in FIG. 12. The operation of the third embodiment is similar to that of the second embodiment.

As explained above, the solid-state imaging device of the present invention has MO
It is equipped with an S-type imaging device and a CCD analog shift register, and a signal output line of this MOS-type imaging device and a CCD
A first gate forms the potential of the signal output line, and a second gate stores the temporary signal between the analog registers.
a third gate located between the first gate and the second gate to control charge transfer, a second gate and a third gate located between the first and second gates;
The fourth gate is located between the input gates of the CD analog shift register and controls charge transfer.

Therefore, the signal charge from the MOS type imaging device can be injected into the CCD analog shift register without loss, and the CC
Since it is output as a D analog shift register output,
The low sensitivity, which is a disadvantage of MOS type imaging devices, can be improved by one to two orders of magnitude.

In addition, blurring of the image caused by using only the CCD analog shift register can be eliminated by not exposing the CCD analog shift register to light and by configuring the potential of the picture element part to be a MOS type system. As a result, clear images of good hair can be obtained. Furthermore, since the potential of the signal output line of the MOS type imaging device is determined by the first gate, there is an advantage that charge can be easily and completely injected into the CCD analog shift register. Furthermore, according to the method of forming the potential of the signal output line with the first gate, in other words, the method of making the signal output line a constant bias with the first gate, there is no fluctuation in the bias voltage, so the operation is stable. . Furthermore, by setting the bias of the signal output line in a DC manner, the operating margin of the pulse peak value applied to the third gate can be expanded, and the bias voltage application circuit can also be easily created using resistor voltage division. be able to. Furthermore, the device of the present invention can be realized with a smaller chip area than conventional devices. (Also, in the second embodiment, since the signal output line can always be maintained in the initial state, unnecessary charges injected into the signal output line can be absorbed, so there is an advantage that a solid-state imaging device with almost no blooming etc. can be obtained. be.

[Brief explanation of the drawing]

FIG. 1 is an equivalent block diagram showing a MOS type imaging device among conventional solid-state imaging devices, FIG. 2 is a block diagram showing a CCD-type imaging device among conventional solid-state imaging devices, and FIG. 3 is a solid-state imaging device according to the present invention. 4 is a sectional view of the main parts of the first embodiment, FIG. 5 is a timing diagram for explaining the operation of the first embodiment, and FIG. 6 is a circuit block diagram showing the first embodiment of the device. 7 is a circuit block diagram showing the second embodiment of the present invention, FIG. 8 is a pattern plan view of the main part of the second embodiment, and FIG. 9 is an internal potential diagram for explaining the operation. The figure is a sectional view taken along the l-t1 line in Fig. 8, and the 10th
11 is a circuit block diagram of the third embodiment of the present invention. FIG. 12 is a pattern plan view of the third embodiment. The figure is a cross-sectional view taken along line I-- in FIG. 12, and FIG. 14 is a cross-sectional view taken along line I-- in FIG. 12. 21...MOS type imaging device, 22...
Signal output line, 27...First gate, 29...
... Line bias gate, 30 ... Storage gate, 31, 32 ... Switch gate.

Claims (1)

[Scope of Claims] 1. A first gate comprising a MOS type imaging device and a CCD analog shift register, and forming a signal output line potential between the signal output line of the MOS type imaging device and the CCD analog shift register. , a second gate for storing a temporary signal, a third gate located between the first gate and the second gate to control charge transfer, and between the second gate and the input gate of the CCD analog shift register. A solid-state imaging device characterized by having a fourth gate located at and controlling charge transfer. 2. Solid-state imaging according to claim 1, characterized in that a fifth gate is formed by connecting to the second gate portion, and unnecessary charges are absorbed by a diffusion layer connected to the fifth gate. Device.