JPS5925302B2 - Control method for multi-tiered storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION An information processing device cannot achieve sufficient performance if data requested by a central processing unit is transferred from a slow main storage device each time.

Therefore, by placing a low-capacity but high-speed buffer storage device that can synchronize with the speed of the central processing unit between the central processing unit and the main memory device, it is usually possible to transfer data from the buffer storage device at high speed. . This method is called a buffer storage method. The low capacity of the buffer storage device is based on the ubiquitous nature of the program, and due to the nature of this program, the data in the main storage device is stored as a copy in the buffer storage device, thereby meeting the demands of the central processing unit. probability that the data to be stored does not exist in the buffer storage (NIBR: noti)
nBufferRatlo) can be kept within 10%. The data correspondence between the main memory and the buffer memory is dynamically exchanged so that the data most needed by the central processing unit at that time is present in the buffer memory.

The most widely used buffer storage system at present is a two-level hierarchical storage system, which is one type of multiple storage system.

As a multi-layered storage system, an n-level hierarchical storage device can generally be considered. In the buffer storage system, n=1 for the buffer storage device and n=2 for the main storage device. FIG. 1 shows part of an n-level hierarchical storage device, where Mi+1, Mi, Mi
-1 storage device is illustrated.

l is n-1<1<1, and M6 is considered a central processing unit. The data correspondence between each storage device is temporarily Mi-M
The data amount between i-1 is called a head nok, and the data amount between Mi-Mi+1 is called a line. Here, the line generally consists of several blocks. (In the figure, it consists of four blocks.) Data transfer between storage devices is performed according to data requests. For example, when Mi-1 requests block A3 from Mi, Mi requests that the line A containing the requested block is
If line A has not been captured yet after checking whether it exists in , it requests line A from Mi+1, transfers line A from Mi+1 to Mi (line transfer), and then transfers block A3 from Mi to Mi-1 (line transfer). transfer) and completes the data transfer process. For store processing from Mi-1, there is a so-called store-through method in which data is updated up to the storage device of Mi+1 every time a store request occurs, but in this method, even if the store data exists in Mi, it cannot be refreshed up to Mi+1. Therefore, it can be said that the hierarchical storage method does not fully demonstrate its advantages for store processing.

In contrast, the so-called swapping method aims to improve the speed of store processing by completing the processing by updating the data in Mi when store data exists in Mi.
Generally, in the swapping method, if the store data does not exist in Mi, line transfer is performed from Mi+1,
After that, data is updated on Mi.

In the swapping method, the data of Mi+1 and Mi do not necessarily match. In order to display this mismatched line, generally a 1-bit identification latch (change bit) is provided for the line of Mi, and the change bit is set to ``1'' every time a store operation is performed on the line. When a transfer request occurs, a replacement entry is determined using a predetermined algorithm, but if valid data is stored in the entry and the change bit is ``1'', the line is set to Mi+1 prior to line transfer. Swap・
By going out, the unupdated line of Mi is updated. Although the swapping method can be easily applied to buffer storage systems, it has not been widely adopted in conventional buffer storage systems. One of the reasons for this is that swap out has a large overhead. SUMMARY OF THE INVENTION An object of the present invention is to provide a means for reducing the amount of data transferred due to swap-out, which is essential to the swapping method of a multi-layered storage system of an information processing device.

The present invention adds the change bits that were conventionally added to the line correspondences of the storage device Mi to the block correspondences, so that when swapping out, only the blocks indicated by the change bits are swapped out without swapping out all lines. - A feature is that a table is installed that has a bit that indicates whether or not an entry has been rewritten in units of further subdivisions in order to write out the entry.

FIG. 2 is a detailed block diagram of FIG. 1 illustrating an example of memory mapping.

The storage device Mi+1 is divided into lines of CpXRx entries, and the storage device Mi is divided into lines of CpXRy entries such that line A of column C2, row R, of Ml+1 is divided into lines of CpXRx entries.
The rows C and R2 of i are arranged in column correspondence, but which row they correspond to is determined depending on the usage status of the rows of Mi. Generally X>y. On the other hand, the storage device Mi-1 is divided into blocks of Cq×Rz entries, for example, block A3 in line A of column C2 and row R2 of Mi is divided into blocks of entries Cq×Rz.
corresponds to Generally, Pzz and multiple columns of Mi are M
Corresponds to 1 column of i-1. The rows used vary depending on the usage of the block. x>y>z and M.O.
When , it is generally considered that Q=1 and z=1. When a swapping method is adopted between Mi and Mi+1 as a store control method, compared to the conventional method, each entry of Mi has a
It is the same that it has an address table that stores which memory area of +1 corresponds to, but in the present invention, change bits, which previously corresponded to lines, are subdivided and correspond to blocks. It was a characteristic of

FIG. 3 is a logic block diagram of the storage device Mi control section showing a detailed embodiment of the present invention. 1 is a memory request address where the memory request address from the storage device Mi-1 is stored.
In the register, the address consists of a tag address part T1 a line address part L1 a block address part B.

Line address decoders 2 and 6 output select signals corresponding to the columns of address table 3 and change bit table 7, respectively.

3 is an address table in which the upper bits of the memory request address, that is, the tag address, is registered, and it displays the data correspondence between Mi+1 and Mi. In this example, in order to facilitate the following explanation, the address table is 4 columns x 2 rows. It consists of 8 entries.

4 compares the tag address read from the address table with the tag address of the memory request address in an address comparison circuit corresponding to the row of the address table.

Reference numeral 5 denotes a control circuit that outputs various control signals according to the result of the address comparison in 4, and outputs control signals Sl, S2, etc.

The control signals Sl and S2 correspond to the rows of the address table and indicate the match result of address comparison or replacement.
Depending on the result of a row determining circuit (not shown), one of S1 and S2 is set to "1". Numerals 7 to 11 are characteristic logic circuits for implementing the present invention, and 7 is a change bit table, which is divided in the same way as the address table 3 and consists of 8 entries in this example, and each entry further has the number of procs. (4 blocks in this example) corresponding to the number of bits.

8 is a change bit storage register in which the contents of one selected entry of the change bit table 7 is stored.

9 is register 1 where the contents of register 8 are stored as is.
0 is a swap out order determining circuit which selects one bit from among the change bits (4 bits in this example) stored in register 9.

11 is a block address decoder.

12 is an encoder which receives control signals Sl and S2 as input, and its output is stored in the upper part of the pair Mi address register 13 to form a row address.

The 13 paired Mi address registers are the row address part,
It consists of a line address section and a block address section.
The refurbishment address of the storage device Mi is stored.

Reference numeral 14 denotes a pair Mi+1 address register, which consists of a tag address field, a line address field, and a block address field, and stores the repair address of the storage device Mi+1.

15 is a block address plus one circuit, and 16 is a register for storing the result, which counts up the block address during line transfer.

The operation when a store request is generated from the storage device Mi-1 will be described below.

Note that the operation of the data fetch request, which will not be described below, is the same as the conventional one. When a memory request (store) occurs from the storage device Mi-1, the memory request address that is valid on the address transfer path of 100 is transferred to the request address of 1.
Store in register.

The line address portion of request address register 1 is routed through path 102 to column address decoder 2 to refresh one column of address array 3.

Now, if column C2 is selected, tag address A stored in C2×R1 is inputted to the address comparison circuit 4 through path 104, and tag address B stored in C2×R2 is inputted to address comparison circuit 4 through path 105. The tag address of the refurbish request address register 1 is input through path 101 to the other input of the address comparison circuit 4.

The result of the address comparison is input to the control circuit of 5 through paths 106 and 107, and the control circuit of 5 sets the signal line S1 to "1" when there is a match in row 1, and sets the signal line S2 to "1" when there is a match in row 2. ”.The following control differs depending on whether or not a match is detected by the address comparison circuit.

The control when a match is detected as a result of the address comparison in step 4 will be described below.

In parallel with the indexing of the address table at 3, the line address at path 102 is routed to the line address decoder at 6, which refers to the bit table at 7 and is input to the line address at path 108.
, 109, respectively, output change bits corresponding to rows.

Now, if a match is detected in row 1 in the address comparison of 4 and signal line S1 is applied to ``1'''', then 108 change bits (a1 to A4) are valid on path 110. The memory request block address through the encoder is made valid on path 111, and path 110 and path 111 are OR'ed and set in register 8. That is, when a1 to A4 are (0110) binary and the block address is (3) hexadecimal, register 8 contains (1110)2.
Advance is set. The updated change bit created in register 8 is passed through path 112 to the change bit in register 7.
The corresponding entry in the bit table (in this example, C2×
R1).

On the other hand, a store request to the storage device Mi is stored in the upper Mi address register of 13 through the encoder with the matching row number 12 and the path 113.
The line address block address of the memory request address is stored through paths 02 and 103, respectively, and then sent out through path 116. Since the store data width is generally smaller than the block, a mask bit is also sent at the same time as the address is sent, but this is not shown. Next, the control when a mismatch is detected as a result of the address comparison in step 4 will be described.

When the result of the address comparison in 4 does not match, the control circuit 5
After activating a replacement row determining circuit (not shown) and determining the row number to be replaced, one of the signal lines Sl and S2 is applied to "1".

When row 1 is selected and signal line S1 is applied to "1", change bits (a1 to A4) from change bit table 7 are stored in register 8 through path 108 and path 110, and then stored in register 8. After being stored in the change bit of path 114, it is led to 10 swap-out order determining circuits through a path 114.The details of the 10 swap-out order determining circuits will be described later. It is checked whether it is included.

The following controls differ depending on the result of this check. pass 1
14, that is, in this example, a1~
When one or more bits of A4 are "1", 10 swap-out ordering circuits select one of them, encode it, and then pass it through path 115 to the lower order of 13 paired address registers and 14 paired Mi+1 address registers. Stored in the block address section of the block.

There is a path 113 in the upper part of the pair Mi address register of 13.
After the row address is stored through the path 102 and the line address is stored through the path 102, the address is validated on the path 116 and a read request is issued to the storage device Mi.

The upper part of the 14 pair Ml+1 address register contains the corresponding entry of the address table of 3 (in this example, C2×R1)
through paths 104 and 107,
The line address is stored through path 102.

When reading from the storage device Mi is completed, in order to swap out the read data to the storage device Mi+1, the address stored in the 14 paired Mi+1 address registers is made valid on the path 118 and a store request is made to the storage device Mi+1. Send out. When a store operation is started in storage device Mi+1, the 1D swap-out order determination circuit makes the selected change bit valid on path 119 and sets the 1 bit indicated by path 119 of register 8 to "0". That is, a1 ~If A4 is (0110) binary and (0100) binary is output to path 119, the contents of register 8 will be A.
2 is set to (0010) binary. below,
The above operation is repeated until all 0s are detected in the 10 swapout order determining circuits. When all 0s are detected in the 10 swap-out order determining circuits, the block address part of the 1 memory request address is stored in register 8 through decoder 11 and path 111 to form a new change bit.

Subsequently, the new change bit is stored in the corresponding entry of the change bit table at 7 via path 115. In parallel, replacement in address table 3 is performed as in the conventional case. That is, the upper tag address of the memory request address 1 is stored in the corresponding entry of the address table 3 through the path 101. Next 1
After the memory request address of is stored in the 14 pairs of M1+l address registers through paths 101, 102, and 103, it is validated on path 118 requesting a line transfer to storage device Mi+1.

In this example, four lines are transferred sequentially starting from the request block. On the other hand, the block address is set in the pair M1 address register of 13 through path 103. Other bits are retained. After the first memory read is merged with the store data from storage device Mi1, the contents of the 13 paired Mi address registers are made valid on path 116 and written to storage device M1. request. In the remaining blocks, the transferred data from the storage device Mi+1 is written to the storage device Mi as is.

At this time, the block address part of the 13 paired Mi address registers is 15 +1 circuit, 16 register, and path 12.
Each time one block is transferred through 0, it is counted up. FIG. 4 shows a characteristic logic circuit of the present invention.
This figure shows the details of the swap-out order determining circuit.

The swap-out order determination circuit 10 receives the change bit (consisting of 4 bits in this example) of the path 114 as input, and connects four inverters 10-1 to 10-4, 10-5
Consists of a swap-out ranking determination circuit consisting of three AND gates of ~10-7, an all-0 detection circuit consisting of AND gates of 10-8, and an encoder consisting of OR gates of 10-9 and 10-10. The selected change bit is output to the path 119, the encoded value of the path 119 is output to the path 115, and the result of all 0 check of the change bits is output to the signal line ALLO.

As mentioned above, the advantage of the swapping method, which is one of the store methods, is that it is not necessary to send store data to all multi-tiered storage devices to perform the store operation, and the store operation can be completed quickly. A swap out is required, which can occur with a replacement operation that occurs when the corresponding line does not exist in the storage device.

Conventionally, this swap-out has targeted all lines with a relatively large amount of data, but generally the area in which the store operation has been performed, which is included in the replaced line, is not large. The present invention pays attention to this point and manages the store operation by subdividing lines, so that when swapping out, it is possible to target only the part that truly needs to be swapped out, without having to target the entire line. As a result, the overhead associated with swap-out, which is a disadvantage of the swapping method, is reduced, which in turn contributes to improving the throughput of the information processing device.

[Brief explanation of the drawing]

1 is a diagram showing a memory configuration, FIG. 2 is a diagram showing a more detailed memory configuration of FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. FIG. 1: Memory request address register, 2: Line address decoder, 3: Address table, 4: Address comparison circuit, 5: Control circuit, 6: Line address decoder, 7 Reset bit table, 8: Register (change・Bit), 9: Register (change bit), 10: Swap out order determining circuit, \11:
PROC address encoder, 12: Row address decoder, 13: Pair Mi address register, 14
: pair Mi+1 address register, 15:+1 circuit, 1
6: Register (block address), 100 to 200
: Transfer path.

Claims (1)

[Claims] 1 A copy of part of the information held by the upper storage device is stored in the lower storage device in units of lines (or blocks) consisting of a certain amount of data, a store operation is performed on the lower storage device, and the store is stored in the lower storage device. In a multi-tiered storage device that swaps out the information on the line to the upper storage device when a line is replaced, whether or not a store operation was performed on the lower storage device in units smaller than the unit of the line. a change bit table indicating a change bit table, and when a certain line is replaced, the change bit table is referred to, and only the small unit in which a store operation has been performed in the line is swapped out. method.