JPS5925232B2 - Tone control device for electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Summary of the Invention The present invention relates to a timbre control device for an electronic musical instrument, and in particular to analog voltage information related to a plurality of operators and digital information related to a plurality of switches for controlling the timbre of musical sounds. The present invention relates to a device capable of performing the above processing with a simple configuration.

[2] Recent technological trends With the recent development of semiconductor technology, various electronic components, especially integrated circuit components, can be manufactured at low cost, and various electronic musical instruments using electronic components have been developed in the field of musical instruments. has been done.

Examples of such electronic musical instruments include electronic organs and music synthesizers, and LSIs (large scale integrated circuits) and the like have come to be used in these instruments as well. (3
] PRIOR TECHNOLOGY The present applicant previously proposed the above-mentioned electronic musical instrument in the US Patent Publication (Patent Number: No. 3897709, Name: "ELECTRONIC MUSICALINSTRU").
MENT'', public notice date: August 5, 1975).

This electronic musical instrument has a pitch voltage (KV) corresponding to each key press.
) and a keyboard circuit that generates key press signals (KON) corresponding to key presses and key releases, and the oscillation frequency is controlled by the pitch voltage (KV) and generates a sound source signal with a pitch corresponding to the key presses. a voltage-controlled variable frequency oscillator (hereinafter referred to as VCO), a voltage-controlled variable filter (hereinafter referred to as VCF) that forms the timbre of this tone source signal, and a voltage-controlled variable filter that further forms an envelope of the output musical tone signal of this VCF. Gain amplifiers (hereinafter abbreviated as VCA), and these VCOs,
It is composed of a musical tone forming circuit including an envelope generator (hereinafter abbreviated as EG) that controls the VCF and VCA, respectively, and each of these EGs is supplied with multiple analog control voltages from a control voltage generation circuit (waveform controller). is controlled by the key press signal KON to generate an envelope waveform as shown in FIG. 1b and supply it to the VCO, VCF, and VCA. In VCF, the oscillation frequency is slightly changed to create a sound source signal rich in naturalness, and in VCF, the band characteristics are temporally changed to perform timbre modulation.
In CA, the envelope of musical tones is set by changing the amplification gain to form a musical tone signal with rich musicality, which is appropriately amplified and produced as a performance musical tone by a speaker. The envelope waveform shown in FIG. 1b changes from the initial level (IL) to the attack level (A) between the key press time (t1) and the attack time (AT).
It rises to the sustain level (SL) during the first decay time (DTl) and then decays to the sustain level (SL) when the key is released (T
2), and after the key is released the second decay time (DT2)
This is a voltage waveform signal whose voltage value changes as time elapses, falling from the sustain level (SL) to the initial level (1L).

In the control voltage generation circuit, the above-mentioned IL and AL
, each level such as SL, AT, DTl, DT? A plurality of variable resistors are provided to generate analog control voltages for setting each time, and a switch for adding vibrato effects and switching filter characteristics (switching between low-pass, band-pass, and high-pass filters) is provided. The player sets the timbre of the musical tone by appropriately operating these variable resistors and switches. by the way,
In this case, the information indicating the predetermined operating state of each variable resistor and the information indicating the predetermined operating state of each switch are stored by appropriately storing them in a storage device, and then the stored information in this storage device is read out. A brisset device has been considered that controls musical tones by using
JP-A-49-22925, U.S. Patent No. 37007
Specification No. 84).

However, in conventional brisset devices, the information indicating the operating status of each variable resistor is originally analog voltage information, while the information indicating the operating status of each switch is on/off digital information, and both are in the form of information. Since they are different, they are each treated separately.

Therefore, there was a drawback that the configuration was complicated and large-scale. (4) Purpose of the Invention In view of the above circumstances, the present invention provides an electronic musical sound system that can process both analog voltage information and digital information related to a plurality of operators for controlling the timbre of a musical sound with a simple configuration. The purpose is to provide a timbre control device.

(5) Abbreviations used in the description of the invention Before entering into the detailed description of the invention, a list of abbreviations used in the description of the invention is shown below.

CH... Channel (Ul, U2..., S2 or O~7) AL... All mode designation signal S
L...Select mode designation signal PR
...Produce mode designation signal RET...Reset signal R/R...From ROM to RAM (
ROMtORAM) specification signal WT...Write (Wri)
te) Mode designation signal RD...Read mode designation signal EX...Exchan
ge) Mode designation signal CKO...System clock (
CKl (switchable in WT-RD/other modes)
...Oscillator output clock CKl2...Clock recorded on the card CCl~8
...Channel code CHO (SOHO) ~ CH7 (
SCH7)...Channel timing SHO (PSH
O) ~ SH2O (PSH2O)...Sampling timing EXl~4...Equiset engine mode timing designation signal DO~7...Data code signal ADO~7...Andres code signal 00525 (00-9'''07-25) 0゛゜Sunf 0
Ring output signal WPS... Card protect signal SBO... Card loading signal RSS...
Reverse switch signal WRC...Write/read control signal RS
... Card control device reset signal WC ... Write control signal RCl-2 ... Channel code signal FC ... Finish code detection signal 0A-B ... Coincidence signal [6] Structure of the invention and Function: An embodiment in which the present invention is applied to a music synthesizer will be described in detail below with reference to the drawings.

[6-1] Description of a block diagram of the main parts of the music synthesizer [Fig. 1a] Figure 1a shows a block diagram of the main parts of the music synthesizer.

Keyboard 1 in the figure is an upper keyboard 11, a lower keyboard 12, and a pedal keyboard 13.
, a solo keyboard 14, and each of the keyboards 11 to 14 has a plurality of keys (not shown). Each keyboard 11-1
4, in this embodiment, two sets of tone forming circuits 26 to 27 are provided, for a total of eight musical tone forming circuits 26 to 27. That is, for the upper keyboard 11, there is a musical tone forming circuit 2. , 21 are provided, and each of these circuits 2. , 21 will be referred to as channel O (abbreviated as CH9 or U1) or channel 1 (abbreviated as CHl or U2), respectively, in the following description. Similarly, the lower keyboard 12, pedal keyboard 13, and solo keyboard 14 each have two sets of tone forming circuits 22 (CH2 or L1), 2
3 (CH3 or L2), 24 (CH4 or P1),
23 (CH5 or P2), 26 (CH6 or S1)
, 27 (CH7 or S2). As shown in FIG. 1a, each musical tone forming circuit 2 corresponds to a channel to which the high-tone voltage signal KV or key press signal KON, which is a key output signal from each keyboard 11 to 14, corresponds. ~ Sent to 27. The above voltage signal KV generates a musical tone signal of an oscillation frequency (that is, corresponding to a musical scale) corresponding to the key pressed on each keyboard 11 to 14 by a voltage controlled variable frequency oscillator 3 (V
This is a signal to be generated from CO). The key press signal KON is a key on/off signal generated when a key is pressed or released, and this key press signal triggers each envelope generator (EG) 63 to 66, which will be described later. These EGs output the envelope waveform shown in FIG. 1b similar to the prior art described above. Musical tone formation circuit 2
6 to 27 all have the same configuration, and in this case, the musical tone forming circuit 2 of channel O. The configuration will be explained below.
Musical tone formation circuit 2. is a voltage controlled variable frequency oscillator (VCO) 3 and a voltage controlled variable filter (VC
F) 4, Voltage controlled variable gain amplifier (VCA) 6 (!:
, and envelope generators (EG) 63, 64, and 65 provided corresponding to the VCO, VCF, and VCA. As mentioned above, the VCO generates a musical tone signal of a frequency corresponding to the voltage signal KV of the pressed key.
Send to CF. The VCF extracts a signal having a specific harmonic component from the musical tone signal (that is, modifies the musical tone signal) and sends it to the VCA. The VCA gives a predetermined magnitude (envelope) to the modified musical tone signal and supplies the output signal to an amplifier and a speaker (both not shown) common to each channel, so that the sound corresponding to the pressed key is generated from the speaker. Ru. The above VCO, VCF, and VCA are controlled by control voltage waveforms (envelope waveforms) output from the corresponding EG63, 64, and 65, respectively, and the EG63, 64
, 65 are both triggered by the key press signal KON output from the keyboard, and control signal 0 is output from the tone color control device 7 to each channel CH6 to CH7. −
025. The present invention particularly relates to the timbre control device 7, and the control signal 0 output from the timbre control device 7. -025 is EG63 as mentioned above,
64 and 65 to determine each envelope waveform, and as a result, according to these envelope waveforms, the VC
O, VCF, and VCA are controlled. Note that the control signal is 0. ~05 is the initial level (IL) of the envelope waveform output from EG63, 64, 65.
), attack level (AL), sustain level (SL)
), attack time (AT), first and second decay times (DTl), (DT2), etc. [6-2] Outline description of the timbre control device 7 (FIG. 2) Next, details of the timbre control device 7 will be explained with reference to FIG. 2 and the subsequent drawings.

First, the overall configuration will be schematically explained with reference to FIG.
This timbre control device 7 is a device that can control the performance operation of the music synthesizer according to eight operation modes to be described later.

The timbre setting board (timbre setting device) 16 in the figure is designed to give control signals for creating an envelope waveform to the EGs 63, 64, and 65, and can arbitrarily set the initial level, etc. of the envelope waveform. A plurality of tone-determining element control polyurems (variable resistors) are provided on the substrate. In addition to the tone determining element control polyurethane, a plurality of tone determining element control switches for imparting vibrato effect characteristics and the like to the musical tone signal are also provided on the tone color setting board 16.
Analog information for creating musical tones determined before performance by the musical tone determining element control polyyume and musical tone determining element C control switch on the tone setting board 16 (however, the output of the musical tone determining element control switch is digital information)
is converted into digital information by the A/D converter 17 and sent to the data bus 262, and the magnetic ! card (not shown), and furthermore, from this magnetic card to the RA of the internal storage device.
It is written and stored in M (random access memory) 13. Another internal storage device, ROM (read-only memory I-14, is provided for storing standard tone information. When playing the Music Synthesizer with the standard tone information stored in ROM14, the power supply At the same time as the switch is turned on, the standard timbre information in the ROM 14 is transferred to the RAM 13 via the data bus 262.
Then, when the performance starts, the musical tone forming circuit 2 of each channel CH6 to CH7 among the information stored in the RAM13. 27 used as analog information is sent to the D/A converter 20 via the data bus 262 and converted into analog information. This analog information is then held by the sample hold circuit 21a.
Also, the tone forming circuit 2 for each channel CH6 to CH7 among the information stored in the RAM13.

27 used as digital information is sent to the latch circuit 21b via the data bus 262 and latched. The information stored in the sample hold circuit 21a and the latch circuit 21b is the control signal 0. -025
The tone forming circuit 2 of the corresponding channel. Sent to ~27. In the embodiment of the present invention, the operation mode in which the contents of the ROM 14 are transferred to the RAM 13 at the start of a performance as described above is called a VR (ROM to ORAM) mode.

Further, the operation mode in which the contents of RAM13 are sent to the sample hold circuit 21a or the latch circuit 21b so that the contents can be played is called a performance mode. The R/R mode is one of the features of the present invention, and can be entered immediately by turning on the power switch or operating the reset switch.

Then, by turning on the desired channel switch and tone select switch, which will be described later, the performance mode is entered, and the standard tone information corresponding to the turned on channel switch and tone select switch is stored in RAM13.
It can be read from and played. In this embodiment, it is also possible to switch from a performance using standard tone information to a performance using tone information other than the standard tone information using a tone setting board or magnetic card, or to switch to the opposite performance state, as described below. There is also a feature that allows you to switch with a single touch using a switch or the like. A performance mode using tone color information other than standard tone color information using the above-mentioned tone color setting board is referred to as a PR-WT mode in the present invention. In this mode, the information obtained by operating the tone determining element control polyurethane or tone determining element control switch on the tone color setting board during performance is directly sent to the sample hold circuit 21a or the latch circuit 31b to perform the performance. Note that the analog information output from the sample hold circuit 21a, for example, the signal 0.0 to 001
0 indicates for O channel.

Further, signals CHO~7 are signals specifying channels, and these signals CHO~7 are created by decoding channel codes CCl~3 (these are signals created by the panel control logic 25, which will be described later) using a decoder. be done. Furthermore, the digital signals outputted from the latch circuit 21b, for example 07-20 to 07-25, correspond to seven channels. RAMl3 or ROMl
A tone selector 10 and an address generator 11 are provided in order to designate addresses of 4 and write information to or read information from these addresses. The tone selector 10 has each channel CHO-CH.
8 channel selection switches corresponding to SUL. S
U2. SLl. SLl. SPl. SP2. SSl. S.S.
Eight tone selector switches (abbreviated as TSO-TS7) are provided under the control of each channel selection switch. That is, in this embodiment, RAM13 and R provided for each channel are
The storage area of the OM14 is each divided into eight blocks, and each block stores information for one timbre. Then, if you turn on any tone select switch of any channel, the RAM13 or ROM1 corresponding to this tone select switch is
Address No. 4 is designated by the address generator 11, and tone information is written and read as described above. Note that address signals ADO to AD7 are connected to address bus 2.
61 to RAMl3 and ROMl4, and RAMl5 provided for the EX mode (described later).
The EX mode, which is one of the features of this embodiment, will now be explained.

This EX mode is a mode for exchanging information stored in two programs in the same channel or different channels in the RAM 13. In this mode, the information in each program to be exchanged is first stored in different areas of RAM 15 for temporary storage, and then this information is sequentially transferred to the other party's program. exchange with each other. This EX mode is executed by operating the SELECT switch and EX switch of each mode, which will be described later, as well as the corresponding channel selection switch and tone selection switch. In this way, the arrangement state of tone color information corresponding to the tone select switch can be freely set to the most convenient state during performance. In this embodiment, the tone information set by the tone setting board 16 is further stored in an external memory, for example, a magnetic card, or the tone information thus stored on the magnetic card is read out.
You can store it in AMl3 and use it for performance, or vice versa.
For the purpose of recording information in Ml3 on a magnetic card, a card 1/O logic 22, a card reader 23,
A force reader control logic 24 is provided.

In this embodiment, the tone information set in the PR and WT modes described above is transferred to the card I/O via the data bus 262.
PR- the operation of sending it to the logic 22 and storing it on the magnetic card.
It is called WT mode. In this example, one PR-W
By operating the T mode, information for one tone is stored on the magnetic card. Therefore, when storing information for eight tones (corresponding to information for one channel in this embodiment) on a magnetic card, the information on the tone setting board 16 is Change the setting positions of the musical tone determining element control polyurem and musical tone determining element control switch to obtain the desired tone information, and then operate the write switch (abbreviated as WRITE) to write to the magnetic card 8 times. Repeat. That is, PR-WT mode and P
Perform R-WT mode 8 times in a row. Note that if you have recorded information for 8 tones on 8 magnetic cards by repeating the above operation, and you want to record this information on another magnetic card, you must first R the information on the 8 magnetic cards.
The information for these eight tones can be written into the AMl3 and then recorded from the RAMl3 onto one magnetic card. Further, in this embodiment, as described above, information in the RAM 13 is recorded on the magnetic card, and conversely, information on the magnetic card is recorded on the RA.
When writing to M13, there are cases in which all eight procs of a certain channel are written at the same time, and cases in which it is written in only one proc of a certain channel, so there are three additional operating modes.

That is, in the WT-AL mode, information for eight tones of one channel in RAM13 is recorded on one magnetic card. Further, in the RD-SL mode, information for one tone recorded on the magnetic card is written into an arbitrary block of an arbitrary channel in the RAM 13. Furthermore, RD-AL
In the mode, all information for eight tones recorded on the magnetic card is written to a certain channel of RAM13. In this way, if a large number of desired tone information is recorded in advance on a large number of magnetic cards before a performance, when performing a performance, by selecting a desired magnetic card and inserting this magnetic card into the card reader 23, the desired tone will be generated. Information can be quickly set in the RAM 13, and a performance based on the tone information can be started immediately.

Furthermore, since analog timbre information is converted into digital timbre information and stored in a memory such as a magnetic card, it is easier, cheaper, and more accurate to record and store the timbre information than storing analog timbre information. The memory control logic 12 is a circuit that controls writing of tone color information to RAM13, ROM14, and RAM15 or reading of tone color information, and an address is specified at the time of this write operation or read operation.

The panel control logic 25 includes the above-mentioned R/R mode, performance mode, PR-WT mode, PR-WT mode, EX mode, WT-AL mode, RD-SL mode,
This is a circuit that creates various command signals from signals output from various command buttons and switches operated when executing each of a total of eight types of RD-AL modes.

The generated command signal is sent to each circuit of the timbre control device 7 to control the operation of these circuits. Furthermore, the operation of each circuit of the tone control device 7 is controlled by a clock generator 1.
A reference frequency clock pulse that is constantly output from 8,
It is controlled by various timing signals generated by a timing pulse generator 19 from this clock pulse.

[6-3] Detailed explanation of each circuit in the timbre control device 7 Next, each circuit in the timbre control device 7 of the above embodiment will be explained in more detail with reference to the drawings from FIG. 3 onwards.

FIG. 3 is a plan view of the operation panel 26 provided near the keyboard 1. The operation panel 26 is provided with various command switches that are operated respectively when executing the eight operation modes mentioned above. Read switch (READ) 27
is operated in the RD-SL mode or RD-AL mode, and at this time the tone information in the magnetic card is written into the RAM 13. The write switch (WRITE) 28 is operated in the PR-WT mode or WT-AL mode, and at this time the tone information in the RAM 13 is written to the magnetic card. EXCHAGE switch (EXCHAGE) 2
9 is a switch operated in the EX mode. The reset switch (RESET) 30 is a switch operated at the start of the R/R mode, and the reset signal RET output at this time resets the flipflops, counters, etc. included in each circuit in FIG. 2 to the initial state. is set. All select switch (ALL-S
As shown in the figure, ELECT) 31 is a slide switch, and if this switch 31 is set to the right side, a select command (SL) will be generated, and if it is set to the left side, an all life + (AL) will be generated.

Therefore, the all select switch 31 is
WT mode, RD-SL mode, WT-AL mode, R
Operate in D-AL mode and EX mode. The production switch (PRODUCE) 32 is a switch operated in the PR-WT mode. As mentioned above, the channel selection switch 33 has 2 channels for each type of keyboard 1.
There are 8 in total. These channel selection switches SUL. SU1, . . . , SS2 are used while being turned on two at the same time during EX mode operation.
The switches other than the all-select switch 31 can be implemented as push-on or push-off type switches. This type of switch is a switch that is turned on the first time it is pressed and turned off the second time, and these states are repeated thereafter. Especially readout switch 2
7. Write switch 28, I/O switch 29,
The reset switch 30 may be of the self-resetting type.
6-4] Detailed Description of Panel Control Logic 25 Next, the circuit configuration of the panel control logic 25 will be explained with reference to FIGS. 4 and 5.

First, a circuit for generating various command signals will be explained with reference to FIG.
The all-side output end of the all-select switch 31 is connected to the other end of a resistor R1, one end of which is grounded, and to the input end of an inverter 34. As a result, when the all select switch 31 is set to the all side, 2
An output voltage of 11" level of value logic is generated, and this signal is called AL. Also, when the all select switch 31 is set to the select side, the output of the resistor R1 disappears, so the output terminal of the inverter 34 has a "1". A level signal is generated.This signal is called SL.Product use switch 3
The output end of R2 is grounded to the other end of a resistor R2 whose one end is grounded. Therefore, when the production switch 32 is turned on, a voltage is generated across the resistor R2, and this signal is
Call it R. Next, explaining the circuit for generating the signal RET (5R/R), the output terminal of the power switch 35 is connected to the input terminal of a D-type flip-flop 36 via a capacitor C1.

In the following explanation, the flip-flop will be abbreviated as FF. Also, the output terminal of the reset switch 30 is a diode D.
1, one end of the resistor R3, and the input end of the D-type FF 36. The anode S of the diode D1 and the other end of the resistor R3 are both grounded. In addition,
The power supply voltage is a direct current positive voltage +V. The D-type FF 36 is driven by a clock pulse CKO generated by a clock generator 18, which will be described later. The set output terminal Q of the FF36 is a D-type FF38 included in the pulse h generation circuit 37.
and the first input terminal of the NOR gate 39. The reset output terminal Q of the D-type FF 38 is connected to the second input terminal of the NOR gate 39, and the NOR gate 3
The output terminal of 9 is connected to the set input terminal S of the RS type FF4O. The D-type FF 38 is driven by the clock pulse CKO, and the RS-type FF 4O is driven by the output pulse CKl of the oscillator of the clock generator 18. (This clock pulse CKl is used in each circuit in the device. This clock pulse CXl will not be mentioned in the following explanation.) Also, the timing signal CH7 is input to the D-type FF4l, and the set output terminal of this FF4l is inputted. is connected to a first input terminal of AND gate 42. A signal FC is input to the second input terminal of the AND gate 42. The output terminal of the AND gate 42 is D type F.
It is connected to the input terminal of F43, and the set output terminal of this FF43 is connected to the set input terminal of the RS type FF4O. Timing signal CH7 is a signal created from channel code signals CCl to CC3.
~ Occurs when all "11" are output from CC3.
These signals CCl to CC3 provide timing to channel 7. A signal FC (finish code) is a signal output immediately before the program counter of the address generator 11 is reset periodically. Furthermore, both FF4l. Both 43 are clock pulse CK
6. Here, the operation of the circuit for generating the signals RET and R/R will be explained with reference to the time chart of FIG.

Turn on the power switch 35, then turn on the reset switch (
9) is pressed once, the signal RET is output from the set output terminal Q of the D-type FF 36 with a slight delay from the output of the reset switch 30 by the ClR3 time constant circuit. Further, when the signals at both input ends of the NOR gate 39 are both at the IO'' level, the RS type FF4O is set and the signal R/R is output.On the other hand, the output states of the timing signal CH7 and the signal FC are shown in FIG. Therefore, both signals CH
When 7 and FC are both "1", a signal "1" is output from the AND gate 42, and this signal is delayed by the FF 43 and input to the reset input terminal R of the FF 4O. At this time, the signal R/R is inverted and becomes the "1" level. Next, a circuit for generating signals WT, RD, EX, etc. will be explained. The output end of the write switch 28 has one end connected to the ground, the other end of the resistor R4, the set input end of the RS type FF 47, and the 3-input 0R terminal.
It is connected to a first input terminal of gate 48 . The set output signal of FF 47 is signal WT. The output end of the readout switch 27 has one end grounded and the other end connected to a 3-input 0R resistor.
It is connected to the first input terminal of the gate 46 and the set input terminal S of the RS type FF 49. Also, the set output terminal Q of FF49
is connected to the first input terminal of AND gate 59. This A
The set output terminal Q of the FF 4O is connected to the second input terminal of the ND gate 59 via an inverter 58. AND
The output of gate 59 is called signal RD. The output end of the current switch 29 is connected to a resistor R6 whose one end is grounded.
Other end, third input end of 0R gate 46.48, resistor R7
The other end of the capacitor C2, which has one end grounded, and the input end of the D-type FF 5l included in the pulse generation circuit 50 are respectively grounded via the pulse generating circuit 50. Further, the set output terminal Q of the FF 5l is connected to the input terminal of another D-type FF 52 and the first input terminal of an AND gate 53. Further, the second input terminal of the AND gate 53 is connected to the reset output terminal Q of the FF 52, and the output terminal thereof is connected to the set input terminal of the RS type FF 55. Both of the above FF5l. 52 is also clock pulse CK6
Driven by. Further, the set output terminal Q of the FF 55 is connected to the reset input terminal R of a 5-bit shift register via an inverter 56. This set output signal of FF 55 is called signal EX. The shift register 57 is driven by a pulse signal PSH2O generated by the timing pulse generator 19, which will be described later, but the initial state of the shift register 57 is that all bits from the 1st bit to the 5th bit are "0". be. Here, when a pulse is outputted from the pulse generating circuit 50 mentioned above, the FF 55 outputs an EX signal "B" and resets the shift register 57 via the impurator 56.Then, the pulse signal PSH2O is output. Each time a bit is input, the content "1" of the shift register 57 is shifted to the next bit position, such as the 1st bit, the 2nd bit, the 3rd bit, etc., and the content of the 5th bit becomes 11". The FF 55 is reset via the 0R gate 54, which causes the inverter 5 to
Since the output of 6 becomes 1, this shift register 57 is reset and returns to its initial state. Here, shift register 5T
The 1st, 2nd, 3rd, 4th and 5th bit output signals of EXl. EX2. EX3. EX4-. It is called EX. FIG. 7 shows each of the above signals EX. EXl~EX5. Shows the output status of PSH2O. In this embodiment, the output interval of the signals PSH, O, that is, the pulse width of each signal EX, -EX4 shown in FIG. 7, is equal to the length of information for one tone color (20 bits). As mentioned above, the signal EX5 is used together with the reset signal RET as a signal for resetting the FF 55. FF47 and FF49 are further reset by another reset signal.

That is, the output terminal of reset switch 30 is connected to the input terminal of OR gate 45. The signal FC is also connected to the second input terminal of the 0R gate 6. Furthermore, signal SL and signal 0A
-B is input to the AND gate 44, and the output SL-0A=B of this AND gate 44 is input to the CR gate 45. The output of this 0R gate 45 is inputted to the third input terminal of 0R gate 46 or 0R gate 48, and is inputted to the set input terminal R of each FF47 or FF48 via this 0R gate 48, and is inputted to each set input terminal R of FF47 and FF49. Set it. Next, the operation when each of the above-mentioned switches 27 to 29 is operated will be explained.

First, when the write switch 28 is pressed once, the FF 47 is set to the set state by the voltage appearing on the other end of the resistor R4.
The set output signal of F47, that is, the signal WT becomes "1". Even if the write switch 28 is not pressed, the signal W remains
T-beam 7 is held. The output of the reset switch 30, the signal FCl signal SL. O
A-B1 readout switch 27 output,
When any one of the 9 outputs is inputted, the FF 47 enters the reset state, and the signal WT is inverted and becomes "0". Next, in the case of the read switch 27, set this switch 27 to 1.
When the button is pressed twice, the FF 49 is similarly placed in the set state, and its set output signal becomes "1".

In this embodiment, generation of the signal RD is prohibited while the signal R/R is being output, so even if the readout switch 27 is pressed while the signal R/R is being output, the AND gate 59 remains closed and the signal RD is not output. Not done. If the signal R/R is not output, the AND gate 59 opens, and the signal RD becomes "1" by the set output signal of the FF 49, and this state is changed to the FF 49.
It is held until 49 is set. The FF 49 enters a reset state in which either the output of the reset switch 30, the output of the signal FCl signal SL-0A=B1 write switch 23, or the output of the current switch 29 is input to the reset input terminal R, and the signal RD is input. becomes "0". Also, if you press the Ixtrange switch 29 once,
As shown in FIG. 7, the capacitor C2 is gradually charged, and when the charging voltage reaches a predetermined value, a "1" signal is output.
It is input to type FF5l.

At the same time as the next clock pulse CKO is input to the FF 51, one pulse is output from the AND gate 53, and this pulse is sent to the set input terminal S of the flip-flop FF 55. Therefore, the signal EX is output from the set output terminal Q of the FF 55. At the same time, this signal EX is applied to the shift register 57 via the inverter 56 to the set input terminal R? C″O″
It is sent as a signal to release the reset state and start the operation of the shift register 57. As described above, the shift register 57 is driven by the pulse signal PSH2O and sequentially outputs each of the timing signals EX1 to EX5. These timing signals EX1-EX4 are used in the change mode and control writing and reading of information of two programs to be exchanged into and from memories (RAM13, RAM15). The signal EX5 also becomes FF when the signal RET is output.
55 is set, and its set output is "0" (5) The "0" signal of the lever is inverted by the inverter 56 and applied to the shift register 57's set input terminal R, and as a result, the shift register 57 is set, initial state,
In other words, all contents become "0". The signals 0A-B are generated by the address generator 11, and are output when the contents of the two inputs of the comparator 161 match, as will be described later. Next, a circuit for generating channel codes CCl to CC3 and channel timing signals SCHO to SCH7 and CH7 will be explained with reference to FIG.

The four gate circuits 60, 61, 62, 63 (hereinafter also referred to as gate circuits Gl.G2.G3.G4) have the same configuration, and each has a junction type, N-channel FET (
The gate terminals of the three FETs are commonly connected.

When signals are applied to these gate terminals, gate circuits G1 to G4 are opened. Card I/O logic 22 (
Channel code RC output from (see Figure 2), ~
RC3 (signal read from the magnetic card) is input to the drain terminal of the corresponding FET in the gate circuit G1, and when there is an input signal to the gate G of the gate circuit G1, the channel code CCl~ in the device is input from the corresponding source terminal.
Output as CC3. In addition, each FE of the gate circuit G1
The source terminal of T is connected to the input terminal of a 3-input AND gate 76. Therefore, when the 3-bit channel codes RCl to RC3 are both "1" (channel 7), a signal is output from the AND gate 76. , this signal becomes the channel signal CH7. Gate G of gate circuit G1
The output of AND gate JMoV is added to , but this AN
The input signals of the D gate are the signal RD-AL (that is, the AND of the signal RD and the signal AL) and the output of a NOR gate 70, which will be described later.

The NOR gate 70 includes the eight channel selection switches SUL. SU2. SLl. SL2, SSl. S2
Therefore, when no channel selection switch is pressed, the
A signal from 0 to "1" level is output. That is, the gate circuit G1 selects the AND gate J mode when the all select switch 81 is set to the all side, the readout switch 27 is pressed, and neither channel selection switch is pressed, that is, in the RD-AL mode. An output signal is applied to the gate to open it, and channel codes CCl to CC3 are output from the gate circuit G1. Further, when channel codes RCl to RC3 are channel 7, channel signal CH7 is output as described above. Gate circuit G2 is gate circuit Gl. G3. When G4 is not operating, that is, in the R/R mode and the playing state after this R/R mode, it is opened and the channel code C is
Cl to CC3 and a channel signal CH7 are output.

That is, the signal FC and the signal R/R are input to an AND gate 65 of a pulse generating circuit 64, and the output of this AND gate 65 is led to an octal counter 69 via an 0R gate 68, and becomes a clock pulse signal for this counter 69. . Further, a signal obtained by inverting the signal R/R by an inverter 66 and a signal PSH2O are input to an AND gate 67,
The output of this AND gate 67 is led to a counter 69 via the 0R gate 68, and becomes a clock pulse signal for this counter 69. Further, the counter 69 is reset by the reset signal RET. Each digit output terminal of the counter 69 is connected to the tray 7 terminal of the corresponding FET of the gate circuit 61, and the source terminal is connected to the AND gate 76. The gate of this gate circuit G2 is connected to the output terminal of the NOR gate 78;
8, the output of the AND gate J and V, and the signal EX2. The signal RD/SLl signal WTl signal EXl.
The outputs of EX4 and AND gate 88 are added. The AND gate 88 is connected to the signal RD-AL and the inverter 8.
The output of NOR gate 70 via 2 is added. Therefore, operations are performed according to the time chart shown in FIG. 8A. That is, in the R/R mode, when the reset switch 30 is pressed, the counter 69 is reset to an initial state, and its contents become O. Furthermore, when the reset switch 30 is released, the signal RET becomes "0" and at the same time the signal R/R becomes "1", resulting in the signal FC
Each time FC is output, a signal synchronized with signal FC is output from AND gate 65, and this signal is applied to counter 69 via 0R gate 68 as a clock pulse.

Therefore, the counter 69 starts operating, and the output of each digit is sent to the gate circuit G2. At this time, the output "1" of the NOR gate 78 is applied to the gate G of the other gate circuit G2.
(Because in this R/R mode, all three inputs of the NOR gate 78 are "0".) is added, and the j gate circuit G2 is opened. Therefore, the output of the counter 69 is output as channel codes CCl to CC3. Then, when the R/R mode ends, AND gate 67
opens, and from this point on, the counter 69 receives the pulse signal PSH2O.
It is driven by. (See Figures 6 and 8B) Of course, the gate circuit G2 is also connected at this time, and the output of the counter 69 is the channel code C as in the R/R mode.
It is output as Cl to CC3, and the performance becomes executable.
Further, when the content of the counter 69 becomes 7 "111", the channel signal CH7 is outputted from the AND gate 76. The gate circuit G3 is operated during read operation of musical tone information from the magnetic card (i.e., in RD-SL mode and RD-AL mode) or write operation (i.e., in WT-SL mode and WT-AL mode). The channel codes CCl to CC3 corresponding to the selected channel selection switches SUL to SS2 and the channel signal CH7 are output.

In addition, the gate circuit G3 is the gate circuit G4 in the EX mode.
Code signals CCl to CC3 and channel signal CH7 corresponding to the channel selection switches sequentially operated
Output. In this embodiment, as described above, the channel selection switch SUL. SU2...Two SS2 are operated in EX mode. Also provided are respective priority encoders 71 and 72 which determine the priority of the pressed channel selection switch. Therefore, when two channel selection switches are pressed at the same time, the channel codes CCl to CC3 corresponding to the switch with the highest priority are assigned to the gate circuit G3.
The channel codes CCl to CC3 corresponding to the switches with lower priority are output from the gate circuit G4. To explain these configurations, each channel selection switch SUL. The output signals of SU2...SS2 are input to corresponding input terminals 0.1...7 of the priority encoder 71.

At the same time, each channel selection switch SUL. SU2...
The output signal of SS2 is input to manual terminals 7.6...0 which are obtained by reversing the order of the other priority encoders 72.
The priority encoder 71 electrically gives priority to the switch with the smaller channel number, and the priority encoder 72 gives electrical priority to the switch with the smaller channel number. Output terminal Q of priority encoder 71. ．． Ql. Each output signal from Q2 is input to gate circuit G3. In addition, the output terminal QO of the other priority encoder 72. Ql. Each output signal from Q2 is input to gate circuit G4 via inverters 73, 74, and 75, respectively. Gate circuit G3 or G4
Each output signal of the aforementioned 0R gate 80 or 0R gate 81 is input to the gate. Furthermore, the output terminal Q of the priority encoder 71. ．． Q. The output signal from Q2 is input to a decoder 79, decoded by this decoder 79, and outputs a corresponding channel timing signal SCHO-SCH.
7 is created. Note that the output of the NOR gate 70 is applied to the inhibit input terminal of the decoder 79. Therefore, this decoder 79 is prohibited from operating when no channel selection switch is selected. With the above configuration, when one channel selection switch, for example switch SU2 (channel 1), is pressed, the output signal of this switch SU2 is sent to input terminals 1 and 6 of priority encoders 71 and 72, respectively.

Therefore, the output signal from the priority encoder 71 is "001".
(Binary number: QO-1, Q, -0, Q2=0) is obtained and input to the gate circuit G3. Also, the priority encoder 72
An output signal "110" is obtained from the gate circuit G4, but this signal is inverted by the corresponding inverter 73, 74, 75 to become a signal "011", which is input to the gate circuit G4. When one channel selection switch is operated in this way, each gate circuit G3. The same signal is input to G4. However, since gate circuit G4 is opened only in EX mode (because gate G has signals EX2.E
channel codes CCl to CC3 by gate circuit G3 when not in EX mode.
is output. In the above case, the output of the NOR gate 70 is "0", and this "0" signal releases the inhibition of the decoder 79, so the decoder 79 operates and the channel timing signal SCH1 is output. When two channel selection switches, for example, switch SU2 (channel 1) and switch SP1 (channel 4), are pressed in the EX mode, the output signal of switch P1 is input to priority encoder 72.

Therefore, the output of the priority encoder 71 is "001", and this signal "001" is input to the gate circuit G3. On the other hand, the output of the switch P1 is applied to the input terminal 3 of the priority encoder 72, so its output becomes "011".

Therefore, this output "011" corresponds to the inverter 7.
3.74.75, it becomes "110" and is input to the gate circuit G4. That is, gate circuit G3
Since the switch SU2 (channel 1) is selected for the gate circuit G4, and the switch SP1 (channel 4) is selected for the gate circuit G4, the signal EXl. When outputting EX4, gate circuit G3 is opened and channel codes CCl to CC3 corresponding to channel 1 are output. Also signal EX
2. When EX3 is output, gate circuit G4 is opened and channel codes CCl to CC3 corresponding to channel 4 are output. That is, EX mode is executed. In addition,
When two channel selection switches are pressed at the same time in a mode other than EX mode, the one with the lowest priority is gate circuit G.
4 is given its output signal, but the gate circuit G4 is
Since it is closed except in the X mode, it is virtually ignored and is the same as not being operated. [6-5] Detailed Description of Clock Pulse Generator 18 and Timing Pulse Generator 19 Next, the configurations of the clock generator 18 and timing pulse generator 19 will be described with reference to FIG. 9.

Reference pulse output from oscillator 85 (frequency 100k
Hz) CKl is input to a frequency divider 86 and a NAND gate 87 in addition to being used as a clock pulse for various circuits (flip-flops, etc.) in this embodiment. Frequency divider 8
6 outputs a pulse signal with a frequency of 390Hz, and
It is input to AND gate 88. Signal WT. The output of the NOR gate 92 which takes RD as an input signal is sent as a regulation signal to the NAND gate 87. Also NAND
The signal WT is input to the gate 88 as a regulation signal. Furthermore, the clock pulse CKl read from the magnetic card
The AND gate 90 which takes 2 as an input signal receives the signal RD as a regulation signal. And the above NAND gate 8
7.88 output is NAND gate 89.0R gate 91
and the output of the AND gate 90 is outputted as the system clock CKO via the 0R gate 91. The frequency divider 86 consists of a counter circuit, and when the reset signal RET is input to the reset terminal R, the frequency divider 86 is reset and stops operating. With the above configuration, during output of signal RD (RD.SL mode, RD-AL mode), A
When the ND gate 90 is deregulated, the clock pulse CKl2 read from the magnetic card becomes the system clock CKO.
is output as While the signal WT is being output (WT-SL mode, WT-AL mode), the NAND gate 88 is deregulated and the frequency 390 Hz is output from the frequency divider 86.
The pulse signal is output as the system clock CKO. Also, both signals WT. When RD is not output (R
/R mode, performance mode, PR-WT mode, EX mode), the output of the NOR gate 92 becomes '1f,
The output pulse (frequency 100 KHz) of oscillator 85 is output as system clock CKO. As mentioned above, the system clock CKO is switched depending on the mode.
Next, a circuit for generating sampling timing signals SHO (PSHO) to SH2O (PSH2O) will be explained.

System clock CK output from 0R gate 91
O is a D-type FF98 and a 20-bit shift register 9
In addition to being used as a drive pulse 9, the signal is also input to an inhibition signal generating circuit 94.

The prohibition signal generation circuit 94 includes a resistor R8 connected to the output end of the 0R gate 91, and an inverter 9 connected to the other end of this resistor R3.
a NAND gate 96 to which the first input terminal is connected via 5;
, a capacitor C3, one end of which is connected to the other end of resistor R8, and the other end of which is grounded. A second input terminal of NAND gate 96 is directly connected to an output terminal of 0R gate 91. Output of NAND gate 96 (inhibition signal 1NH)
is AND gate 1000 to 1 in AND gate group 100
0020 is input as a control signal. Also these AN
D gates 000 to 10019 each have the first bit, second bit, . . . of a 20-bit shift register 99.
, the contents of the 20th bit are input. AND gate 10
The FF98 reset output signal is input to 020. This reset output signal is called PSH2O. Furthermore, the contents of the 20th bit of the shift register 99 and the output of the 0R gate 93 are both passed through the NOR gate 97 to F
The reset output signal of this FF 98 is input to the first bit of the shift register 99.

The 0R gate 93 receives the reset signals RET and RS as input signals, and these reset signals RET and RS are also used as reset signals for the shift register 99. Each output signal of the above AND gates 00, ~10020 is a sampling timing signal SHO-SH2O.
It is called. In addition, each output of the 1st bit, 2nd bit, . . . , 20th bit of the shift register 99 and the D-type FF 9
Each output of 8 is a sampling timing signal PSH.
It is called O-PSH2O. 4. The set signal RS mentioned above is a signal generated by the card control logic 24 (see FIG. 2).

Next, the operation of the above circuit will be explained with reference to the time charts of FIGS. 10 and 11.

The 0R gate 91 outputs the system clock CKO corresponding to one of the operating modes as described above.

At this time, when the threshold set signal RET or RS is output, all contents of the shift register 99 are cleared. When the reset signal RET or RS disappears, NOR
Since the two inputs of gate 97 are both 10'', this NO
A "1" signal output from the R gate 97 is applied to the FF 98. A signal is input to the FF 98, and the reset output of the FF 98 remains in the "1" state until the next system clock CKO is output, and the signal PSH2O is output. By the way, as shown in FIG. 10, the prohibition signal generation circuit 94 outputs N from the time the system clock CKO is input until the potential of the capacitor C3 reaches a predetermined value.
The output signal 1NH of the AND gate 96 becomes "0" level, and when it reaches a predetermined value, the signal 1NH is inverted to the 11I level and remains "1" until the next system clock CKO is output.
``The operation that maintains the level is repeated. Therefore, F
While the F98 reset output is "1", the AND gate 10
A signal SH2O synchronized with the signal 1NH is output from 020.

When the next system clock CKO is output, the FF98 reset output/712 is transferred to the shift register 99.
is input to the first bit of AND gate 100 at the same time.
Similarly, the signal SHO is output from 0. In this way, each time the system clock CKO is output and the signal 1NH is generated, the signals SHl, SH2, . . . , SH are sequentially generated.
l, is output. Further, the signal PSH1 outputted from the 20th bit of the shift register 99 is outputted from the time when the signal SH18 disappears until the time when the signal SH19 disappears. When this signal PSHL, is output, the output of the NOR gate 97 becomes "0", and the input of the FF 98 becomes "0". From this point on, the second output of the system clock CKO causes the reset output of the FF 98 to become "0". ``It becomes 1f. Thereafter, the above operation is repeated. 6-6] Detailed Description of Tone Setting Board 16 and Iy/D Conversion Device 17 Next, the detailed configuration of the tone setting board 16 and A/D conversion device 17 will be explained with reference to FIG.

Each output terminal of 20 musical tone determining element control variables TVRO-TVR19 consisting of variable resistors is connected to the drain terminal of the corresponding FET1010 to 1011 in the gate group 101, respectively. The above FETlOlO~10
The source terminals of 119 are connected to each other and to the input terminal of A/D converter 109 via buffer amplifier 107 . Furthermore, the gate terminals of FETlOlO~1011 are connected to the corresponding output terminals 0, 1, . . . of the decoder 102.
, 19. A signal representing the contents of the 21-decimal counter 103 is input to the input terminal of the decoder 102. The 21-bit counter 103 receives the output signal SKl of the 21-bit parallel/serial shift register 116 through an inverter 105 at its clock input terminal, and is driven by this signal SKl.

In addition, in order to cause the reset signal RET of the 21-decimal counter 103 or the content of the 21-decimal counter 103 to be reset to 21, the reset signal RET is sent to the 0R gate 1.
06 to the reset input terminal R, and 2
The outputs of the 1st, 3rd, and 5th digits of the 1-digit counter 103 are ANDed.
It is sent to the reset input terminal R via gate 104 and 0R gate 106. The A/D converter 109 is driven by the system clock CKO, and the signals RET and SKl are input to the master reset input terminal MR of the 0R gate 108.
is input and reset via .

Further, the signal EOC outputted from the end of conversion terminal EOC of the A/D converter 109 every time the conversion of one data is completed, that is, every time the system clock CKO is outputted nine times, is outputted via the 0R gate 110. It is input to the start convert terminal SC. Also, the set signal RET is input to the input terminal D and the reset input terminal R of the D-type FFll, and the set output of the FFll is set to 0R.
The signal is inputted to the terminal SC of the A/D converter 109 via the gate 110. FFll is the system clock C
Driven by KO. The parallel 8-bit digital signal output from the A/D converter 109 (that is, the information sequentially taken in from the musical tone determining element control polygons TVRO-TVRl9) is sent to a two-stage latch circuit 112.11.
3 to the corresponding input terminal A of the select game 115.
,A,,...,A7. Latch circuit 112
is driven by the signal EOC, and its output is now called A/D1. The latch circuit 113 is driven by the signal SKl, and its output is called A/D2. Each output terminal Q of the select game 115. -Q7 is connected to one shift register each having a capacity of 21 bits. If these eight shift registers are called a shift register group, the output signal of the select gate 15 input to the shift register group 118 is shifted to the right every time the system clock CKO is input to the shift register group 118. , when the 22nd system clock CKO is output, parallel 8-bit data (
(referred to as A/D4). This data is the other input terminal B of the select gate 115. ,Bl,...,B
In addition to being input to 7, the input terminal A of another select game 119. , Al, . . . , are also input to A7. To explain the circuit for generating the signals SKl and SK2, the 21-bit (O stage to 20th stage) parallel/serial shift register 116 is reset by the reset signal RBT, and after the reset, the 21st bit (20th stage) is reset. ) only signal ``1
This shift register 116 is driven by the system clock CKO, so the I'1'' signal input at the 21st bit is output by the next system clock CKO. Then, the signal SKl is output from the shift register 116, and is sent to the A/D converter 109 and the latch circuit 113 as described above.
It is also input to the Oth stage). The signal SKl ("I"') input at the first bit is shifted to the right by one bit each time the system clock CKO is output.
Therefore, the signal SK is a signal generated every time the system clock CKO is output 22 times. A 22-bit (O stage to 21 stage) parallel/serial shift register 117 that outputs the signal SK2 has the same configuration as the shift register 116 described above.

That is, the shift register 117 receives the set signal RET.
The 22nd bit (21st row) is set by
The signal "1" is input only to the signal "1". When the next system clock CKO is output, it is output as a signal SK2 from the shift register 117, and this signal SK2 is input to the 1st bit (0th stage) of the shift register 117, and the select game 115 to the control input terminal KA of the select game 115 via the inverter 114.
It is input to the control input terminal KB of. That is, signal SK2 is generated every time the system clock CKO is output 23 times. Further, the select game 115 is input to the input terminal A when the signal SK2 is input to the control input terminal KA. -The data input to A7 is the output terminal Q. ~ Output from Q7 and also the signal SK
2 disappears and a signal "1" is input to the control input terminal KB, the input terminal B. -B, the data input to output terminal Q. ~
It is output from Q7. Input terminal B of select gate 119
.

-B5 is the tone determining element control switch TSW, which is composed of six changeover switches; The output signal of ~TSW25 is input, and the input terminals B6 and B7 are not used and are always held at the 0 level. That is, each output terminal of the musical tone determining element control switches TSW2O-TSW25 is grounded via the corresponding resistor R2O-R25, and the corresponding input terminal B of the select gate 119. - Connected to B5. These musical tone determining element control switches TSW2O-TSW
25 can selectively call out a specific sound source waveform to add various effects such as vibrato during a performance, or switch to any one of a low-pass, band-pass, and high-pass filter, or . [This is a switch used when performing PWM that changes the pulse width. The sampling timing signal PSHl9 is connected to the control input terminal KA of the selector game 119 from the inverter 1.
27. Therefore the signal PSHlO5
When is "1", the output terminal QO-Q of the select gate 119
From 7 is input terminal B. -B7 input data (ie, on/off signals of tone determining element control switches TSW2O to TSW25) is selected and output. Other signal PSHl9
When is "0", 4 input terminal A. - input data of A7 (i.e. musical tone determining element control polyyum TVRO-T
VR, 9 output signal) is output. Select gate 1
The output data of 19 is the input terminal D of the delay 123. ~D7
(DO is input through the AND gate 122), is delayed by the system clock CKOl, and is then delayed by the delay 1.
23 each output terminal Q. -Q7 outputs it to the data bus 27 as 8-bit parallel data.

Here, the configuration of the prohibition circuit that prohibits the operation of the delay 123 when the signal PR is not outputted will be explained. AN
AND gates 1240 to 1247 in D gate group 124
Channel codes CCl to CC3 are input to each first input terminal of
Channel timing signal CH obtained by decoding
O-CH7 are respectively inputted, and channel timing signals SCHO-SCH7 are inputted to each second input terminal. The outputs of each AND gate 1240 to 1247 are both 0
The signal P is sent to the NAND gate 126 via the R gate 125.
The output of this NAND gate 126 is inputted to the control input terminal DIS of the delay 123. Therefore, when the signal PR is "0", the output of the NAND gate 126 becomes "1", the operation of the delay 123 is prohibited, and the output of data from the delay 123 is prohibited. Moreover, when the signal PR is "1", AND gate group 1
Since the signal "1" is always output from one of the AND gates 24, the output of the NAND gate 126 is "O".
'', the delay 123 operates, and the tone information is created in the RAM 13 (Fig. 2) corresponding to each channel.
Alternatively, if the data set by the switches TSW2O-TSW25 match the channel information, there is a risk that the tone control device will malfunction.

In the present invention, a channel code detection circuit is provided to prevent such malfunctions. Next, this circuit will be explained. In this embodiment, the channel signal CHO-CH
7 is defined as 8-bit data shown in the following table. As can be seen from Table 1, the first digit (DO) and fifth digit (D4) of each data representing the channel signal are both "1".
/', and the second digit (D1) and the sixth digit (D5)
, the third digit (D2), the seventh digit (D6), and the fourth digit (D
3) and the eighth digit (D7) are both equal.

That is, DO-D4j-/'1'', D1-D5, D2
There is a relationship of =D6, D3-D7. Therefore, data having such a relationship may be detected from the output data A/D5 of the select gate 119, and the data may be disabled from being used as musical tone information. In the embodiment C of the present invention, when such data is detected, the first digit (DO) of the data is forcibly set to "0/'. That is, the A input terminals of the comparator 120 are gate 119
The output terminals Q, , Q2, and Q3 of are connected, and the corresponding output terminals Q5, Q6, and Q7 are connected to the B side input terminal, and each output is output from the output terminals Q1 and Q5, Q2 and Q6, and Q3 and Q7. be compared. When the contents of each output all match, a match signal A=B of 1'' level is outputted from the output terminal of the comparator 120 to the first input terminal of the NAND gate 121. 2. 3rd
The input end is the output end Q of the select game port 19. , Q4, and its output terminal is connected to the first input terminal of AND gate 122. The second input terminal of the AND gate 22 is the output terminal Q of the select gate 119.

The output terminal is connected to the input terminal D of the delay 123. connected to. If the channel code detection circuit has such a configuration, when the same data as the channel signal shown in Table 1 is output from the select gate 119,
Match signals A and B are output from the comparator 120, and the output terminal Q of the select gate 119.

, Q4 output a signal "1". As a result, NAN
All three inputs of the D gate 121 become "1", so its output becomes "0" and the AND gate 122 is closed. Therefore, the input terminal D of the delay 123. is ``0''
The signal is input, and thus data that differs from the channel signal only in the first digit is input to the delay 123 and then input to the data bus 262. On the other hand, if data different from the channel signal is output from the select gate 119, the match signal A=
Since B is not output, the output of the NAND gate 121 is ``
The signal becomes 11/level and opens the AND gate 122. Therefore, the output data of the select gate 119 is directly added to the delay 123, and the data bus 262
is output to. Next, the operation of the circuit shown in FIG. 12 will be explained with reference to the time charts shown in FIGS. 13 and 14.

As described above, in this circuit, when the signal PR is output, that is, in the PR-WT mode or the PR-WT mode, the prohibition of the operation of the delay 123 is canceled by the above-mentioned prohibition circuit, and the data is transmitted to the data verse 27. The output of is executed. Before entering any of the above modes, the tone determining element control polyurems TVRO-TVRl, and the tone determining element control switches TSW2O-TSW25 are set to desired states. First, when the reset switch 30 is operated, the 21-decimal counter 103, A/D converter 109, FF 111,
The contents of shift registers 116 and 117 are respectively signal R.
Cleared by ET. Shift register 116, 11
7 of the shift register 116 is cleared simultaneously.
Signal 71'' is manually input to the 1st bit and the 22nd bit of the shift register 117.At the same time as the reset signal RET disappears, the system clock CKO starts to be output.The first system clock CKO is input to both shift registers. 116 and 117, signals SKl and SK2 are output, respectively.

Number 20.2 below the signals SKl, SK shown in FIG.
1 of each shift register 116, 117, respectively.
Indicates that the output is from the 0th stage and the 21st stage. When the signal SKl is output, the content of the counter 103 changes from O to 1, so the signal is output only from the output terminal 1 of the decoder 102, FETlOll becomes conductive, and the output of the musical tone determining element control polyurem TVRl is transferred to the buffer amplifier 107.
The signal is sent to the A/D converter 109 via the A/D converter 109. Signals SKl and SK2 are input to the first bit of both shift registers 116 and 117, and thereafter are shifted to the right every time the system clock CKO is output, and when they reach the 21st or 22nd bit, respectively, they are input to the next bit. When the system clock CKO is output, the signals SK1 and SK2 are output. Furthermore, the set output is inverted by the set signal RET applied to FFll, and the output is applied to the input terminal SC of the VD converter 109, and the set output is inverted by the set signal RET.
09 takes in the output of the musical tone determining element control polynum TVRl and begins converting it into a digital signal, and the conversion is completed by the time the ninth system clock CKO is output. As seen in the time chart, the 22nd system clock CKO is output, and at the same time the second signal SK is output.
, until the signal EOC is output from A/D converter 1.
A/D converter 109 so that two shots are output from 09
is configured. The first signal EOC is latch circuit 1
12, the tone-determining element control polynum T which has already been converted into a digital signal from this latch circuit 112.
The output data of VR is output as data A/D1da.

Even after the second signal EOC is output, the output data A/D1 of the latch circuit 112 is still output from the musical tone determining element control polyyum TV.
It remains the output data of Rl.

When the second signal SKl is output, the content of the counter 103 becomes 2, the signal is output only from the output terminal 2 of the decoder 102, and the output of the tone determining element control polynum TVR2 is supplied to the NΦ converter 109.

In addition, the output data A/D2 of the latch circuit 113 is transferred to the tone determining element control polyume TVRl by the second signal SKl.
The output is When the 23rd system clock CKO is output, the second signal SK2 is output, and this signal S
When outputting K2, data A/
D2, that is, the output of the tone determining element control polynum TVR1, is output as data A/D3, and is input to the first bit of each shift register in the shift register group 118.

This data input to the shift register is shifted to the right every time the system clock CKO is output, and is output from the shift register group 118 as data A/D4 at the output of the 22nd system clock after the input of the data. ,
Data A/ of this musical tone determining element control polyume TVRl
D4 is the input terminal B of the select gate 115. -B7 and input terminal A of select gate 119; - input to A7. Further, when the third and fourth signals EOC are output, the output of the tone determining element control polynum TVR2 is output from the latch circuit 112 as data A/D1 and supplied to the latch circuit 113. Therefore, the data A/D1 outputted from the latch circuit 113 when the third signal SK is outputted is the output of the musical tone determining element control polynum TVR2. By the way, after the third signal SKl is output, the system clock CKOl
Input terminal B of the select gate 115 to which the output of the musical tone determining element control polyume TVR1 is output as data A/D4 from the shift register group 118 with a delay in onset. - B7, the output of the inverter 114 is output before the third signal SX2 is output after the third signal SKl.
1″, so input end B of select game port 15.-B7
The input data (output of musical tone determining element control polyume TVRl) is selected and output as data A/D3.
Then, when the third signal SK2 is output, inverter 1
14 becomes "0I", and the input terminal A of the selector gate 15.The input data of A7 to A7 (output of the tone determining element control polyyum TVR2) is outputted from the select gate 115 as data A/D3. Since the operation is repeated, the output data A/D of the select gate 115
3, as shown in FIG. 13, the outputs of the musical tone determining element control polyurems TVR1, TVR2, . Ru. Next select gate 11
9 will be described. Until the data A/D3 of the first musical tone determining element control polyyum TVR1 is input, the input terminal A of the select game port 19 is input.

-A7 has no input terminal, and is input terminal B. -Tone determining element control switch TSW2O-TSW25 only for B7
On/off information has been entered. Therefore, when the first timing signal PSHl is output after the first timing signal RET is output, the on/off information of the tone determining element control switches TSW2O to TSW25 is output from the select gate 119 as data A/D5. Ru. Further, after the second timing signal PSH19 is output, the input terminal A of the select game port 19 is input. - Since the output of the musical tone determining element control polyurem 5TVR is input as data A/D to A7, the timing signal PSH1 disappears and when the output of the inverter 127 becomes "1", the data A/D4 is also input to the data A/D. It will now be output as D5. In this way, the contents of the counter 103 progress sequentially,
When the content becomes 21 and is reset by the output of the AND gate 104 and counting starts again from 0, the input terminal A of the select gate 119, as can be seen from the previous explanation.

~A7 includes timing signals SH2O, SHO, S which are sequentially output as shown in the time chart of FIG.
Since the outputs of the musical tone determining element control polyurems TVRO-TVRl, are input in synchronization with H,..., SHl7, these are sequentially sent to the data A/D from the selector gate 119.
Output as 5. Then the timing signal PSHL,
is output, the output of the musical tone determining element control switches TSW2O-TSW25 is output from the select game port 19 as data A.
/D5 is output. This operation is repeated below. This data A/D5 is output to the data bus 262 via the delay 123. Also, as mentioned above, data A
The comparator 120 compares /D5 with the channel signal.
Executed by [6-7] Detailed explanation of D/A converter 20 and sample hold latch circuit 21 Next, the 15th
The configurations of the D/A converter 20, the sample hold circuit 21a1 and the latch circuit 21b will be explained with reference to the drawings.

When the channel codes CCl to CC3 are input, the decoder 138 decodes these codes into the corresponding channel timing signals CHO-CH7 and outputs them at the output terminal QO-
It is output from Q7 and input to the input terminal DO-D7 of delay 139. Delay 139 is system clock CKO
The input channel timing signal is delayed by one bit and the output terminal Q is driven by the input channel timing signal. - sequentially output from Q7, and these channel timing signals CH6 to CH
7 is input to the corresponding sample hold and latch circuits 130-137. Data D supplied from data bus 262. As already mentioned, -D7 is the output data from the tone determining element control polyyume TVRO-TVR,9, the tone determining element control switches TSW2O-TSW25, or the data read from the magnetic card.

Among the data D6 to D7, the musical tone determining element control polyyum T
A musical tone forming circuit 2 for the output of VRO-TVRl. ~
The data used as analog information in 27 is D/
The signal is inputted to the A converter 140, converted into analog information, and further inputted via the buffer amplifier 141 to the sample and hold circuits of the sample and latch circuits 130 to 137 of the corresponding channel. Also, data DO-
Tone determining element control switch TSW2O-TS of D7
A musical tone forming circuit 2 corresponds to the output of W25. The data used as digital information in steps 1 to 27 are input to the corresponding sample-hold and latch circuits 130 to 137. Next, sample hold and latch circuit 1
The configurations of 30 to 137 will be explained.

The sample hold and latch circuits 130 to 137 corresponding to each channel 0 to 7 have the same configuration, and only the circuit 130 corresponding to channel 0 will be explained here, and the others will be omitted. In the circuit 130, 20 sample hold circuits S/HO to S/H19 are provided corresponding to each musical tone determining element control polynum TVRO-TVR1, and the input terminals of these circuits are both connected to the output terminal of the buffer amplifier 141. has been done.

Further, one control N1 gate is provided corresponding to each of the sample hold circuits S/HO to S/Hl9, and the first input terminals of these AND gates 1420 to 14219 are the output terminals Q of the delay 139. is connected to. In addition, the second input terminals of the AND gates 420 and 14219 are supplied with sampling timing signals SHO-SH in order to correspond to the respective musical tone determining element control polyurems TVRO to TVRl.
19 is input. Therefore, for example, in the case of the sample hold circuit S/HO, when the channel timing signal CHO is being outputted from the delay 139 and the sampling timing signal SHO is being outputted, the AND gate 1420 is opened, and the sample and hold circuit is S/HO will be deregulated. During this period, the sample and hold circuit S/HO outputs the stored output voltage of the musical tone determining element control polyurethane TVRO to a signal 0.

Output as -o. In exactly the same manner, the signal 0 is sequentially output from each sample hold circuit S/H1 to S/H19. -1~0
0-19 is output. Furthermore, a latch circuit 143 is provided within the circuit 130 for latching the outputs of the tone determining element control switches TSW2O-TSW25.

This latch circuit 143 is connected to the channel timing signal CH.
When the regulation is released, the latch circuit 143 outputs the tone determining element control switches TSW2O to TSW25 as a signal signal 0.
-! ,00-25. With the above configuration, the channel timing signal CHO is sequentially output from the decoder 138.
-CH7 is output, sample and hold, latch circuit 1
30 to 137 are sequentially specified, and the specified circuits 130 to 137 are sequentially specified.
From 137, each sampling timing signal SHO
- Each signal 0 according to SH19, PSH2O.

-0, 00-25 are output, and these are the corresponding musical tone forming circuits 2 as described above. ~ Sent to 27. [6-8
] Detailed explanation of tone selector 10 and address generator 11 Next, referring to FIG.
, the detailed configuration of the address generator 11 will be explained.

The decoder 145, which receives channel codes CCl-CC3 as input signals, sequentially outputs channel timing signals CHO-CH7 from its output terminals QO-Q7, and outputs them to the common input terminals of the corresponding channel switches SU, SU2, . . . , SS2. send out. As mentioned above, each channel switch SUL, SS2 is provided with eight tone selector switches TSO-TS7, and the output terminal of each tone selector switch TSO-TS7 is connected to the corresponding one in the 0R gate group 146. 0R gate 1460~
It is connected to the input terminal of 1467. That is, for example 0
The input terminal of the R gate 1460 is connected to each channel switch SU.
It is connected to each tone select switch TSO 1 to SS2. The output terminals of each of the 0R game ports 460 to 1467 are respectively the corresponding input terminals D of the priority encoder 147. , Dl,..., D7 and priority encoder 148
are connected to corresponding input terminals D7, D8, . . . , DO. The priority encoder 147 gives priority to the one with the smaller number among the two tone selector switches pressed at the same time, and conversely, the priority encoder 148 gives priority to the one with the smaller number. These priority encoders 147, 148
The functions of the priority encoders 71 and 72 described in the panel control logic 25 of FIG. 5 are similar to those of the priority encoders 71 and 72, so a detailed explanation thereof will be omitted. The priority encoder 147 operates only when the control signal "R" is input to its control input terminal "Enable2" and outputs the corresponding 0R gate 155 from its output terminals QO, Ql, Q3.
．． 156.157 encoded signal is output. The priority encoder 148 is always ready for this purpose and has its output Q. , Ql, and Q2 are input to respective first inputs of AND gates 152.153.154 via corresponding inverters 149.150.151. A signal obtained by inverting a set output of a D-type FF1 59, which will be described later, by an inverter 158 is input to the second input terminal of each AND gate 152 to 154 as a control signal. Furthermore, the outputs of AND gates 152-154 are input to corresponding OR gates 155.156.157. The D-type FF159 receives the signal EX1 or the signal EX2 at its input terminal D through the 0R gate 60, and is driven by the signal PSH2O to delay both input signals and output them from the set output terminal Q.

The set output of FF1 59 is input to the control input "Enable" of priority encoder 147 and to AND gates 152-154 via inverter 158, as described above. Further, the FF159 is reset by receiving the set signal RET at its reset input terminal R. The outputs of the 0R gates 155, 156, 157 are connected to the inputs A5, A6, A7 of the comparator 161 and to the inputs P5, P6, P7 of the program counter 169, respectively.

Also, the input terminal A of the comparator 161. , Al, A2, A
3, A4 have signals "O", "0", "11'," respectively.
"0" and "1" are always input, so the A side input terminal of this comparator 161 is always set to 20 (decimal number). As will be described later, this means that the information for one tone is stored in the RAM 13 or ROM 14 from 0 to 20,3.
2-52, 64-84, 96-116, 128-148
, 160-180, 192-212, 224-244 (these areas are O block, 1 block, .
. At this time, the final address of each block is set for ~A7. B side input terminal BO, Bl of comparator 161
, . . . , B7 is a signal representing the contents of the program counter 169, that is, an output terminal Q. ,Ql,...,Q7
The output signal from is input. Both input signals are then compared by the comparator 161, and if the contents of both input signals match, a match signal is output from the output terminals A and B, and a signal 0A
- It is input to the D type FF163 in the B creation circuit 162.
This FF163 is driven by the system clock CKO. The reset output from terminal Q of FF163 is led together with a signal inverted by system clock CK' inverter 164 to the input end of NOR gate 165, and the output signal of this NOR gate 165 is referred to as signal 0A=B.
Further, the signal 0A=B is inputted to the first input terminal of the AND gate 168 via the 0R gate 66. Furthermore, the output signal of the AND gate 179 which receives the signal EX1 signal PSH2O and the reset signal RS are both input to the first input terminal of the AND gate 168 via the 0R gate 166. Further, the output of the NOR gate inputting the signal AL and the signal R/R is inputted to the second input terminal of the AND gate 168 as a control signal. The output of the AND gate 168 is inputted to the control input terminal PE of the program counter 169 as an enable signal. When this enable signal is input to the program counter 169, the input terminal P of this program counter 169 simultaneously. , Pl, . . . , P4 are all input with a signal "O". As already mentioned, the tone select switch code signal is input to the input terminals P5, P6, and P7 of the program counter 169.
Therefore, for example, when the tone selector switch FTS is closed, each input terminal P5, P6, P7 receives a signal "
Since 11, 1'0'', and ``0'' are input, the program counter 169 receives a signal at the control input terminal PE and inputs P.-P4 is set to ``01'', and the system clock This clock CKO is input every time CKO is input.
The configuration of the program counter 169 reset circuit is as follows: A signal obtained by inverting the system clock CKOl signal WC via an inverter 171, and a signal PSH2Ol signal A.
The output of the AND gate 172 which takes L as an input signal is inputted to the reset input terminal R of the program counter 169 via the 0R gate 174. Further, the output of the AND gate 173 having the signal AL1 signal RS as an input signal and the reset signal RET are also inputted to the above-mentioned set input terminal R via the 0R gate 174. The output of program counter 169 is input terminal D of delay 170. ~Input to D7. Since this delay 170 is driven by the system clock CKO, the output of the program counter 169 is delayed by one bit to the output terminal Q of the delay 170. -Q7 is output as an 8-bit address signal ADO-AD7 specifying the addresses of 0yRAM13 and R0M14.

Next, a signal FC (finish code) generation circuit 176
To explain, each output terminal Q of the program counter 169
.

- The output signal of Q7 is input to the AND gate 175, and the output of this AND gate 175 is sent to the signal FC generation circuit 176.
The signal is input to the input terminal D of the D-type FF177. This FF
177 is driven by the system clock CKO. F
The set output signal of Fl77 is input to AND gate 178 together with system clock CKO, and AND gate 1
78 output signals are obtained. The output of this AND gate 178 is referred to as signal FC. Next, the operation of the above circuit will be explained. Each output terminal Q of the decoder 145 receives channel codes CCl to CC3.

, Ql, . . . , Q7 sequentially output channel timing signals CHO, CHl, . . . , CH7, and the corresponding channel selection switches SUl, SU2, .
Input to SS2. Any one of the tone select switches TSO to TS7 included in these channel selection switches SUL, ..., SS2 is selected for each channel.
For example, channel selection switch SUL is TS7.
When the tone select switch TS7 is turned on in a performance mode other than the EX mode, the output signal of this tone select switch TS7 is "1".
is input to the priority encoder 148 via the 0R gate 146 during the output of the channel timing signal CHO.
At this time, the outputs of the other 0R gates 1461 to 1467 are all "0". This is because the enable signal is not input to the control input terminal "Enable" of the priority encoder 147 when the mode is not EX mode.
This is because 47 does not work. Therefore encoder 1
Since the signal "1" is input only to the input terminal DO of 48,
Each output Q of priority encoder 148. , Ql, Q3 output a signal [000], and this signal is sent to inverter 1.
49 to 151 and becomes "111", representing the tone selector switch TS7.

This signal "111" is output by the AND gate 152 since the output of the inverter 158 is "1" when the mode is not EX mode.
~Output from U154, 0R gates 155 to 157
input terminals A5, A6, A7 of the comparator 161 via
and input terminals P5, P6, P7 of the program counter 169.
and supplies a signal "1" to each input terminal.

Furthermore, if the other channel selection switches SU2 to SS2 are simultaneously outputting channel timing signals CH1 to CH7 according to the ON state of the tone select switch among them, the signals are sequentially encoded by the priority encoder 148. In the case of the channel switch SU1, when the output of the decoder 145 is switched from the previous channel timing signal CH7 to the channel timing signal CHO, both inputs A of the comparator 161. -A7,BO-B
7 match, and a match signal A-B is output from the output terminal A=B. Therefore, the signal 0A-B generation circuit 162 outputs the signal 0A=B with a delay of one system clock CKO after outputting the coincidence signal A-B, as shown in the time chart of FIG. . This signal 0A-B is 0
It is input to the AND gate 168 via the R gate 166, but at this time the signals R/R and AL are not output (
That is, R/R mode, WT-AL mode, RD・A
Since the AND gate 168 is deregulated, the signal 0A=B is input to the control input terminal PE of the program counter 169, and at the same time, the manual input terminal P of the program counter 169 is input to the control input terminal PE of the program counter 169. The signal "0I" is input to both P4 and -P4. Therefore, the program counter 169 starts counting from the content 224 "1110000". The output of program counter 169 is delay 17
Address signal ADO is delayed by 1 bit due to 0.
- It is sent to the RAM or ROM for channel 0 as AD7. The output of the program counter 169 is connected to each input terminal B of the comparator 161. -B7, is also sent to the AND gate 175, but since the A input terminal of the comparator 161 is set to the content 244 "11110100", when the content of the program counter 169 becomes 244, the match signal A=B is sent to the comparator 161. and sent to the signal 0A-B generation circuit 162. Therefore, when signals 0A-B are output as described above, program counter 169 starts counting operation for channel switch SU2. In this case, which tone select switch TSO-TS in the channel selection switch SU1
7 is not used, there is no output from the 0R gate group 146 when the channel timing signal CHO is output, but the output obtained by performing a NOR logic operation on these outputs, that is, the output of the NOR gate 280, is sent to the 0R gate by the 0R gate 281. It is subjected to an 0R logic operation with the output of the encoder 1460, and /'1/I is taken into the input terminal D7 of the priority encoder 148. As a result, the output Q of this priority encoder 148
. , Ql, and Q2 output a signal "111," respectively. Then, the input terminals A5 to A7 of the comparator 161 and the input terminal P5 of the program counter 169
A signal "0" can be input to both of P7 and P7. That is, in the program counter 169, the decoder 145
At the same time the output of the channel timing signal CH7 changes to CHO, the input terminal P. - P7 has all signals''
0// is input, and the program counter 169 has the content 0.
The counting operation starts from 20 [10100].
A match signal AB is output from the comparator 161.

Also, although it is not EX mode, WT-AL mode, RD-
In the AL mode or R/R mode, the output of the NOR gate 167 becomes "O", the AND gate 168 is closed, and the enable signal is no longer output to the program counter 169.

To explain the operation of the program counter 169 in the above three modes, first, in the R/R mode, since the reset switch 30 (see FIG. 2) is operated first, its output signal RET passes through the 0R gate 174. A set input terminal R of the program counter 169 is inputted through the
The content of the program counter 169 becomes O. Next, program counter 169 starts operating for channel 0, and its contents are brushed by "1" each time system clock CKO is input, and the contents are output from delay 170 as address signals ADO-AD7. The contents of program counter 169 are 255 "11"
111111'' and output terminal Q. - When all the outputs of Q7 become "1", the AND gate 175 outputs a "1" signal. At this time, the signal FC generation circuit 176 executes the operation of the time chart shown in FIG.
C is created. Next, program counter 169 begins counting for channel 1. In this way, the counting operation for all channels is completed. In the WT-AL mode, the program counter 169 first
It is set by the output signal of gate 172 and the contents are
and starts counting operation. Then, in the same manner as described above, when the content reaches 255, the signal FC is output, and this mode is completed. R.D. In the AL mode, the program counter 169 registers the AND gate 173 at the start of operation.
It is set by the output signal of , and its contents become O.
Start counting.

When the content becomes 255, the signal FC is output,
Complete this mode. Next, the operation in EX mode will be explained.

In this case, a total of two desired tone select switches in the same channel or in different channels are turned on. For example, when tone select switches TS1 and TS7 of channel 0 are turned on, the output of switch TS1 is preferentially output from priority encoder 147, and the output of switch TS7 is output from priority encoder 147.
8 is output preferentially. The priority encoder 147 operates while the enable signal is being input, but as shown in the time chart shown in FIG. 19, the set output (ie, the enable signal) of the FF1 59 is output while the signals EX2 and EX3 are being output. (Refer to the time chart in FIG. 7) Therefore, after the signal EX that enters the EX mode is output, the first signal PSH2O is output, and when the signal EXl is generated, the priority encoder 148 selects the tone select switch T.
A signal corresponding to S7 is output and sent to input terminals A5 to A7 of comparator 161 and input terminals P5 to P7 of program counter 169. At the same time, AND gate 179
A program enable signal is applied to the input terminal PE of the program counter 169 by the output signal EX-PSH2O of the program counter 169, and the input terminal P of the program counter 169 is input. - A "0" signal is input to P4. Therefore, program counter 169 starts counting from content 224. When the content becomes 244, the comparator 161 outputs the match signal A-B, and the signal 0A-B becomes the signal EX-PSX2.
Output at the same time as O. Next, when the output period of the signal EX2 begins, the priority encoder 147 starts operating and outputs a signal corresponding to the switch TS1 to the comparator 161 and the program counter 169. The program counter 169 starts counting from the content 0, and when the content reaches 20, the comparator 161 outputs a match signal AB. Next, the output period of the signal EX3 begins, and the program counter 169 performs the same operation as in the output period of the signal EX2.

Next, when the output period of the signal EX4 begins, the program counter 169 performs the same operation as the output period of the signal EXl, and when this operation ends, the EX mode is completed. In this way, when each signal EXl to EX4 is sequentially output, the program counter 169 executes the operation for the tone select switches TS7, TS1, TS1, TS7, respectively, and stores the data in the RAM designated by both switches TS, TS7. The internal parts of the blocks are exchanged with each other. [6-9] Detailed Description of Memory Device M Next, the configuration of the memory device M will be described with reference to FIG. 20.

This memory device M consists of a memory control logic 12 and each memory 13, 14, 15. One pair of RAMl3 and ROMl4 are provided for each channel, and RAMl3 and ROMl4 are used in this embodiment.
4 has a capacity of 256 words x 8 bits. (See FIG. 21) Furthermore, the memory blocks 200 to 207 for each channel have the same configuration. Here, the memory block configuration for channel 0 will be explained, and the memory blocks for other channels 1 to 7 will be explained. J is omitted. Further, in this embodiment, the RAM or ROM in the memory block of each channel is each composed of one chip element, so selection of a channel is the same as selection of a chip. 8z bit data D sent from data bus 262. -D7 is the data output terminal D of the RAM 187 in the memory block 200. ~D7
The data D in RAM 187 is input and written to
.

-D7 is read from data input/output terminal DO-D7 and output to data bus 262. Also, data D written in ROM188. -D7 (standard timbre information) is data output terminal D. -D7 and written to RAM187. Data D to RAM187. -Write or read D7 and data D from ROM188. -D7, the address signal ADO-AD7 is sent from the address bus 26 to the address input terminals ADO to AD7 of the RAM 187 and ROM 188, and the data D is read. -D7
The address where is stored is specified. RAM187
The output signal "1/'" of the AND gate 186 is inputted as a write command signal to the read/write control manual terminal R/W of the AND gate 186.The system clock 0K0 is inputted to the first input terminal of the AND gate 186, and The second input terminal has a signal RD
, signal R/R is inputted via the 0R gate 185.
Furthermore, the signals EX3 and EX4 are sent to the D-type FF184 via the 0R gate 183, and these signals EX3 and EX4 are
The bit-delayed signal is passed through the 0R gate 185 to the AN
A second input terminal of D gate 186 is inputted manually. That is, R.A.
Ml87 is R/R mode, RD/AL mode, RD-
In the SL mode and EX mode, the output signal of the AND gate 186 becomes 7'1//, and data read from the ROM 188 or a magnetic card (not shown) is written by being driven by the system clock CKO. Also, AND game mouth 8
When the output signal of 6 is 7', RAM187 receives a read command. Incidentally, the above-mentioned FF184 is driven by the system clock CKO.

Furthermore, specify the channel and save it to RAMl87 or ROM.
In order to select the chip of RAMl87 and ROMl88, the chip select terminals CS of RAMl87 and ROMl88 are connected to each other.
A selection signal output from AND gate 190 or AND gate 189 is input.

A channel timing signal CHO is input to the first input terminals of AND gate 90 and AND gate 189. Note that the channel timing signal CHO connects the channel codes CCl to CC3 to the system clock CKO.
Therefore, the signal is delayed by 1 bit by the delay CKO driven by the signal and then inputted to the decoder 182, and this decoder 1
82, the other channel timing signals CHl to C
Created together with H7.

Channel timing signals CH, ~CH7 as well as A in memory blocks 201~207 of the corresponding channels.
It is input to an ND gate (not shown). AND game mouth 90
5 has a NAND gate 91 which receives the signal PR and the channel timing signal SOHO as input signals.
The output of is input.

On the other hand, the second input terminal of the AND gate 198 receives the signal R/R.
is input. That is, in the RAM 187, the IC is creating tone information by the tone setting board 16 (i.e., P
R-WT mode and PR. NAN in WT mode)
The output of D gate 191! 111', the selection signal is not output from the AND gate 190, and therefore, at this time, 1! It is prohibited to rewrite the contents of RAM 187. In addition, in the ROM188, in the R/R mode, the selection signal is output from the AND gate 189 and inputted to the chip select terminal CS of the ROM188, so that the content 2 of the ROM188 is written to the RAM187.As mentioned above, , the above information is on another channel C
The memory blocks 201 to 207 of HO-CH7 are also exactly the same. Therefore, 2N in memory blocks 201 to 207 corresponding to the NAND gate 191
Channel timing signals SCH1 to SCH7 are input to AND gates (not shown), respectively. Next, EX
The RAM 198 for temporary storage used in the mode will be explained.

This RAM3198 is a memory having the same configuration as the RAM187 described above.

As described later, in EX mode, the timing signal EX
When the timing signals EX3 and EX2 are output, the data of the two programs to be exchanged are read from the RAM in the memory block and stored in different areas of the 3RAM 198, and when the timing signals EX3 and EX4 are output, the data of the two programs to be exchanged are read out from the RAM in the memory block.
The data temporarily stored in the memory block 8 is read out and stored in the RAM in the memory block by replacing the block. Therefore, the address input terminals ADO-AD4 of the 4RAM 198 are supplied with the address signals ADO-
AD4 is input. In addition, the address input line AD5 has
The timing signals EX2 and EX4 are input to the D-type FF193 via the 0R gate 92, and a delayed signal is input. The above FF193 is driven by the system clock CKO. Further, address input terminals AD6 and AD7 are always held at the signal "O". As a result, each block of data consisting of 20 words is stored in different areas of the RAM 198 at the data input/output terminals D. - written and read via D7. Also, when outputting signals EXl and EX2, RA
In order to input the write command signal 11/' to the read/write terminal R/W of the Ml98, the system clock CKO is input to the first input terminal of the AND gate 196, and the signals EXl, EXl, A signal obtained by inputting EX2 to the D-type FF195 through the 0R gate 94 and delaying it, that is, a set output signal of the FF195 is manually inputted. FF above
195 is driven by 1 by the system clock CKO to delay signals EX1 and EX2 by 1 bit. In this way, a signal synchronized with the system clock CKO is output from the AND gate 196 as a write command signal. Further R
As the chip select signal of the AM198, a signal obtained by delaying the signal EX by 1 bit by the D-type FF197 is used and is input to the chip select terminal CS. Note that the signals EX1 to EX4 are D-type FF184. l93. l95
．． The reason why the address signal ADO-AD7 is delayed by 1 bit by the delay 197 is to match the timing since the address signal ADO-AD7 is delayed by 1 bit by the delay 170 explained in FIG. 16 and is sent to each RAM. Here, referring to FIG. 21, the RAM and ROM in each memory block 200 to 207 will be explained.
, and the configuration of RAM 198 for temporary storage will be explained.

As already mentioned, each memory consists of 256 words x 8 bits. Each memory is divided into 8 blocks, addresses 0 to 31 are the 0th block, addresses 32 to 63 are the 1st block, and the rest are similarly divided into 32 addresses each, with the last address 224 to 255 being the 7th block. assigned to. Furthermore, data for one tone color is stored in the first 21 addresses of each block, and the last 11 addresses of each block are not used. Further, at addresses 20 at the beginning of each block 0 to 7, there is data D of 8 bits each, which is information obtained by AD converting the output information of the tone determining element control polyurems TVRO to TVRl9. -D7 respectively. Six musical tone determining element control switches TSW2O-TS are located at the 21st address from the beginning of each block 0 to 7.
The on/off information of W25 is stored in the lower 6 bits (DO-D5). Further, each of the blocks 0 to 7 is distinguished by using the upper three bits AD5, AD6, and AD7 of the 8-bit address signals ADO-AD7. Table 2 below shows the correspondence between each block and its code. Next, the operation of the above memory control logic will be explained.
In any operation mode, the channel codes CCl to 5CC3 output at that time are input to a delay 181, delayed by 1 bit, and then sent to a decoder 182. From the decoder 182, the channel signal CHO~
CH7 is sequentially output to each memory block 200 to 207.
is input. In the R/R mode, since the signal R/R is output, the AND gate 186 is opened by this signal R/R, and a write command is issued to the terminal R/W of the RAM in each memory block 200 to 207. Man-powered. For example, in the case of the memory block 200, the channel. While the output signal CHO is output, the output signal from each AND gate 89.190 is output from RAM187. The signal is sent to the terminal CS of the ROM188 and the chip is selected. As a result, address signal AD
The addresses (i.e., blocks) of ROM188 and RAM189 are sequentially specified by O-AD7, and ROM188 and RAM189 are designated in sequence.
The contents of 8 are transferred to the corresponding address of RAM 187. This kind of operation is performed by other memory blocks 201 to 207.
Similarly, the corresponding channel signals CH, ~CH
Executed during output of 7. Write operation, i.e. PR-
When in WT mode or WT-AL mode, AND gate 186 is closed, so each memory block 20
A signal 0I is input to the RAMOR/W terminals 0 to 207 as a read command signal.

In the WT-AL mode, the data in the SAMs in the memory blocks 200-207 corresponding to the operated channel selection switches SUL-SS2 are recorded on the magnetic card.

Furthermore, in the PR-WT mode, the tone information created by the tone setting board 16 is not written into the RAM.
Since the data is written to the magnetic card via the card I/O logic 22, which will be described later, each RAM in each memory block 200 to 207 is not selected, and the signal IO'' is sent to its terminal CS.
(For example, in the case of memory block 200, the output of AND gate 190/'0'') is input.

Furthermore, in the PR-WT mode, as in the PR/WT mode, the tone information created by the tone setting board 16 is not written into the RAM, so the input signal to the terminal °CS of each RAM is 7'. It is 7. During a read operation, that is, in RD-SL mode and RD-AL mode, signal RD is output, so that each memory block 200 to 207
A write command (signal IO/
7) has been input.

And the channel selection switch SU being operated, ~
The RAM corresponding to SS2 is selected while the corresponding channel timing signal CHO-CH7 is being output, and the tone information in the magnetic card is transferred to the RAM. In EX mode, tone select switches in the same channel or in different channels, such as switches TS1 and TS7,
are manipulated, but first the signal EX is output, and this signal EX is delayed by 1 bit by FF197 and sent to RAM1.
It is manually input to terminal CS of 98.

Also, during the output of signals EXl and EX2, the AND gate 86
Since the output of is /10//, each memory block has 200
A read command signal is input to the RAMOR/W terminal in ~207.

Moreover, since the timing signals EX1 to EX6 are signals that are sequentially output in this order, first of all, during the output of the signal EX, the signal I
O'' is input manually.In addition, the address input terminals AD6, AD
Both inputs of 7 are IOI. At this time, RAM198
The address input terminal ADO-AD4 of the lower 5 bits of
The address of the trace within the channel to which the tone select switch being operated, for example the switch TS1, belongs is input. Therefore, data for one block in the RAM corresponding to switch TS1 is written in an area for one block in RAM198. Next, when the signal EX2 is output, the address of the RAM in the channel to which the other tone select switch TS7 belongs is changed to the address signal ADO.
- Specified by AD5 to RAM 198, and as a result, data for one block in RAM corresponding to switch TS7 is written to an area of RAM 198 different from that of switch TS1. Note that while the signals EXl and EX2 are being output, the output of the AND gate 196 becomes II'', and this signal 11!' is sent to the R/R of the RAM I98 as a write command signal.
It is input to the W terminal. Then signal EX3. When EX4 is output, the output of the AND gate 196 becomes l''7, and this signal is input to the R/W terminal of the RAM 198 as a read command signal. Further, while the signals EX3 and EX4 are being output, the output of the AND gate 186 becomes 11/I, and a write command signal is input to the RAM (7) R/W terminal in each memory block 200-207.

Therefore, while the signal EX3 is being output, the address previously specified for the tone select switch TS is specified by the address signal input to the address input terminal ADO-AD4 of the RAM 198, and the address is output from that block of the RAM 198. One block's worth of data corresponding to the switch TS1 is written into the corresponding block in the RAM that originally stored the data corresponding to the tone select switch TS7.

Next, when signal EX4 is output, RAM1 is
The address signal input to the address input terminal ADO-AD of 98 specifies the address previously specified for tone select switch TS7, and
The data for one block corresponding to switch TS7 from that block is first transferred to tone select switch TS1.
is written into the corresponding block in the RAM that previously stored the data corresponding to the block. As a result, the data in the RAM specified by the two tone selector switches are exchanged with each other, and a desired performance form is obtained. Z6-10] Detailed Description of Card Reader Control Logic 24 Next, the configuration of the card reader control logic 24 will be described with reference to FIG. 22.

The card reader (magnetic card reading device) 23 used in this embodiment follows the following procedure during each operation of writing data to a magnetic card or reading data from a magnetic card, and also receives control signals WPS, SBO,
Generate RSS. That is, when a magnetic card is first inserted into the card slot, the card transport motor begins to rotate in the forward direction, and the card is transported past the position where the magnetic head is installed. No data is read or written during this forward transport. When the magnetic card has completely passed through the magnetic head installation position, this state is detected by the reverse switch, and this detection signal is sent to the card transfer motor, which starts rotating in reverse and transfers it toward the magnetic card insertion slot. begins to During this transfer, data reading or writing operations are performed on the magnetic card. During such a magnetic card transfer operation, the card loading signal (signal SBO, (See Figure 25) is output from the power reader 23. When a magnetic card is detected by the reverse switch, a reverse switch signal (signal RSS, see FIG. 25) is similarly output from the card reader 23. Furthermore, at the same time as the above signal RSS is output, write protect signals (signals WPS,
(see FIG. 25) is output from the card reader 23, but
This signal WPS is valid when it is at the 7075 level, and after the output of this signal WPS, a write operation is possible. In Fig. 22, each of the above signals WPS, SBO, RSS
A signal WRC (write read control) and a reset signal RS are created using the . That is, the signal WPS
is input to the inverter 211, but this inverter 2
The output terminal of 11 is connected to the NAND gate 21 via the resistor R3O.
2.

In addition, the first input terminal of the NAND gate 212 is also grounded to the other end of the capacitor ClO, which has one end grounded.
A second input terminal of the D gate 212 is connected to a resistor R3, one end of which is connected to a power supply supplying the signal "11," and the other end of the resistor R3, and the input terminal of the inverter 211. The output of the NAND gate 212 is connected to the input terminal of the inverter 211. The signal WT is input together with a signal obtained by inverting the signal WT by the inverter 213.The output of the NOR gate 215 is also sent to the set input terminal S of the RS type FF 2l6. Then, the reset output of FF2l6 is called signal WRC and is sent to card I/C logic 22. Signal RSS is input to resistor R33, and resistor R
A capacitor Cll, which has one end connected to the output end of 33 and the other end grounded, is charged. The output end of the resistor R33 and one end of the capacitor Cll are connected to the input end D of the D-type FF2l8. Also, the input side of resistor R33 is the signal '
One end is connected to the other end of the resistor R32, which is connected to the power supply that supplies 71''.The reset output of the above FF2l8 is N
OR gate 217, NOR gate 220, D type FF2l
They are respectively input to the D input terminals of 9. Further, the reset output of FF2l9 is inputted to the NOR gate 220, and the output of this NOR gate 220 is outputted along with the signal RD.
It is input to the ND gate 222. Furthermore, NOR gate 21
The reset output (signal WRC) of the FF2l6 is inputted to 7, and the output of the NOR gate 217 and the output of the AND gate 222 are both outputted via the 0R gate 223 as the reset signal RS.

Further, the FF2l8 and FF2l9 are driven by a clock pulse having a frequency of 500 Hz output from the oscillator 221.

Next, the operation of the above circuit will be explained with reference to the time charts of FIGS. 23 to 25.

First, in the case of a write operation, a signal WT is output. Therefore, the output of inverter 213 is IO//.

When a magnetic card is inserted into the card insertion slot of the card reader 23, the transfer motor starts to rotate in the forward direction, and the signal SBO is outputted to reach the "11" level.

When the magnetic card is completely inserted and the magnetic card is detected by the reverse switch, the signal RSS of 11" level is output (Figure 25) and the transfer motor starts to reverse. At the same time, it is normally at /11I level. Signal WPS
is inverted and becomes "O/' level. Signal WPS becomes "0I"
During the level period, as can be seen from the time chart in Fig. 23, when the signal WPS becomes "0'1", the output of the inverter 211 becomes /'B, and the capacitor ClO is gradually charged, and its charging value reaches the 11111 level. Become.

When the signal WPS disappears and reaches the /'bi level, the capacitor ClO begins to discharge, but while its potential is still at the "1" level, both power levels go to the "7" level, and therefore, during this period, the NAND gate 212 outputs a negative voltage. Therefore, the NOR gate 215 outputs a pulse in the positive direction that is synchronized with the above pulse, and this pulse puts the RS type FF 2l6 into the set state.Therefore, the FF2l6 reset signal That is, the signal WRO is inverted to the "0//" level from this point on. (See Figure 25; the vertical axes in Figure 25, that is, the time axes, are the same.) Also, when the signal RSS is output, the capacitor Cll
is charged, its charge value reaches the '7' level, and then, as seen in the time chart of Figure 24, FF2
The reset output of l8 is inverted to the "0" level. In this way, as shown in FIG.
When the reset outputs of 2l8 are both at the IO'5 level, the output of the NOR gate 217 is obtained, and this output is 0R.
It is outputted via gate 223 as a reset signal RS. This reset signal RS is sent to a card I/O logic, which will be described later, and each circuit is reset so that data can be written to the magnetic card. During the next read operation, signal RD is output and held at the 11l' level.

Of course, since the signal WT is at the 7 level, the inverter 2
13 becomes //1", therefore the output of NOR gate 215 becomes "0'5", and the set input of FF2l6 is always at "0/' level.When the magnetic card is inserted into the insertion slot, the transfer motor Before the FF2l6 starts rotating and the signal SBO is output, the FF2l6 set input signal is 1.
Since it is at the /I level, the FF2l6 is in the reset state, and the reset output signal, that is, the signal WRC is at the 21'7 level.

Signal SBO is output and FF2l6 set input is set to 2.
Even if the level reaches 01/, the set input "1" is not input, so the set output (signal WRC) does not change and becomes "1'".
It remains at level 7 (see Figure 25). When the signal RSS is output following such a state, as can be seen from the time chart in FIG.
．． 2l9 and then output to NOR gate 220. From the NOR gate 220, both FF2l8.
When the reset outputs of 2l9 and 2l9 are both "O/I", pulse signal 2"7 is output and output to AND gate 222. Therefore, AND gate 222 outputs a signal synchronized with the above pulse signal. , this signal is further outputted as a reset signal RS via an 0R gate 223.
C As a result, data is read from the magnetic card after the reset signal RS is output. [6-11] Detailed Description of Card/0 Logic 22 Next, the configuration of the card I/O logic 22 will be described with reference to FIG. 26.

First, the write control circuit will be explained. Write read control signal WRC is tie sink signal PSHl9
is input to the input terminal D of the D-type FF 23l, which is driven by a signal inverted by the inverter 232. This FF
A write control signal WC and its inverted signal WC are obtained from the output of the D-type FF 23l.
It is input to the input terminal D of No. 3. The output signal of this FF233 is applied to the set input terminal S of the RS type FF239, and the output signal of the FF233 is
39 into the set state. Further, a reset signal RS (FIG. 25) is applied to the reset input terminal R of the FF 239, and the FF 239 is brought into the reset state. And FF23
The set output of FF 239 is applied as a control signal to a control input terminal KA of a select gate 243, which will be described later, and the set output of FF 239 is applied to a control input terminal KB of the select gate 243, respectively. 8-bit data D taken out from the RAM in the memory blocks 200-207 or the tone color setting board 16 referred to in the explanation of FIG. -D7
In this embodiment, the lower and upper bits each have 4 bits, that is, D. - D3, D4 to D7 are divided and written to the magnetic card. That is, the lower 4 bits of data D. -D3 is the A-side input terminal A of the select gate 242.
−A3 is input, and the upper 4 bits of data D4~
D7 is the B-side input terminal B of the select gate 242. -B3
is input. The control input terminals KA and KB of this select gate 242 are connected to the system clock CKO.
signals via inverters 240 and 241 (i.e. system clock CKO), and system clock CK
A signal obtained by inverting O by an inverter 240 is applied. Therefore, during the period when the system clock CKO is applied to the control input terminal KA of the select gate, its output terminal D
. ~D3 to lower 4 bits of data D. -D3 is output to the A-side input terminal A of the select gate 243. -A3
is input. Further, during a period when the inverted signal of the system clock CKO is applied to the control terminal KB of the select gate 242, the output terminal D is applied. - The upper 4 bits of data D4 to D7 are output from D3 and sent to the select gate 2.
A side input terminal A of 43. - input to A3. In this way, the select gate 242 receives 8-bit data D. -D7 is data D of 4 bits each. -D3, D4~
This is an 8/4 bit conversion element that outputs data with a time shift to D7. B-side input terminal B of the select gate 243. -B
2 has its A side input terminal A. - Data D input into A3. Channel code C to which ~D3~, D4~D7 belong
Cl to CC3 are input as 3-bit data. Note that the remaining B-side input terminal B3 is always held at the 11'' level. As a result, during the period when the FF 239 nozzle set output /11I is applied to the control input terminal KB of the select gate 243, the select gate 243 is kept at the 11'' level. Output end D.-
Channel codes CCl to CC3 are outputted from D3 as data DCO-DO3 for writing to the magnetic card, and FF239 is outputted to the control input terminal KA of the select gate 243.
During the period when the set output "1" is applied, the output terminal D
. -Data D of 4 bits each from D3. -D3, D4~
D7 is output as write data DOO-DO3 to the magnetic card. By the way, the above data D is on the magnetic card. ~D7, a clock pulse is recorded simultaneously with channel codes CCl~CC3. During a read operation, data D is read from the magnetic card using this clock pulse as a reference. -D7, channel code CC, ~CC
3 is read. In this embodiment, the clock pulse written to the magnetic card is called write clock CO. In addition, as will be described later, the clock pulse C (inverted signal of the write clock CO) read from the magnetic card is processed to generate the clock pulse used in the read operation.
It is called Kl2. Here, a circuit for generating the write clock CO will be explained. Signal WRC is input terminal D of D type FF23l
is input. This FF23l is a timing signal PSH
, 9 are inverted by an inverter 232. The set output signal of the FF 23l is called a signal WC and is sent to the address generator 11 (FIG. 16). Further, the reset output signal WC of the FF 23l is supplied to the NAND gate 236 in the write clock CO generation circuit 235.
It is input together with the system clock CKO. NAN
The output terminal of the D gate 236 is connected to a D type FF via a resistor R4O.
238, and this input terminal D is grounded via a capacitor Cl5.

In addition, the signal WT is input to the input terminal S of the FF238.
It is manually powered through 37.

This FF 238 is driven by a clock pulse CKl having a frequency of 100 KHz, and outputs a write clock CC from its set output terminal Q.

System clock CKO is a clock pulse with a frequency of 390 Hz, and during a write operation, data is written to the magnetic card at the rising (falling) edge of system clock CKO. Therefore, if the clock pulse CO recorded on the magnetic card is a clock that is output at the same timing as the system clock CKO, the timing of the system clock CKO and the write clock may deviate for some reason during this write operation. If the data is recorded on a magnetic card in such a state, an error may occur in which the data cannot be read accurately during a read operation. The write clock CO in this embodiment has its rising (falling) position at the system clock C.
This clock is created to be located between the rising (falling) and falling (rising) positions of OO. Therefore, the occurrence of the above-mentioned errors is reliably prevented, and a stable read operation can be performed at all times. Write clock C here.
The operation of the O generation circuit 235 will be explained with reference to the time chart of FIG. 27.

When the signal PSH19 is output and the reset output (signal WC) of the FF 23l reaches the 21'' level, the NAND gate 236 outputs a signal CKO which is an inversion of the system clock CKO.

This signal CKO charges and discharges the capacitor Cl5 via the resistor RO. Also, the input terminal S of the FF238 has a signal WT.
(At this time, an inverted signal WT'' of 2''7 level) is applied, and the terminal voltage of the capacitor Cl5 is applied to the input terminal D. Therefore, as shown in Figure 27, N
System clock CK added to AND gate 236
Since O is transmitted to the input terminal D of FF238 with a delay of time t when it is charged and discharged to the capacitors C and 5, FF23
The set output of 8, ie, the write clock CO, is also at time t.
output with a delay. As a result, the write clock CO
The rising (falling) position of CKO is located midway between the rising (falling) and the falling (rising) of the system clock CKO. Next, the configuration of the read control circuit will be explained. Data D recorded on a magnetic card in a 4-bit configuration as described above. -D3, D4 to D7 and channel codes CCl to CC3 are read by the card reader as signals D[o to DI3 of opposite polarity in this embodiment.
Therefore, these signals DIO to DI3 are connected to the delay 246
input end D. - input to D3 and delayed by 1 bit,
Its inverted output terminal Q. -The polarity is inverted and output from Q3. The output of the delay 246 is called data DTl, and this data DTl is the input terminal D of the delay 245. ~D3 and the input terminals D4 to D7 of the delay 244, and are output after being delayed by one bit at the delay 245. Output data DT from output terminal QO-Q3 of delay 245
2 is the input terminal D of the delay 244. - Manually powered by D3.
Here, the signal is again delayed by one bit at the delay 244 and output. The output data DT3 from the output end QO-Q7 of the delay 244 is 8-bit data D. -D7 is output to the data bus 27. As mentioned above, the 4-bit data DIO-DI3 read from the magnetic card
is 8-bit data D via delay 245 and delay 244. -D7 is output from the delay 244. Therefore, both days 245 and 244 are 4
/8 bit conversion element is formed. Next, the above Delay 2
Clock pulses SC and PCKl that drive 44 to 246
The circuit for generating the reset signal R and the circuit for generating the read clock CKl2 will be explained below. The reset signal RS and the control signal RD output during the read operation are
is input to the ND gate 250, and this AND gate 250
The output of is applied to the set input terminal S of the RS type FF 252l. This FF252 converts the signal SBO to the inverter 251.
The inverted signal is input to the reset input terminal R and set state, and this reset output signal is applied to the reset input terminal R2 of each of the above-mentioned delays 244 to 246, so that each delay 244 to 246 is simultaneously activated. will be reset.
The set output signal of FF252 is the clock pulse CI (CO: clock pulse C) read from the magnetic card.
I has an inverse characteristic to the write clock CO. ) together with
It is input to a NAND gate 254 in a 2×2 multiplier 253. The output of the NAND gate 254 is input to the first input terminal of the NAND gate 258 as well as to the inverter 2.
55. The output of inverter 255 is NAND
In addition to being input to the first power terminal of gate 260, it is also input to capacitor Cl6 and inverter 256, one end of which is grounded, via resistor R4l. The output of the inverter 256 is input to the second input terminal of the PAND gate 260, and is also input to the second input terminal of the NAND gate 260 via the inverter 257.
It is input to the second input terminal of 8. Furthermore, both NAND gates 2
The output of 58.260 is input to NAND gate 259.

The output of this NAND gate 259 is the clock pulse SC.
As both delay 245.246 and D type FF249
is applied to each clock input terminal CK.

The input terminal D and the set output terminal Q of the FF249 are connected together, and the set output signal is the signal PCKl2.
In addition to being applied to the clock input CK of the delay 244, the signal is also input to the first input of the AND gate 265. Furthermore, the clock pulse SC is an SR type FF2.
6l set input S and AND gate 266.26
7.268 are input to each first input terminal. Also, the second input terminals of AND gates 266, 267, 268 and 265 have FF26l, FF262, FF263,
64 set outputs are input.

Furthermore, each output signal of AND gates 266, 267 and 268 is outputted to FF262, FF263, FF264, respectively.
is input to each set input terminal S of.

The output signal of AND gate 265 is the read clock. The reset output signal of the FF 252 is input to the reset input terminal R of each of the FFs 249, 261-264, and is set. The operation of the clock pulse SC and readout clock CKl2 generating circuit will now be described with reference to the time chart of FIG.

Now the signal RD is 2"7, and at this time the threshold set signal R
When S is output, a signal 212 synchronized with the set signal RS is output from the NAND gate 250, the FF 252 enters the set state, and its set output becomes 212. When the first tarlock pulse CI is read out from the magnetic card, the NAND gate 254 outputs an inverted signal of the clock pulse CI.

The output of inverter 255 is a signal synchronized with clock pulse CI, and this signal is charged in capacitor Cl6.

Since this RC circuit is a delay element, the inverter 256
The output of the inverter 255 falls slightly later than the rise of the output signal of the inverter 255, and is outputted to the NAND 25 via the inverter 257.
7 and directly to NAND gate 260. Therefore, the output of the NAND gate 258 is at the 2O level from when the output of the NAND gate 254 rises until the output of the inverter 257 falls, and is at the ``1'' level during the other periods.

Similarly, the output of NAND gate 260 is
The output of inverter 256 rises and then remains at 20'' level until the output of inverter 256 falls, and remains at 71'' for the rest of the period.
It becomes a level signal. Therefore, the NAND gate 259
The signal SC which is the output of both NAND gates 258.26
When the output of 0 is at the 20'' level, it becomes a pulse signal of the 1 level. When the second and subsequent clock pulses CI are sequentially read out, two clock pulses SC are outputted at a time.

That is, the clock pulse SC is a pulse that is output at the rising and falling edges of the clock pulse CI. F
Since F249 and FF26l-264 are both reset at the start of the read operation, the first clock pulse S
When C is output, the set output of FF249 (signal PC
K, 2) becomes "12," and at the same time, the input terminal D of FF249
becomes 202. Therefore, when the second clock pulse SC is output, the set output of FF249 (signal PC
K, 2) becomes "0". Therefore, the signal PCKl2 becomes a signal with a waveform as shown in FIG. 28, and the signal SC
is inverted each time it is output. Other power, FF26l~26
In 4, FF2 was created by the first Clock Panores SC.
6l is set and its set output becomes "1" and is held thereafter. FF262 is the second clock pulse S
FF263 and PF264 are set by the third and fourth clock pulses SC, respectively. Therefore, the read clock CKl2 is 4
After the first clock pulse SC is output and the FF 264 is set, it is output in synchronization with the signal PCK,2.
In this way, the readout clock CK,2 is a four-stage FF26l.
By the operation of ~264, the output data D of the delay 244
The timing is set with T3 (DO-D7).

Next, channel codes CCl to C included in data DIO-DI3 read from the magnetic card.
From C3, the corresponding channel codes RC, ~
The configuration of a detection circuit that detects RC3 will be explained.

As already mentioned in the description of FIG. 12, each channel signal CHO-CH7 in this embodiment has a code shown in Table 1. Therefore, the channel signal CHO-CH
7 (that is, channel codes RC, to RC3) can be detected by comparing identical digits, for example, the first and fifth digits, the second and sixth digits, etc. Data D are also compared with each other. - Data D of the lower 4 bits of D7. −
D3 and the upper 4 bits of data D4 to D7 are delay 24
5 output data DT2 and delay 246 output data D
Obtained as Tl. That is, the output of the output terminal QO of the delay 246 (fifth digit of data) and the output terminal Q of the delay 245. (first digit of data) is input to an AND gate 247, and the output of this AND gate 247 is used as an enable signal for the manual terminal Enab of the comparison circuit 270.
It is input to Ie.

Also, the human power end A of the comparison circuit 270. -A3 and input end B
. -B3 are input with DT, and data DT2, respectively. At the same time, the manual terminals DTl to DT3 of the latch circuit 248
The outputs (5th to 7th digits of data) of the output terminals Q1 to Q3 of the delay 246 are input manually.

When the match signal from the comparison circuit 270 is input to the clock input terminal CK, the latch circuit 248 latches the input data and outputs 3-bit channel codes RCl to RC3 from its output terminals Q1 to Q3.

Latch circuit 248 is also set by signal SBO. The write and read operations of the card I/O logic configured as described above will now be explained with reference to the time charts of FIGS. 29 and 30.

First, the write mode will be explained. At this time, the signal WT
is at the 21" level. Also, the system clock CKO with a frequency of 390 Hz is manually input to the card/0 logic 22, and further a set signal RS is output to reset the FF 239. At the same time, the signal WRC is inverted and the 20/0 logic is input. ' level and a write operation is possible.Then, when the sampling signal PSH19 is output, the signal inverted by the inverter 232 is applied to the clock input terminal of the FF231.
At the rising edge of this signal PSHL9, the output terminal Q of FF23l
A signal WC"1" is obtained from. This signal WC is D type F
When input to the D terminal of F233 and driven by clock CKO, the signal PS/'1 is outputted from FF233 with a delay of one clock.
'' is obtained. Due to the stiffness, the set output of FF 239 is inverted to the ``1// level, and thereafter it is held at the ``11 level.'' While the set output of FF 239 is at the ``O'' level, that is, the set output of FF 239 is inverted to the ``1'' level. Since the FF 239 set output is applied to the control input terminal KB of the select gate 243 during the ``11 level, at this time, the input data at the B side input terminal of the select gate 243, that is, the channel codes CCl to CC3 are applied to the output terminal D. Data D.-D3 is output as data D.-D3 and written to the beginning of the magnetic card.When the signal PSH19 is output here and applied to the clock input terminal CK of FF23l via the inverter 232, the set output of FF23l is output. The signal (signal WC) is inverted at the rising edge of the signal PSHl9 and becomes the 202 level. At the same time, the signal WC becomes the 7 level and is input to the NAND gate 236. From this point on, the NAND gate 236 outputs the signals to both inverters 240 and 241. The inverted signal of the system clock CKO applied via
The capacitor Cl5 is charged and discharged. Then, as described with reference to FIG.
It starts being output when H2O is output. From this point on, the select gate 242 inputs the manual data D according to the input state of the system clock CKO. - Data D of the lower 4 bits of D7. -D3 (L) or the upper 4 bits of data D4 to D7 (H) are alternately outputted and sent to the select gate 243. The select gate 243 is the A side input terminal A. -The above data sequentially input to A3 is output as output data DOO-DO3. As shown in Figure 29, the channel code CCl~ is placed at the beginning of the magnetic card.
After CC3 is written, the lower 4 bits of data 0L. of the channel O block are written. 0 block's upper 4 bits of data 0H. Data IN of lower 4 bits of I block
, . . . each piece of data is sequentially written. At the same time, the write clock CO also outputs each data 0L, 0H, IL...
written with. Next, the read operation will be explained. In this case, the signal RD is at the 7"2 level. Also, when the signal SBO is at the "0I" level before the read operation, this signal is applied to the reset input terminal R of the FF 252 via the inverter 251, and the FF 252 is Since the reset output is ``1'', each delay 244~
FF 246, FF 249, and FF 261 to 264 have all been reset.

When the read operation starts and the reset signal RS is output,
A signal synchronized with the reset signal RS is output from the AND gate 250, and the FF 252 is brought into the set state. Then, the set output 2111 of the FF 252 is inputted to the 4NAND gate 254 together with the clock pulse CI read from the magnetic card, and the signal SC is created as described with reference to FIG. When the signal SC starts to be output, the delay 245, 246, F
Since F249 starts to be driven, the channel code of a certain channel read from the magnetic card CCl~C
C3, data 0L, 0H, L,... are sequentially delayed 2
46 and sent out to delay 245 and delay 244.

Therefore, as shown in FIG.
6,245.244 output data DTl, DT2, DT
3, there is a shift of the signal SCl. When the read clock CKl2 begins to be output, the data from the O block is outputted as data DT3 (DO-D7) and sent to the data bus 27.

In addition, the detection of channel codes CCl to CC3 is performed by comparing both data DTl and DT2 in a comparison circuit 270.
When a match signal is output, its channel code CCl
~CC3 are latched by the latch circuit 248 and output as channel codes RCl~RC3. This concludes the explanation of the configuration and operation of each part of the above embodiment of the present invention. [6-12] Detailed Explanation of Operation Modes Next, a detailed explanation of the eight operation modes of the invention described at the beginning will be explained with reference to the related drawings.

(1) R/R mode (ROM to ORAM mode) This mode is a mode in which the standard tone color information previously stored in the ROM 14 is immediately transferred to the RAM 13 at the start of a performance so that the performance can be performed.

When the power switch (not shown) is turned on and the reset switch 30 is then pressed, a reset signal RET is output (see FIG. 31).

In FIG. 9, since the signal WT and signal RD are both at the "0I level," the NAND gates 87 and 89 are opened.
A clock pulse with a frequency of 100 KHz from the oscillator 85 is output as the system clock CKO. Also the fourth
In the figure, when the reset signal RET disappears, the signal R/R
is output from FF4O, and this signal R/R is sent to NOR gate 167 (FIG. 16).

Therefore, the output of the NOR gate 167 becomes "0" and A
ND gate 168 is closed and program counter 169 is not program enabled.

The program counter 169 is reset when the set signal RET is output, and thereafter the system clock C is reset.
It is driven to 1 by KO and starts a counting operation, and its output is applied to delay 170 and delayed by 1 bit, and then output to address bus 26 as address signal ADO-AD7.

Furthermore, the output of the program counter 169 is also sent to a signal FC generation circuit 176, and a signal FC is output every time the contents of the program counter 169 reach the maximum count value 255. On the other hand, the octal counter 69 (FIG. 5) is reset when the above set signal RET is output, and its content becomes O. This content 0 is output as channel codes CCl to CC3 via the gate circuit G2, but at this time, these channel codes CCl to CC3 are set to channel O (CHO
). The contents of the octal counter 69 are incremented by 1 each time the signal FC is output, and the channel codes CCl to CC3 change sequentially to channel 1, channel 2, and so on. Channel code CC, ~
CC3 is delayed by 1 bit by a delay 181 (FIG. 20) and then input to a decoder 182, which outputs rechannel timing signals CHO and CHl.
, . . . decoded to CH7.

Each of the channel codes CCl to CC3 and the address signals ADO to AD7 corresponding to these channel codes are each delayed by one bit by the delay 170 or delay 181, so the timing of the output period of both is shown in FIG. are consistent.

In this way, since an address is specified for each channel, each memory block 200 to 2 shown in FIG.
At 07, the RAM and ROM are chip-selected at the channel timing, and a write command is output to the control terminal 10/W of the RAM. For this reason, R.O.
The contents of M are sequentially copied to corresponding locations in the RAM.

When the write operation for channel 7 is completed, the eighth signal FC is output from the signal FC generation circuit 176. Also, since the signal CH7 is output from the AND gate 76 (Fig. 5) and opens the AND gate 42 (Fig. 4), when the eighth signal FC is output, this signal FC is delayed by one bit by the delay 43. After that, the signal is input to the FF4O reset input terminal R, and the FF4O is reset. Therefore, the signal R/R is inverted to become /'0I, and the chip select signal for the RAM and ROM in each memory block 200-207 becomes O, completing all operations in the R/R mode. As described above, when the power switch and reset switch are turned on at the start of a performance, the contents of the ROM, which stores standard timbre information for each channel, are immediately and automatically written to the RAM.

Therefore, after this, select the desired channel selection switches SUL, SU2, ..., SS2 and the tone selection switch TSO-T belonging to these channel selection switches.
Performances using arbitrary standard tone color information can be performed while operating S7. Further, even when a performance is being performed using arbitrary tone color information in the PR-WT mode, which will be described later, by operating this R/R mode, it is possible to immediately return to the performance using standard tone color information. ). ) Performance Mode Next, the operating method of the performance mode and its circuit operation will be explained with reference to FIG. 32 and the like.

This performance mode can be performed by operating a channel switch and a tone select switch belonging to the channel switch to select a specified channel (in this embodiment, memory block 200 to The tone information stored in the specified program in the RAM (corresponding to the RAM in the 207) is always output to the corresponding channel of the sample-hold latch circuit 21 (Figs. 2 and 15) so that it can be played. This is what I did.

Before starting the performance, operate the channel switch of the desired channel and the desired tone select switch belonging to it. For example, channel switch U1 of channel O (ChO) and its tone select switch TSO
Similarly, switches CHl (U2) and TSl, CH2 (L
1), TS2, ..., CH7 (S2) and TS7 are operated. Since none of the signals WT, RD, and EX are output, only the gate circuit G2 in FIG. 5 is open.

Further, since the signal R/R is also "0'5", the AND gate 67 in the pulse generating circuit 64 is open, and this AND gate 67 is open.
A sampling timing signal PSH2 is output from the gate 67.
A signal synchronized with O is output.

This signal PSH2O is applied to the clock input terminal CK of the octal counter 69 via the 0R gate 68, and
Drive 9.

If the counter 69 is initially set, the counter 69
The contents of are incremented by 1 from O. Therefore, channel codes CCl-CC3 sequentially change to contents corresponding to channel timing signals CHO-CH7 in synchronization with signal PSH2O. Also, in FIG. 9, the NOR gate 92
Since the output is "11", a pulse signal of the same wave number of 100 KHz is output as the system clock CKO.

Driven to 1 by this system clock CKO, a 20-bit shift register 99 operates, and the sampling timing signals PSH2O and SHO-SH19 are sequentially output. Next, in FIG. 16, the channel code CC,
~CC3 is input to the decoder 145, decoded into channel timing signals CHO-CH7, and sent to each channel selection switch SU1-SS2.

For example, in the channel selection switch SUl,
Because the tone select switch TSO is installed,
When the signal CHO is output, the output of the switch TSO is input to the priority encoder 148 via the 0R gate group 146. The output of the priority encoder 148 is transferred to the inverters 149 to 1.
The code signal [000'' of the switch TSO obtained by inverting the switch TSO by
and input terminals A5 to A7 of the comparator 161.

Also, at this time, that is, the channel timing signal is C
At the time of switching from H7 to CHO, the comparison was 16
The contents of both inputs of 1 match, and a match signal A=B is output. Therefore, 0A=B is output from the circuit 162 and 0
R gate 166 is applied via AND gate 168 to the control input PE of program counter 169 to program counter 169 and its input P. -The "0I signal is input to P4. Therefore, all the inputs of the program counter 169 become "0'7, the contents become O, and address 0 of block O of RAM 187 in the memory block 200 is specified. be done. The contents of the program counter 169 are incremented by 1 each time the system clock CKO is input, and the contents are output as the address signal ADO-AD7 via the delay 170.
61 is also input. On the other hand, in FIG. 20, channel codes CCl to CC3 are input to a decoder 182 via a delay 181, and a channel timing signal C
Since HO is input to memory block 200, R
AMl87 is chip selected.

And address input terminal A of this RAM187. The address signal ADO-AD7 is input to -A7, and the contents of address O (data D.

-D7) and output to the data bus 27. Note that a signal 0 is manually inputted to the R/W input terminal of the RAM 187 as a read command. In addition, in the sample hold latch circuit shown in Fig. 15, channel code C
Cl to CC3 are decoded by a decoder 138, and a channel timing signal CHO is input to the circuit 130 via a delay 139.

Also, the switch T read out from RAMl87 in FIG.
Data D for SO.

-D7 is input to the D/A converter 140 and latch circuit 143 in FIG. 15, and the sampling timing signal SH
Data D stored in addresses 0 to 20 of RAM 187 in synchronization with O to SHl,,PSH2O. ~D7 are sequentially stored in each sample hold circuit S/HO~S/H19 and latch circuit 143. Also, these output data are 0. -025 is the vendor formation circuit 2 of channel 0 (CHO) in FIG. 1a. supplied to In this way, when the operation for the channel selection switch SU is completed and the contents of the program counter 169 reach 20, the contents of both inputs of the comparator 161 match, and a match signal A-B is output, and then 0A-B is output. It is output and program counter 169 is enabled for programming. At this time, the channel is switched to channel 1, and a similar operation is started for the tone select switch TS of the channel selection switch SU2. In this case, the address 32 is given to the program counter 169 as the first address of the RAM in the memory block 201, and the last address 52 of the RAM is given to the A side input terminal of the comparator 161.

In this way, once the contents of the RAM corresponding to the channel selection switches SU, ~SS2 are stored in the sample and hold latch circuits 130 to 137, the keyboard corresponding to each channel selection switch is operated. For example: - You can perform with different tones. (3)
PR-WT mode This PR-WT mode uses the tone setting board 16.
Tone determining element control polyume TVRO-TVR19
or musical tone determining element control switch TSW2O-TSW
25 while operating the keyboard keys to play with any tone.
The signal is converted into a digital amount by the converter 17 and placed on the data bus 27, and further converted into an analog amount by the D/A converter 20 and stored in the sample and hold circuit 21a.

Also, musical tone determining element control switch TSW2O-TSW2,
The output is sent to the latch circuit 21b via the data bus 27 and latched.

First, the production use switch 32 shown in FIGS. 3 and 4 is operated.

In this example, it is assumed that channel 1 (U2) and tone select switch TS1 have been operated, and the upper keyboard 11 of FIG. 1a is operated to perform a performance in this mode. At this time, the all select switch 31 shown in FIGS. 3 and 4 is set to the SELCT side.

As a result, in FIG. 4, the signal PR and the signal SL are output, and both become 21//. Also, as shown in FIG. 8B, the octal counter 69 (FIG. 5) outputs the signal PSH2.
O, the counter 69 is driven to perform a counting operation, and the contents of the counter 69 are sent to the channel codes CC, ~C through the gate circuit G2.
It is output as C3. Furthermore, in FIG. 9, the signal WT
, signal RD should both be output, so the frequency is 10.
A 0KHz clock pulse is output as the system clock CKO. Therefore, the sampling timing signals PSH2O, SHO to SH, , are sequentially output to the sample-hold/latch circuit 2 of FIG. 2 or FIG.
1 (130-137). Also, since the channel selection switch SU2 is operated, the output of this channel selection switch SU2 is sent to the priority encoder 71 (fifth
) is input to the NOR gate 70. As a result, a code signal for channel selection switch SU2 is output from priority encoder 71 and sent to decoder 79.

At this time, since the output "0//" of the NOR gate 70 is applied to the inhibit input terminal of the decoder 79 to cancel the inhibition, the channel timing signal SCHl for the channel selection switch SU2 is output from the decoder 79, and /becomes.

Since each signal is output as described above, the channel codes CCl to CC3 are decoded by the decoder 138 (FIG. 15), further delayed by 1 bit by the delay 139, and the channel timing signals CHO to CH7 are output to the sample and hold latches. It is input to circuits 130-137. Further, in FIG. 12, as already described in detail, the counting operation of the 21-decimal counter 103 causes the decoder 10 to
2, each gate 1010 to 1 in the gate group 101 is sequentially
01, 9 are outputted, and the output voltages of musical tone determining element control polyurems TVRO to TVR, 9 are sequentially passed through the buffer amplifier 107 to the A/D.
The data are sent to the converter 109 and converted into corresponding digital amounts of data, and these data are sent to the latch circuit 1.
12.113, A side input terminal A of the select gate 19 via the select gate 115 and the shift register group 118.

-It is being sent to A7. Further, on/off information of the tone determining element control switches TSW2O to TSW25 is directly supplied to the B side input terminal B of the select gate 119. -It is being sent to B3. The timing signal PS is output from the select game port 19.
Depending on the output state of Hl9, the output of the musical tone determining element control polyyume TVRO-TVRl9 or the output of the musical tone determining element foot switches TSW2O-TSW25 is the data A/D.
It is output as 5l.

This data A/D5 is sent to the first
As shown in the table, it is compared to see if it matches the predefined channel code, and if the data A/D5 is different from the channel code, it remains 1 and the delay 1
Data D is delayed by 1 bit by 23 and then transferred to data bus 27.

-D7, and further sent to the sample-hold/latch circuit 131 via the D/A converter 140 (see FIG. 15) and the buffer amplifier 141 or directly when the channel signal CHl is output.

Furthermore, if the data A/D5 shown in FIG. 12 matches the 10,000-channel code, 1
After the digit is set to 201/, it is output to the delay 1232, thereby preventing a match with the channel code. Note that at the control input terminal DIS of the delay 123, the signal SCHl is always 2-bit, so the output of the AND gate 241 becomes "1" only when the channel signal CHl is output.
'7.

Also, since the signal PR is "1", the NAND gate 12
The output of 6 is synchronized with the output of AND gate 1241.
This becomes an I signal and is input to the control input terminal DIS.
Therefore, the delay 123 is canceled during the output period of the channel signal CHl, and the data A/D5 is changed to the data D as described above.

-D7 to the data bus 27. Also data D
. -D7 is delayed by 1 bit by delay 123, and channel timing signal CHO-CH7 is delayed by 1 bit by delay 139, so they are input to sample-hold/latch circuits 130-137 in FIG. 15 at the same timing.

As described above, in the above example, the output data of the tone determining element control polyurems TVRO-TVRl9 and the tone determining element control switches TSW2O-TSW25 for the tone select switch TSL of the channel selection switch SU2 are sent to the sample-hold latch circuit 131. Data bus 262 for each output of timing signal CHl
It is sent via. Therefore, by operating the upper keyboard 11, a performance can be performed using the set tone information. Of course, if any of the tone determining element control polyurems or tone determining element control switches are operated simultaneously during performance, the performance can be performed with a different tone each time. Of course, by increasing the number of channel selection switches and tone selection switches used, it is possible to freely perform performances using more complex tones. 4) PR-WT mode This mode is the tone information D set in the PR-WT mode described above.

-D7 is sent to the card I/C logic 22 via the data bus 262, and the card I/C logic 22 converts the above 8-bit information into 4-bit information, and also creates a write clock. The write clock is recorded on the magnetic card along with the above 4-bit information. PR-WT
Following the mode switch operation, a magnetic card is set in the card reader 23.

Next, write switch 28 is operated. At this time, the FF 47 in FIG. 4 is set by the output signal of the write switch 28, and the set output causes the signal WT to become "11." This signal WT releases the regulation of the NAND gate 88 in FIG. 87 is closed.
As a result, the frequency 3 used in this PR-WT mode
The system clock CKO switches to the 90z clock. Since the FF 98 and shift register 99 are driven by 1 by this system clock CKO, the sampling timing signals SHO-SH2O, P output from these
The frequency of SHO-PSH2O also changes.

Furthermore, since the switch operation in the PR-WT mode described above remains unchanged, the signals PR and SL are output.
A channel selection switch SUl and a tone selection switch TSL are also installed. Furthermore, as in the PR/WT mode, the output of the counter 69 in FIG. 5 is outputted as channel codes CC, -CC3 via the gate circuit G2.

Also, the musical tone determining element control polyyum TVRO~TVRl9
, the outputs of the tone determining element control switches TSW2O-TSW25 are outputted from the select gate 119 (FIG. 12) according to the output state of the signal PSH19, and are delayed by 1 bit by the delay 123 to become data D.

-D7 is output to the data bus 27. In addition, the output of the tone select switch TSL of channel 1 is manually inputted to the priority encoder 148 shown in FIG.
As described in the mode, the program counter 169 and comparator 161 are operating. Program counter 1
The output of 69 is delayed by 1 bit by delay 170 and sent to address bus 26 as address data ADO-AD7.
1 is output. At this time, the card reader control logic 24 (Fig. 22) outputs the signal WRC and the reset signal RS from the control signals RSS, WPS, and SBO output from the card reader 23, as shown in the time chart of Fig. 25. Created.

In addition, in the card I/0 logic 22 of FIG. 26, FF2
39 is in the set state, the select gate 24
Data DOO-DO3 representing channel 1 is output from 3 and written to the magnetic card. Next, when the FF 239 is set, 8-bit data D is sent from the data bus 27. -D3 is the system clock CKOOllI
(4 bits of data D are output from the select gate 242 as -D3, D4 to D7 according to each state of 5"0I, and these data are further output from the select gate 243 as data DOO-DO3 and written to the magnetic card. At the same time, a write clock CO is created in the circuit 235 and written to the magnetic card simultaneously with each of the above data DOO-DO3.

When the tone data for one block, that is, 21 words, is written to the tone select switch TSL in this way, the match signal A=B is output from the comparator 161 in FIG. 16, and therefore the signal 0A-3 is Output.

As a result, the output of the AND gate 44 in FIG.
47 is added to the human power end R, and FF47 is set. Therefore, the signal WT disappears and the PR-WT mode for the tone select switch TS1 is completed.

As a result, data for one tone color is recorded on the magnetic card. By repeating the above PR-WT mode and PR-WT mode many times in succession, a large number of tone information can be recorded on a large number of magnetic cards. You can immediately start playing using the tone information recorded in the . In addition, the eight magnetic cards created as described above are used as RD-SL, which will be described later.
By operating the mode, you can sequentially write to each program of a certain channel, and then record data for 8 tones on one magnetic card using the WT-AL mode, which will be described later, for even more convenient performance. The number of sheets required is also small. 5) RD-SL mode This mode is similar to the PR-WT mode and PR-W described above.
This mode allows information for one tone color to be written into any program of any channel from one magnetic card on which information for one tone color has been recorded in the T mode so that it can be used for performance.

Assume that a large number of magnetic cards each storing information for one tone have already been created.

First, the all select switch 31 shown in FIGS. 3 and 4 is set to the select (SL) side, and then a magnetic card storing information for one tone color is set in the card reader 23. Next, the readout switch 27 is operated, and the channel selection switch of the desired channel and its tone selection switch are operated one by one. In this example, channel selection switch SU2 and tone selection switch TS
Let us operate O. By operating these switches, FF49 in FIG. 4 is set and the signal RD becomes "
1/', and the signal SL also becomes 2'7.
Since the channel selection switch SU2 shown in the figure is turned on, its output is sent to the priority encoder 71 and the NOR gate 70.
is man-powered.

Therefore, the decoder 79 is disabled and becomes operational, and the code signal of the channel selection switch 5SU2 is output from the priority encoder 71, and the decoder 79 is outputted from the priority encoder 71.
9 and is output to the gate circuit G3. Gate circuit G3 is 0
It is opened by the signal RD-SL output from the R gate 80. Therefore, the gate circuit G3 outputs the channel code CC, to CC3 representing the channel 1, and the decoder 79 outputs the signal SCH1. The card reader control logic 24 in FIG. 22 outputs the reset signal RS.
S is manually inputted to the control input terminal PE of the program counter 169 in FIG. 16 via the 0R gate 166 and the AND gate 168, and the program counter 169 is enabled for programming.2. Signal ``0'' on P0-P4
Let I be supplied. At this time, the input terminals P5 to P7 of the program counter 169 are supplied with the code signal [0
00] is input. This code loss signal is also input to input terminals A5 to A7 of converter 161 at the same time.
Furthermore, the FF 252 of the card I/O logic (FIG. 26) is set by the reset signal RS.

Next, the clock pulse CI is transferred from the magnetic card to the data DI.
The readout clock CK,2 created from this clock pulse C is outputted with a delay of 4 bits from the clock pulse C1 (second clock pulse C1).
8), until the first clock pulse CI is read and the first read clock CKl2 corresponding to this clock pulse CJ is applied, the channel codes RC, to RC3 representing channel 1 are changed to the 26th clock pulse CI. The signal is first output from the latch circuit 248 in the figure.

(See Figures 30 and 33) - Next, when the first readout clock CKl2 is output, the readout clock CKl2 is outputted from the AND gate 90 (Figure 9), and from then on, this readout clock CK,2 is used as the system clock. Output as clock CKO. Therefore, the FF 98 and the shift register 99 are driven by this system clock CKO, and the signals SHO-SH2OJPSHO-PSH2O begin to be output. In addition, the program counter 169 (16th
) is also driven by the system clock CKO by 5 and its contents are incremented from 0 to +1, and output to the address bus 261 as address signals ADO to AD7. At this time, the RAM in the memory block 201 (FIG. 20) corresponding to channel 1 is chip-selected by the channel signal CH and signal SCHl, and the address signal ADO-AD is selected by the channel signal CH and the signal SCHl.
7 and data D read from the magnetic card.

-D7 is input to the RAM. A write command 217 is also sent to this RAM from an AND gate 186.
As a result, in accordance with the contents of the program counter 169 in FIG.
On 20, the above de L evening D. -D7 are written sequentially. When all writing is completed, a match signal A is sent from the converter 161.
=B is output, and then signal 0A-8 is output,
A signal SL-0A=3 of level "11" is input to the set input terminal R of FF47 and FF49 in FIG.
and FF49 is set.

Therefore, the signals WT and RD become "O/'. Through the above operations, all information for one tone in the magnetic card is written to block 0 in the RAM of the specified channel 1. PR/WT mode As mentioned above, if you repeat the above RD-SL mode 8 times for 8 magnetic cards that store different information for each tone, for example, all the programs (0 to 7 programs) in the RAM of channel 1 will be stored. Data for 8 tones can be stored in 8 tones.At this time, the tone select switches TSO-TS7 corresponding to programs 0 to 7 can be operated together with the channel select switch SU1.In this way, the data for channel 1 can be stored. R
The information for 8 tones written in AM is WT-A described below.
By operating in L mode, data can be written on one magnetic card. By operating the RD-SL mode described above, certain tone information can be written into an arbitrary block of an arbitrary channel of RAM (in the embodiment, an arbitrary block of RAM of an arbitrary channel). The advantage is that you can play with any tone while selecting the series tone selector switch.

(6) WT-AL mode This mode is a mode in which information for eight tones written in the RAM by repeating the above-mentioned RD-SL mode is recorded under one magnetic card.

In this example, if data in the RAM of channel 1 is to be recorded on a magnetic card, channel selection switch SU2 is operated, then all selection switch 31 is operated.
Set to the ALL side.

Then, a magnetic card with a storage capacity for eight tones is set in the card reader 23, and finally the write switch 28 is operated.

By operating the above switch, the signal ALL. WT is both 7
It becomes 1I. This allows the NAND gate 87 in FIG.
is closed and NAND gate 88 is opened, so that the system clock CKO is switched to a write clock with a frequency of 390 Hz. In addition, sampling timing signals SHO-SH2O and PSHO are output by this system clock CKO.
-PSH2O is output. Also, the gate circuit G in Fig. 5
Channel codes CC, .about.CC3 representing the channel selection switch SU2 are outputted via S3. A signal SCH is also output from the decoder 79. Also, in FIG. 22, the magnetic card is detected by the reverse switch,
When the reset signal RS is output from the card reader control logic 24, the FF 239 is activated by the reset signal RS.
(Fig. 26) The set output is 20
I, reset output becomes "1".

At the same time, the output AL-R of AND gate 173 (Fig. 16)
st) 5"1", the program counter 169 is set at this time, and its contents become O.

This program counter 169 is the system clock CK.
Each time O is output, its contents are incremented by +1.

By the way, as seen in the time chart in Figure 34,
When the program counter 169 reaches 20,
At the next timing, the output CKO-WC-PSH2O-AL of the AND gate 172 in FIG. 16 becomes "1", is reset again, and its content becomes O.

As can be seen from the time chart in FIG. 29, the signal WC is output as the signal SHl9, then the signal SH2O.
This is because when the program counter 169 in FIG. Channel code CCl~ input to side input terminal B.-B3
CC2 is recorded on the magnetic card. In addition, the channel codes CCl to CC3 and CHl allow The RAM of the memory block 201 (FIG. 20) is chip-selected, and a read command is sent to this RAM. Therefore, when the program counter 169 is reset again and its contents become O and are sequentially incremented by 1, the contents are outputted as address data ADO-AD7 and sent to the RAM of the memory block 201. At this time, since the set output of the FF 239 in FIG. 26 is "1", the select gate 243 outputs the 8-bit data D sent from the RAM. -D7 is output as 4-bit data DOO-DO3, and written to the magnetic card together with the write clock. In this way, the tone color information of the O-block is sequentially read out from the RAM and written onto the magnetic card. When the content of program counter 169 reaches 255, signal FC is output to circuit 176.
(FIG. 16), and this signal FC is applied to the reset input R of FF 47 via both 0R gates 45 and 46 (FIG. 4). Therefore, FF47 is reset and the signal WT becomes "0I", and the contents of all the programs in the RAM of channel 1 are recorded on one magnetic card.In this way, eight tones are recorded on one magnetic card. If you prepare a large number of such magnetic cards, you can read the contents of the magnetic cards into RAM before playing, as you can see from the explanation of the RD-AL mode below. A large amount of tone information can be set in a music synthesizer in a short time.

(7) RD-AL mode In this mode, information for the above 8 tones is transferred from one magnetic card to which information for the 8 tones has been written in the WT-AL mode to all programs in the RAM of any channel. This is the mode for writing.

In this case, there are cases in which a channel is specified using the channel switch and information for eight tones is copied into the RAM of the specified channel, regardless of the channel written at the beginning of the magnetic card. There are two ways to copy information into the RAM of the channel written in the channel. First, the operating method and operation when specifying a channel will be explained with reference to FIG. 35.

Set the all select switch 31 shown in Figs. 3 and 4 to the ALL side, and set one magnetic card on which information for eight tones has been written into the card reader 23 (Fig. 2). do. Next, read switch (READ) 27
Press , and finally press one channel selection switch.
For example, press SU2 for channel 1 to specify the channel. By operating the above switch, signal ALL, signal RD
Both become 21I.

Also, in FIG. 5, the gate circuit G3 is open because the signal RD-AL is "1'1." Since the channel selection switch SU2 is turned on, the priority encoder 71,
Channel codes CCl to CC3 representing channel 1 are outputted via gate circuit G3. Furthermore, a channel timing signal SCHl is output from the decoder 79. Also, because the signal AL/)5″11, the NCR gate 1
The output of 67 (FIG. 16) becomes "0/'.

Therefore, the FE terminal of the program counter 169 is always IO'' in this mode, and the program is not enabled. When the magnetic card is detected by the reverse switch and the set signal RS (Fig. 25) is output, the AND gate 173 outputs the FE terminal of the program counter 169. AL-RS becomes 7 "7," and this signal causes the program counter 169 to be reset and its contents to be "O!". ! becomes. Further, the RAM of the memory block 201 is chip-selected by the signal CHl and the signal SCHl, and a write command is output to this RAM. As mentioned in the explanation of the RD-SL mode, the read clock CKl2 used in this mode is output 4 bits later than the clock CI read from the magnetic card. Until CKl2 is output, the contents of the program counter 169 in FIG. 16 remain O and do not change, so the address signal ADO
-AD7 represents O.

During this period, the channel code CCl~C will be sent from the magnetic card.
C3 is read and input to the delay 246 in FIG. 26 as data DIO-DI3, and further data RCl to RC
2 from the latch circuit 248. However, in FIG. 5, since the channel selection switch SU2 is turned on and the output of the NOR gate 70 is 20//, the output of the AND gate JMOV also becomes "0", and the gate circuit G1 is closed. There is. Therefore, the above channel code RC
1 to RC3 are not output from the gate circuit G, and this channel code is not used. That is, channel 1 designated by channel selection switch SU2 is used, and the channel written on the magnetic card is not used.

When the read clock CK,2 starts to be output, the NAN
Since D gates 87 and 88 are closed, this clock CKl2 becomes the system clock CKO, and the program counter 169 is incremented by 1 and its contents change.

Therefore, when the address signal ADO-AD7 is first output, the addresses of the RAM of the memory block 201 are sequentially designated, and the corresponding data DO-D7 read from the magnetic card and converted into 8-bit data is written into the RAM. .
When the content of the program counter 169 reaches 255, a signal FC is output from the circuit 176.
F49 is set and the signal RD becomes 207, completing the writing of information for eight tones into the RAM of the designated channel 1.

Next, a case will be described in which information for eight tones is written into the RAM of the channel according to the channel written at the beginning of the magnetic card without specifying the channel using the channel selection switch.

The operating method is the same as in the former case except that none of the channel selection switches are operated. Since the channel selection switch is not operated, none of the signals SCHO-SCH7 from the decoder 79 (FIG. 5) is output. Also, since the output of the NOR gate 70 becomes "1", the AND
The output of the gate J and V becomes "1", and this signal 7 "7 opens the gate circuit G in place of the gate circuit G3.

The circuit operation in this case is almost the same as the former, but when channel codes RCl to RC3 are read from the magnetic card, these channel codes RCl to RC3 are outputted from the gate circuit G1 as channel codes CC, to CC3. Therefore, this channel code CCl~CC
3, the RAM of that channel is chip-selected. Then, information for eight tones is written to all the blocks in this RAM. If the information for the 8 tones in the magnetic card is copied to the RAM of the channel as described above, when playing, the tone select switch TSWO-TSW
You can freely perform with any tone while operating the 7.

(8) EX mode This mode is a mode in which the contents (timbre information) of programs in the same channel or in two different channels are exchanged with each other, and RAM 15 for temporary storage is used.

First, the operating method and operation when information stored in two programs in the RAM of the same channel are exchanged with each other will be explained with reference to FIGS. 36 and 37.

Set the all select switch 31 (Figures 3 and 4) to the select side, operate the channel selection switch of the channel to which the RAM whose contents you want to exchange belongs, for example, switch SU2 of channel 1, and
The block you want to replace in RAM, for example, block 1.
Tone select switch TSL, TS7 corresponding to and 7
operate.

Finally, operate the current switch 29. By operating these switches, the signal SL becomes 21I. Also, since both signals WT and RD are "01", N
AND gate 87 (Figure 9) opens and the frequency is 100KI.
−] Becomes the system clock CKO of z.

This system clock CKO causes the signal SHO-SH to
The frequencies of 2O, PSHO to PSH2O are also changed and output. Here, since the FF 55 (FIG. 4) is in the reset state, the output of the inverter 56 is 21'5, and the shift register 57 is reset. Then, the FF 55 (FIG. 4) is set by operating the current switch 29, and the set output signal changes the signal EX to "11".
Then, the shift register 57 is reset and shifted sequentially by the signal PSH2O. That is, this shift register 57 generates signals EXl, EX2, EX3, and EX4 each time signal PSH2O is output, and generates signals EXl, EX2, EX3, and EX4, and
It is reset and returns to the initial state when X5 is output.

The output of the channel selection switch SU, is manually inputted to the priority encoders 71, 72 (FIG. 5), and the gate circuit G3 is opened when the above-mentioned signals EXl, EX4 are output.
Furthermore, the gate circuit G4 is opened when the signals EX2 and EX3 are output.

Therefore, channel codes CCl to CC3 representing channel 1 are output from both gate circuits G3 and G4.

Further, a signal SCHO is output from the decoder 79, and is created from this signal SCHO and channel codes CCl to CC3. The RAM of memory block 201 is chip-selected by signal CHl (see FIG. 20).
Note that signals EX3 and EX3 are connected to the terminal R/W of this RAM.
4 is added to the output "11" of the AND gate 186 to receive a write command, and when the signals EX1 and EX2 are output, "0" is added to receive a read command. Furthermore, in FIG. 16, the decoder 145 The channel timing signal CHl is outputted to the channel selection switch SU2.
7 is turned on, the output of the switch TS1 is outputted through the priority encoder 147, and the output of the switch TS is outputted through the priority encoder 148. As shown in FIG. 19, the priority encoder 147 is enabled during the output period of the signals EX1 and EX2 and outputs the code signal [011] for the switch TS1 to the input terminals P5 to P7 of the program counter 169.

In addition, the program counter 169 outputs the output PSH2O-EX of the AND gate 179 for each output of the signal PSH2O.
It will be 11! Therefore, the program is enabled and a signal 207 is applied to its input terminal PO-P4.

Furthermore, the temporary storage RAM198 (Fig. 20) is chip-selected by the signal EX1, EX2.
When outputting, a write command is received and signals EX3 and EX are output.
When outputting 4, a read command is received.

Furthermore, the address terminal AD5 of RAM198 is the signal EX2.
, EX4 is held at the "11" level by these signals. Since each signal is output as described above, the first signal PSH2O is output after the 1st switch 29 is turned on. Then, the signal EXl is output and becomes the 21I level, and the second signal PSH2 is output.
It is held until O is output. Also, the first signal PS
The program counter 169 is program-enabled by H2O, and the tone select switch T output from the priority encoder 148 is input to the input terminals P5 to P7.
The code signal "111" of S7 is input. Therefore, the content of the program counter 169 becomes 224, and the RA
The starting address of M's block (BL7) is given.

The program counter 169 is incremented by 1 each time the system clock CKO is input, and its contents are the address signal A.
It is output as DO-AD7 and applied to the address input terminal of the RAM of the memory block 201 and the address input terminal ADO-AD4 of the temporary storage RAM 198. Therefore, the information in block 7 of RAM of memory block 201 is sequentially transferred to block 0 of RAM 198 (because RAM 16
When the first signal PSH2O is output, "0" is added to the address input terminals ADO-AD7 of 9, and thereafter it is incremented by 1 along with the program counter 169, and its contents change from address O to address 20. This is because it corresponds to block 0.

) is written. FIG. 37 diagrammatically shows this situation. When the contents of the program counter 169 reach 244, this write operation is completed, and then the second signal P
SH2O is output. This signal PSH2O outputs the signal EX2, and the program counter 16
9 is program enabled and its input terminal P.

- Signal "0I" is applied to P4, and input terminals P5 to P7
The switch TS output from the priority encoder 147 is
The code signal "001" of 1 is input.

As a result, the contents of the program counter 169 are set to the starting address 32 of block 1 of the RAM of the memory block 201, and thereafter are incremented by 1 to reach 42.

On the other hand, the address manual end ADO of temporary storage RAM 198
- In AD5, when the second signal PSH2O is output, only the input terminal AD5 becomes "1/I" and address 32 is set. This is the start address of block 1 of RAM 198. Therefore, the signal During the output of EX2, the contents of block 1 of RAM of memory block 201 are transferred to RAM for temporary storage.
Written to block 1 of M198. When the contents of the program counter 169 reach 52, this write operation is completed, and then the third signal PSH2O is output, and at the same time E
X3 becomes 2"7.

In a manner similar to that previously described, program counter 169 is now program enabled and input terminal P5 is
〜P7 receives the code signal ``0011'' of the switch TSL, and the contents of the program counter 169 become 32 again.
becomes. On the other hand, all address inputs of RAM 198 are '
/07, and block 0 of RAM 198 is designated. From this point on, a read command is output to the RAM 198, and a write command is output to the RAM in the memory block 201. Therefore, the information written in block 0 of RAM 198 (that is, the information written in block 2 of memory
The information stored in block 7 of RAM 01) is written to block 1 of RAM 201 of memory block 201. When this operation is completed, the fourth signal PSH2O is output, and at the same time, the signal EX4 is output. At this time, the contents of program counter 169 are set to 224, and RAM 198 is set to 32. For this reason, RAMl
The information of block 1 of memory block 201 (that is, the information originally stored in block 1 of RAM of memory block 201) is written to block 7 of RAM of memory block 201.

When this operation is completed, the signal EX becomes O, and all operations are completed. As a result, R of memory block 201
The contents of AM block 1 and block 7 are exchanged with each other. Next, a case will be explained in which information of one block of two channels is mutually exchanged.

In this example, for example, tone select switch TS1 of channel 1 (block 1 of RAM of memory block 201) and tone select switch TS7 of channel 4 are selected.
(RAM block 7 of memory block 203) information is to be exchanged.

At this time, all select switch 31 is set to the select side, and channel select switches SU2 and SL2 and tone select switches TS1 and TS7 are operated, respectively. Finally, operate the current switch 29. Since the operation at this time is almost the same as in the case of exchange within the same channel, detailed explanation thereof will be omitted. FIG. 38 schematically shows this operation. In FIG. 5, the output of channel selection switch SU2 is input to priority encoder 71, and channel selection switch SL
The output of No. 2 is input to the priority encoder 72. Therefore, the channel codes CCl to CC3 that are output when the signals EXl and EX4 are output become channel 1 (CHl),
Further, the channel codes CCl to CC3 outputted when the signals EX2 and EX3 are outputted become channel 4 (CH4).

Therefore, memory block 201 and memory block 203 shown in FIG. and the information exchange of block 7 is executed. As described above, since information can be exchanged between any blocks in the RAM of any channel, the arrangement of tone information corresponding to the tone select switch can be changed arbitrarily, and performances can be performed using the keyboard convenient for the performance. There are advantages.

[η Effects of the Invention As explained above, according to the present invention, a plurality of first digital data obtained by digitally converting a plurality of analog voltages corresponding to the operating state of each operator and an output signal of each switch are respectively converted into digital data. Since the second digital data assigned to the bits is time-division multiplexed and transferred to the storage device, the number of data input lines of the storage device is reduced, simplifying the configuration, and Since the first and second digital data can be stored sequentially and continuously, the storage device can be used efficiently and its storage capacity can be reduced.

Furthermore, when converting each of the analog voltages into digital data, each analog voltage is time-division multiplexed and input to the A/D converter.
There is an advantage that only one converter is required.

[Brief explanation of drawings]

The drawings are according to one embodiment of the present invention; FIG. 1a is an overall configuration diagram of an electronic musical instrument including a timbre control device of the same example, and FIG. 1b is a musical tone forming control used in a synthesizer-type electronic musical instrument. A waveform diagram, FIG. 2 is an overall configuration diagram of the tone control device of the same example, FIG. 3 is a plan view of the operation panel of the same example, and FIGS. 4 and 5 are separated views of the panel control logic 25 of the same example. 6 is an operational waveform diagram of the pulse generating circuit 37 in the panel control logic 25 of the same example, FIG. 7 is an operational waveform diagram of the pulse generating circuit 50 of the same example, and FIG. 8 is a circuit configuration diagram shown in FIG. is an operating waveform diagram of the pulse generation circuit 64 of the same example, FIG. 9 is a circuit configuration diagram of the clock generator 18 and timing pulse generator 19 of the same example, and FIG. 10 is an operation waveform diagram of the prohibition signal generation circuit 94 of the same example. FIG. 11 is a waveform diagram of the sampling timing signal of the same example, and FIG. 12 is a waveform diagram of the timbre setting board 16 and A/D converter 17.
13 and 14 are A/D circuit diagrams of the same example.
An operating waveform diagram of the converter 17, FIG. 15 is a circuit configuration diagram of the D/A converter 20 and sample-hold/latch circuit 21 of the same example, and FIG. 16 is a circuit configuration of the tone selector 10 and address generator 11 of the same example. 17 is an operating waveform diagram of the signal 0A-3 generating circuit 162 of the same example, FIG. 18 is an operating waveform diagram of the signal FC generating circuit 176 of the same example, and FIG. 19 is an operating waveform diagram of FF159 of the same example. , FIG. 20 shows the circuit configuration of the memory device M of the same example, in which the memory control logic 12, RAM1
3. Circuit configuration diagram of ROMl4, R, AMl5, FIG. 21 is a conceptual diagram of the storage area of RAMl3 and ROMl4 in the same example,
22 is a circuit configuration diagram of the card reader control logic 24, FIGS. 23 and 24 are operational waveform diagrams of some circuits of the card reader control logic 24, and FIG. 25 is a write mode of the card reader control logic 24. Or the operation waveform diagram in read mode, Figure 26 shows the card I/O of the same example.
A circuit configuration diagram of the logic 22, FIG. 27 is an operating waveform diagram of the write clock CC generation circuit 235 of the same example, FIG. 28 is an operating waveform diagram of the X2 multiplier 253 and FFs 26l to 264, etc. of the same example, and FIG. is the above card I/0 logic 22
FIG. 30 is an operating waveform diagram of the card I/0 logic 22 in read mode, FIG. 31 is an operating waveform diagram of the same example in R/R mode, and FIG. 32 is an operating waveform diagram of the same example in write mode. FIG. 33 is an operational waveform diagram in the performance mode of the same example, FIG. 34 is an operational waveform diagram in the RD-SL mode of the same example, and FIG. 34 is a W waveform diagram of the same example.
The operating waveform diagram in T-AL mode, Figure 35 is the RD of the same example.
- An operating waveform diagram in AL mode, Figure 36 is an operating waveform diagram when exchanging the contents of the program in the same channel in EX mode of the same example, and Figure 37 shows the state of EX mode in Figure 36. FIG. 38 is a diagram schematically showing a state when the contents of programs in different channels are exchanged in the EX mode of the same example. TVRO-TVRl9... Analog voltage generation means, 101, 102, 103... Multiplexing means,
109...Analog/digital conversion means, T
SW2O to TSW25... Switch data generation means, 115, 118, 119... Selection means,
13, 23... Storage means, 20... Digital/analog conversion means, 21a (S/HO-S/
Hl9)... Holding means, 21b (143)
・・・・・・Latch means.

Claims (1)

[Scope of Claims] 1 a. Analog voltage generating means for generating a plurality of analog voltages corresponding to the operation states of a plurality of operators that control the timbre of musical sounds; and b. Each analog generated by the analog voltage generating means. multiplexing means for sequentially selecting and outputting voltages in a time-division manner; c. analog/digital conversion means for converting the analog voltage output from the multiplexing means into first digital data; and d. The second one assigns each output signal of the plurality of switches to be controlled to each bit.
switch data generating means for generating digital data; e. selecting the first digital data regarding each of the operators sequentially output from the analog/digital converting means in synchronization with the time-sharing timing for the operators; , by selecting the second digital data output from the switch data generating means in synchronization with the switch time division timing, the first and second digital data are
1. A timbre control device for an electronic musical instrument, comprising: a selection means for multiplexing and outputting digital data together; and a storage means for storing the digital data successively output from the selection means. 2 a. Digital/analog conversion means for converting the first digital data output from the storage means into analog data; b. Storing the analog voltage output from the digital/analog conversion means; c. a latch means for storing the second digital data outputted from the storage means and outputting the stored data to the musical tone formation circuit. A timbre control device for an electronic musical instrument according to claim 1.