JPS5923622A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To obtain a high-precision, high-speed D/A converter economically by using low-precision, high-speed universal D/A converters as subordinate D/A converters. CONSTITUTION:The D/A converter is equipped with subordinate universal D/A converters 5-7 and a code conversion part 8. All digits of a digital input signal are divided into partial digital signals d(5)-d(7) which overlap one another at respective boundaries of adjacent subordinate D/A converters by at least one digit, and those digital signals are supplied to the respective converters 5-7. Partial analog signals i(5)-i(7) from the converters 5-7 are weighted and then summed up to generate an analog output signal (i). This output signal (i) is observed and the code conversion part 8 corrects the respective partial digital signals so that the relation to the digital input signal (d) is linear. Thus, the high-precision, high-speed D/A converter is obtained economically.

Description

DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to a digital analyzer and 1-cog converter, particularly a high-speed and highly accurate digital analog 1-cog converter that converts a digital input signal of a predetermined digit into an analog output signal. Concerning vessels.

Background of fbl technology In recent years, as digital technologies such as digital communication and digital signal processing have come to a standstill, emphasis has been placed on fields of use such as outputting and displaying precise figures processed by electronic calculators as quickly as possible. be.

In such fields, highly accurate, high speed, and economical digital-to-analog converters are required.

tc+ Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional digital-to-analog converter. In Figure 1, 2 i1! A digital-to-analog converter is shown which converts a 10-digit digital input signal d into an analog output signal 5; The digital-to-analog converter receives a current supplied from the reference power supply 3.
Digital input signal (ratio corresponding to each digit of 1?9.N
, . . . :2' and transmits current to the switches 2-0 to 2-9. These current sources 4-0 to 4-9 are composed of, for example, a resistor connection network, a constant current circuit, and the like. The switch setting section 1 includes a switch 2-x (x is 1
9) is set to the terminal 1 side, and the switch 2-x corresponding to the digit of logical value 0 is set to the terminal 1 side. As a result, current is added by the current source 4-x corresponding to the logical value 111 to form an analog output signal i, which is output from the terminal I.

As is clear from the above explanation, in a conventional digital-to-analog converter, current sources 4-0 to 4-9 are provided corresponding to all digits of the input digital input signal d, and current sources 4-0 to 4-9 are provided corresponding to all digits of the logical value 1. The analog output signal i was created by adding the currents.

As a result, in a highly accurate and high speed digital-to-analog converter that converts, for example, an 18-digit digital input signal d, highly accurate current distribution is also required for the current sources 4-0 to 4-17. When each mold flow source 4-0 to 4-17 is composed of individual parts, fine adjustment is required to adjust the mismatch of each part, and when realized by an integrated circuit, Trimming 1 or some circuitry is required.

Furthermore, in the case of using individual components, expensive components such as high-speed transistors are used, and high-speed operation is difficult due to an increase in free capacitance when a large current is passed.

Furthermore, if integrated circuits are used, they will be expensive unless they are mass-produced, making it difficult to put them into practical use.

+d+ OBJECTS OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional digital-to-analog converters as described above, and to economically realize a high-viscosity, high-speed digital-to-analog converter.

(el) Structure of the Invention The object of this invention is to provide a digitizer for converting a digital input signal of a predetermined digit into an analog output signal, in which a plurality of digital signals of the number 111 less than the predetermined number of digits are converted into an analog signal. sub-digital-to-analog converters are provided, and all digits of the digital input signal are divided into partial digital signals such that at least one digit overlaps at each boundary of the adjacent sub-digital-to-analog converters. A weight corresponding to the corresponding partial digital signal (=
This is achieved by creating the analog output signal by adding up the digital input signals and correcting each of the partial digital signals so as to maintain linearity in the relationship between the digital input signal and the analog output signal. .

ffl　Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a digital-to-analog converter according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of a partial digital signal in FIG. 2, and FIG. 4 is a diagram showing an example of a partial digital signal in FIG. FIG. 3 is a diagram showing an example of a partial analog signal. Note that the same reference numerals indicate the same objects throughout the drawings. In FIG. 2, °ζ indicates a digital-to-analog converter that converts an 18-digit binary digital input signal d into an analog output signal l.

The digital-analog converter includes 311M sub-digital-analog converters 5, 6 and 7, and a code converter 8. Each of the sub-digital-to-analog converters 5, 6 and 7 is a general-purpose digital-to-analog converter having a configuration similar to that shown in FIG. A binary IO digit digital signal is converted into an analog signal and output from terminal l. Similarly, the sub digital analog converters 6 and 7 also have terminals DO to I]7, respectively.
Convert the 8-digit binary digital signal input from the terminal into an analog signal and connect it to the terminal! Output from. Further, the code conversion unit 8 divides each digit of the digital input signal d input from the terminals DO to 1]17 as shown in FIG. 7) and transmits it to the terminals D0 to D9 or brr and + terminals DO to D7 of the sub digital-to-analog converters 5.6 and 7, respectively.6 In FIG. 3, the partial digital signal d (5) is Input signal ': The partial digital signal d (6) is similarly applied to the 8th to 17th digits of J-d, and the partial digital signal d (7) is similarly applied to the 0th to 10th digits. Each corresponds to 7 digits. Therefore, the 8th to 10th digits of the digital input signal d overlap and correspond to the partial digital signals d (5) and d (6), and the 3rd to 7th digits of the digital input signal d correspond to the partial digital signal d (5) and d (6). It corresponds to d (6) and d (7) in duplicate. Each of the sub-digital-to-analog converters 5.6 and 7 converts the inputted partial digital signals d(5), d(6) and d(7) into partial analog signals i(5), respectively, using the same principle as described above. , + (6) and i (7) and output. The partial analog signal i (6) is weighted by resistors R1 and R2, and the partial analog signal i (7) is weighted by 11°C resistors R3 and R4, respectively.
It is added with No. a I (5) to create an analog output signal I, which is output from the terminal summer. The weights τJ are calculated for each corresponding partial digital signal d (6) and d (7)
is defined by the position of one row in the digital input signal d relative to the partial digital signal d (5). As shown in FIG. 3, partial digital signals d (6) and d
The maximum digit of (7) is seven and ten digits lower than the maximum digit of partial digital signal d(5), respectively. Therefore, 141i worth of analog signal i due to resistors R1 and R2
The weight for (6) is set to 1/128, and the weight for partial analog signal i (7) due to resistors R3 and R4 is set to 1/1024. Observing the analog output signal i obtained in this way, code conversion is performed on each partial digital signal d (5), d ((
Add corrections to i) and d(7). Next, the principle of correction will be explained based on FIG. In addition, in FIG. 4, for convenience, only the partial analog signal I (5) and l (6) after being subjected to heavy amplification are shown;
(7) is omitted. Partial digital signal d (5
) is a partial analog signal i (5) in which a minimum of 11 bits is increased by 1 bit in the digital input signals da, db and dc, and is output from the sub-digital analog converter 5.
are respectively ia −, ib and ic. Note 1
c-ib is equal to the theoretical value Δi, but 1b-ia is the deviation Δi+ within the tolerance of the sub-digital analog converter 5.
Δi′.

As a result, even though the sub-digital-to-analog converter 6 has a substantially linear relationship between the partial digital signal d (6) and the partial analog signal 1 (6), the digital input signal d changes from da to db. If it changes to dC via
The analog output signal i does not change linearly. In order to eliminate such drawbacks, the digital input signals da and db
In between, the partial digital signal d (6) input to the sub-digital to analog converter 6 is inputted to the partial analog signal i.
The code conversion unit 8 makes a correction such that (6) is increased by Δi' to become l (6) '. Note that the digit that overlaps with the partial digital signal d (5) (digital input signal d
8th to 10th digits)? The nonlinearity of the analog output signal i in the digital input signal db is corrected by the equation 6, which is effective in expanding the possible range of positive ili.

As is clear from the above description, according to this embodiment, the digital-analog converter that converts the 18-digit binary digital input signal d into the analog output signal i is a general-purpose sub-digital analog converter 1:' 5 (10 digits), 6 and 7 (
Since each of them consists of 8 digits), the technical and economical problems mentioned above are solved.

Note that FIGS. 2 to 4 are only one embodiment of the present invention, and for example, partial digital signals d (5), d (
6), d (7) and the number of digits of the digital human input signal d are not limited to what is shown in the figure, and the results of the present invention do not change in the case of any other number of digits. Furthermore, the digital analog converter 1 and the J-G converter are not limited to the three sub-digital analog converters 5, 6 and 7 shown in the figure, and many other modifications may be considered; Even in this case, the effects of the present invention remain the same.

+g) Effects of the Invention According to the present invention, a high-precision and high-speed digital-to-analog converter can be realized economically by using a low-precision and high-speed general-purpose digital-to-analog converter as a sub-digital to analog converter. becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional digital-to-analog converter, FIG. 2 is a diagram showing a digital-to-analog converter according to an embodiment of the present invention, and FIG. 3 is a diagram showing a 2rg! FIG. 4 is a diagram showing an example of the partial digital signal in J. FIG. 4 is a diagram showing two sides of the partial analog signal in FIG. In the figure, 1 is a switch setting section, 2-0 to 2-9 are switches, 3 is a reference power source, 4-0 to 4-9 are current sources,
5 to 7 are sub-digital analog converters, 8 is a code converter, DO to D17 and summer terminals, d, da, db and dc are digital input signals, is ia, ib
and 50 are analog output signals, d (5), d (6
) and d(7) are partial digital signals, i(5)
, f (6) and i (7) are the partial analog signals, Δi and Δi' are the differences in the analog output signals, and do not indicate. 1$ 1 day early 2 Figure/7IIr! Iarlrλure啼#76f492r. Figure 5 db db dc
≠ 4 Figure

Claims (1)

[Claims] A digital-to-analog converter for converting a digital human input signal of a predetermined tli into an analog output signal is provided with a plurality of sub-digital-to-analog converters for converting a digital signal having a number of digits less than the predetermined number of digits into an analog signal, and the digital input signal is All digits are divided into partial digital signals such that at least one digit overlaps at each boundary of the adjacent sub-digital-to-analog converters, and input to each of the sub-digital-to-analog converters; The analog output signal is created by weighting and processing the partial analog signal output from the converter in a manner equivalent to the corresponding partial digital signal, and the analog output signal is combined with the digital input signal and the analog output signal. A digital-to-analog converter, characterized in that each of said partial digital signals (M"J-) is corrected so as to maintain linearity in the relationship.