JPS5923542A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPS5923542A
JPS5923542A JP13193382A JP13193382A JPS5923542A JP S5923542 A JPS5923542 A JP S5923542A JP 13193382 A JP13193382 A JP 13193382A JP 13193382 A JP13193382 A JP 13193382A JP S5923542 A JPS5923542 A JP S5923542A
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
conductor layer
wiring conductor
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13193382A
Other languages
Japanese (ja)
Inventor
Takashi Nishida
西田 高
Atsushi Saiki
斉木 篤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13193382A priority Critical patent/JPS5923542A/en
Publication of JPS5923542A publication Critical patent/JPS5923542A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To improve the reliability of a high molecular resin-sealed device by forming high moisture resistance wirings of an alloy of Ni, si of specific compositions by weight and the residue of aluminum on a semiconductor substrate. CONSTITUTION:A wiring layer which contains 0.01-2.5wt% of Ni, 0.5-4wt% of Si and the residue of aluminum is formed on a semiconductor substrate which has a PSG or high molecular resin layer on the surface. Preferably, Ni is 0.1-1wt%, Si is 1-2wt%. If the contents of the Ni and Si are out of these range, the moisture resistance decreases. When the wiring layer is covered with polyimide and/or PIQ resin, the heat resistance is improved. This composition can effectively perform the effects in case of resin sealing, and even when this is applied to a multilayer wiring structure, the moisture resistance and reliability can be extremely improved.

Description

【発明の詳細な説明】 本発明は耐湿信頼度の改善された半導体装置に関し、特
に樹脂封止された前記半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device with improved moisture resistance reliability, and particularly to the semiconductor device sealed with resin.

樹脂封止した半導体装置における信頼度上の問題は耐湿
信頼度である。高温高湿下において、水分は樹脂中に浸
透し、半導体表面に達し、At配線を腐食させ、半導体
装置をやがては故障に至らしめる。
A reliability problem in resin-sealed semiconductor devices is moisture resistance reliability. Under high temperature and high humidity conditions, moisture penetrates into the resin, reaches the semiconductor surface, corrodes the At wiring, and eventually causes the semiconductor device to fail.

このような不良を避けるには、セシミツク封止が完全で
あるが、価格が約10倍も高くなるので、特に高い信頼
度が必要なデバイス以外には適用することは困難な実情
にある。また配線の下地拐料には、第1パツシベーシヨ
ン膜としてリンを含む5i02(以下、リンを含むガラ
スもしくはPSGと記す)膜が用いられているのが通常
であり、浸透して来た水分によってリンが溶出し、これ
がAtの腐食をさらに促進する作用をなしていた。
To avoid such defects, complete sealing is possible, but the cost is about 10 times higher, so it is difficult to apply it to devices other than those that require particularly high reliability. In addition, a phosphorus-containing 5i02 (hereinafter referred to as phosphorus-containing glass or PSG) film is usually used as the first passivation film for the wiring substrate, and the penetrating moisture can cause phosphorus to be removed. was eluted, which acted to further accelerate the corrosion of At.

さらに、最近の高集積化の何1向に対応して配線層も1
層から2層さらには3ル:1と増加しているが、配線層
間絶縁膜としては、プt1セスコストが小さく、配線歩
留υも高く、樹脂封止のときのモールドストレスに対し
てもクラックの生じないポリイミド樹脂膜もしくはポリ
イミド・インインドロ・キナゾリンジオン樹脂膜が多く
用いられるようになっているが、この場合も樹脂材料で
あるため、水分の浸透を完全には防止しきれない。この
ため、配線の下地の第1パッシベーションMがPSG[
で、さらにポリイミド系樹脂で保許された配線構造を有
する樹脂封止された半導体装置あるいはさらに第2層、
第3層の配線がポリイミド系絶縁膜を介して構成され、
ポリイミド系樹脂膜で保睦された配線構造を有する樹脂
制止半導体素子などの耐湿信頼度のレベルは、民生用の
半導体素子に必要な規準は十分に有していても、さらに
その上の産業用の半導体素子に必要な(Jl、準を満た
すには、必らずしも十分であるとはいいがたかった。
Furthermore, in response to the recent trends toward higher integration, the number of wiring layers has also increased to one layer.
Although the number of layers has increased from 2 layers to 3 layers to 1:1, as a wiring interlayer insulating film, the process cost is low, the wiring yield υ is high, and it is resistant to cracks against mold stress during resin encapsulation. Polyimide resin membranes or polyimide-in-indolo-quinazolinedione resin membranes that do not cause water are increasingly being used, but since these are also resin materials, they cannot completely prevent moisture from penetrating. Therefore, the first passivation M at the base of the wiring is PSG [
Then, a resin-sealed semiconductor device having a wiring structure protected by polyimide resin or a second layer,
The third layer wiring is configured via a polyimide insulating film,
Although the level of humidity resistance of resin-sealed semiconductor devices with wiring structures protected by a polyimide resin film is sufficient to meet the standards required for consumer-use semiconductor devices, it is still difficult to meet the standards required for industrial use. It could not be said that it was necessarily sufficient to satisfy the standard (Jl) required for semiconductor devices.

したがって本発明の目的は、耐湿性に侵れた新しいAt
基合金を配線材料に用いることによって、信頼度の高い
半導体装置、特に高分子樹脂からなる絶縁層を有する半
導体装置を提供することにある。
Therefore, the object of the present invention is to provide a new At
The object of the present invention is to provide a highly reliable semiconductor device, particularly a semiconductor device having an insulating layer made of a polymer resin, by using a base alloy as a wiring material.

上記目的を達成するため、本発明の半導体装置は、0.
01〜2.5 w 1%のNt、o、5〜4.Qwt%
のS’および残余がAtからなる組成の合金で構成され
た配線導体層を半清7体基板上に有するものである。N
i量のよシ望ましい範囲は0.1〜1、□wt%、Si
量のよシ望ましい範囲は1.0〜2、 OW 1%であ
る。Ni量およびSi量が前記範凹外でおると、耐湿信
頼性が低下して好ましくない。
In order to achieve the above object, the semiconductor device of the present invention has 0.
01-2.5 w 1% Nt, o, 5-4. Qwt%
A wiring conductor layer made of an alloy having a composition of S' and the remainder At, is provided on a semi-solid substrate. N
The desirable range of i amount is 0.1 to 1, □wt%, Si
A desirable range of the amount is 1.0 to 2, OW 1%. If the amount of Ni and the amount of Si are outside the above range, the moisture resistance reliability will decrease, which is not preferable.

本発明の半導体装置は、通常、前記配線導体層の少なく
とも一部が、高分子樹脂によシ被腐されているものとす
る。
In the semiconductor device of the present invention, at least a portion of the wiring conductor layer is normally corroded by a polymer resin.

また、前記半導体基板は、少なくとも1表面に絶縁膜を
具備するものを用いると好都合であシ、この場合、前記
配線導体層は少なくともその一部し、この場合に本発明
の効果が顕著に認められる。
Further, it is advantageous to use a semiconductor substrate having an insulating film on at least one surface, and in this case, the wiring conductor layer is at least a part of the semiconductor substrate, and in this case, the effects of the present invention are significantly observed. It will be done.

しかし、これに限定する必要はない。However, it is not necessary to be limited to this.

配線導体層を被履する上記高分子樹脂や上記絶縁膜を構
成する高分子樹脂には、いずれも、ポリイミド樹脂およ
び/もしくはポリイミド・インインドロ・キナゾリンジ
オン樹脂を用いると、耐熱性の点から有利である。
It is advantageous in terms of heat resistance to use polyimide resin and/or polyimide indolo quinazolinedione resin as the polymer resin covering the wiring conductor layer and the polymer resin constituting the insulating film. be.

本発明の半導体装置は多層配線構造としてもよく、この
場合、前記配線導体層が少なくとも2層からなシ、その
上部側の配線導体層はその下に位置する配線導体層の少
なくとも一部を被履する高分子樹脂層上に形成され、且
つ該上部側の配線導体層の少なくとも一部が高分仔樹脂
により被履されるように構成すると、特に好都合である
。この高分子樹脂も前述のポリイミド樹脂および/もし
くはポリイミド・イソインドtz・キナゾリンジオン樹
脂を用いることができる。
The semiconductor device of the present invention may have a multilayer wiring structure. In this case, the wiring conductor layer has at least two layers, and the upper wiring conductor layer covers at least a part of the wiring conductor layer located below. It is particularly advantageous if the upper wiring conductor layer is formed on a polymer resin layer to be worn, and at least a part of the wiring conductor layer on the upper side is covered with the polymer resin. As this polymer resin, the aforementioned polyimide resin and/or polyimide/isoindotz/quinazolinedione resin can be used.

上記配線導体層を、必要に応じて、半導体基板表面の絶
縁膜の開孔部を経由し−C半導体ウェーハの所定部分に
接続せしめ、′?fた必列に応じて、層間絶縁層の所定
の開孔部を経由して上下の配線導体層を互に接続せしめ
るようにイ”1q成できることは言うまでもない。
If necessary, the wiring conductor layer is connected to a predetermined portion of the -C semiconductor wafer via an opening in an insulating film on the surface of the semiconductor substrate. It goes without saying that the upper and lower wiring conductor layers can be connected to each other via predetermined openings in the interlayer insulating layer depending on the necessity.

本発明の上記半導体装置は、いずれも、樹脂封止して用
いた場合に、もつともその効果を期待できる。しかし、
樹脂封止した場合に限らず、半導体装置の耐湿信頼性を
向上させる場合一般に、本発明を適用できる。
Any of the above semiconductor devices of the present invention can be expected to have the same effect when used in a resin-sealed manner. but,
The present invention is applicable not only to the case of resin sealing but also to any case where the moisture resistance reliability of a semiconductor device is to be improved.

ところでA7の腐食に対しては、一般に異種金属を加え
ると多少なυとも効果のあることが知られており、有効
な金属としてN’+Fe+Cut’I’i+ Crt 
MO,wl P t+ Pdなどがあげられて卦シ、−
!た逆にMg、Zn+ Ag、M膠。
By the way, it is generally known that adding different metals has some effect on corrosion of A7, and N'+Fe+Cut'I'i+ Crt is an effective metal.
MO, wl P t+ Pd, etc. are listed, and the -
! On the contrary, Mg, Zn + Ag, M glue.

Snなどは無効もしくは有害とされている(電気化学便
覧、電気化学便覧編、丸善、1964年、第927頁)
。しかしながらこれらの知見i1: A tの構造相料
から得られたものであって、半導体装1g。
Sn, etc. are considered to be ineffective or harmful (Electrochemistry Handbook, edited by Electrochemistry Handbook, Maruzen, 1964, p. 927)
. However, these findings i1: were obtained from the structural phase material of At, semiconductor device 1g.

に用いられる厚さ1μm程度の極めて高純度の蒸着At
膜についても同様に有効であるとは断言できない。
Extremely high-purity vapor-deposited At with a thickness of about 1 μm used for
It cannot be asserted that membranes are similarly effective.

そこで上記の有効とされた金属のうち蒸着によシAtと
合金化薄膜を形成し1nる金Fj戎をいくつかとυ上げ
て、耐湿信頼性を評価した。面1湿試験としては、樹脂
封止された半導体素子でよく用いられている周知のプレ
ッシャークツカーテスト(以下、P CTと記す、12
(1’、2気圧の水蒸気中に放置する)を採用した。評
価用試作は、次のようにA、Bの2とうシに作成した。
Therefore, among the above-mentioned effective metals, a thin film alloyed with At was formed by vapor deposition, and some gold Fj was used to evaluate the moisture resistance reliability. The surface 1 humidity test is performed using the well-known Pressure Test (hereinafter referred to as PCT), which is often used for resin-sealed semiconductor devices.
(Leave it in water vapor at 1' and 2 atmospheres) was adopted. Two prototypes, A and B, were made for evaluation as follows.

すなわちAは、8’基板表面に形成したPSG膜(厚さ
0゜7μm)」二に配線パターン(厚さ1μm)を作成
し、ポリイミド系樹脂(厚さ2,5μm)による保護膜
を形成した。ポリイミド系樹脂としてPIQ(日立化成
(株)の商品名)を用いた。Bは、Si基板上にPIQ
膜(厚さ2.5μm)を形成し、この上に配線パターン
(厚さ1μm)を形成してさらにPIQによる保護膜(
厚さ2.5μm)を形成した。
That is, A is a PSG film (0°7 μm thick) formed on the surface of the 8′ substrate.Secondly, a wiring pattern (1 μm thick) was created, and a protective film made of polyimide resin (2.5 μm thick) was formed. . PIQ (trade name of Hitachi Chemical Co., Ltd.) was used as the polyimide resin. B is PIQ on Si substrate
A film (thickness: 2.5 μm) is formed, a wiring pattern (thickness: 1 μm) is formed on this, and a protective film (of PIQ) is formed.
A thickness of 2.5 μm) was formed.

これらの試験試料に対して1) C’I”を施こし、腐
食開始時間を評価した結果を第1表に示す。
1) C'I'' was applied to these test samples and the corrosion initiation time was evaluated. The results are shown in Table 1.

その結果、効果あシとされた元素は、蒸着薄膜として評
価した場合、はぼ有効であることが確認できたが、それ
ぞれ効果に著るしい違いがあり、中にはTiのように殆
んど効果のないものも見られた。しかしながらht−N
iのNiの濃度1〜2、5 w t%とAt−Pd(起
t%)については、最もよい腐食防止効果を示した。こ
れは試料AおよびBについて共通の傾向であった。
As a result, it was confirmed that most of the elements considered to be effective are effective when evaluated as thin films deposited, but there are significant differences in their effects, and some, like Ti, have very little effectiveness. There were also some cases that had no effect. However, ht-N
The best corrosion prevention effect was shown for Ni concentration of 1-2.5 wt% and At-Pd (at t%). This was a common trend for samples A and B.

さらに腐食防止に最も有効な組み合せであったAt−P
dとht−Niをペースにさらに第3の元素を加えて同
様の試験をカ1;こした。得られた結果を第2表に示す
Furthermore, At-P was the most effective combination for corrosion prevention.
A similar test was conducted using d and ht-Ni as a pace and adding a third element. The results obtained are shown in Table 2.

第   1   表 第   2   表 その結果、AA−Pdと他の金属元素との組み合わせで
はさほどの腐食防止効果の向上はみられなかった。寸た
ht−Niと他の金が元素のうちSi以外の金属との組
み合せはさほどの効果の向上はみられなかったが、ht
−NiとSsの組み合わせにおいては、さらに効果の相
乗性を見出せた。これは試料Aおよび試別13において
共通の傾向として見られた。
Table 1 Table 2 As a result, the combination of AA-Pd and other metal elements did not significantly improve the corrosion prevention effect. Combinations of small ht-Ni and other metals other than Si among gold elements did not show much improvement in effectiveness, but ht
- In the combination of Ni and Ss, even more synergistic effects were found. This was seen as a common tendency in sample A and sample 13.

次にht−Ni−8iの合金薊j摸中のNi及びBrの
有効濃度範囲について検問した結果を第3表に示す。そ
の結果各元素の有効濃度は、Nt;0.01〜2.5 
w t% 5ii0.5 〜4  wt% であることがわかった。
Next, Table 3 shows the results of an investigation regarding the effective concentration range of Ni and Br in the ht-Ni-8i alloy sample. As a result, the effective concentration of each element is Nt: 0.01 to 2.5
It was found that wt% was 5ii0.5 to 4 wt%.

以下、本発明を実施例によシさらに詳細に説明する。Hereinafter, the present invention will be explained in more detail using examples.

第   3   表 実施例1 第1図において、シリコンウェー” 1 上KPsG膜
2を形成したのち、第1の配線導体/R3を形成した。
Table 3 Example 1 In FIG. 1, after forming the KPsG film 2 on the silicon wafer 1, the first wiring conductor /R3 was formed.

次に層間絶縁膜4をPIQによシ形成したのちスルーホ
ール加工を行ない、次いで第2の配線導体層5を形成し
、さらに保腟膜6を再びPIQによシ形成した。保爬膜
6には、外部とワイヤホンディングするための開口を設
けた。
Next, an interlayer insulating film 4 was formed by PIQ, followed by through-hole processing, a second wiring conductor layer 5 was formed, and a vaginal protection film 6 was again formed by PIQ. The retention membrane 6 was provided with an opening for wire bonding with the outside.

この構造において、配線導体層3および5d:次のよう
に形成した。はじめにAtを500人蒸差したのちNi
を30人蒸着し、次いでSiを150人、更にAtを9
500人蒸光蒸着のぢ400C〜450Cでアニールし
て合金化した。次でホトエツチングによυ配線パターン
を形成した。層間絶縁膜および保護膜についてt”l、
PIQのプレポリマー溶液を回転塗布したのち200C
で60分、350Cで30分のベークを行なって形成し
た。
In this structure, wiring conductor layers 3 and 5d were formed as follows. First, after steaming 500 At, Ni
30 people evaporated, then 150 people deposited Si, and then 9 people deposited At.
It was annealed at 400C to 450C using 500-person photoevaporation to form an alloy. Next, a υ wiring pattern was formed by photoetching. Regarding the interlayer insulating film and protective film t”l,
200C after spin coating PIQ prepolymer solution
It was formed by baking at 350C for 60 minutes and 30 minutes at 350C.

膜厚は2μmとした。また配線層間のスルーホールおよ
びポンディングパッドの開口の形成ハ、ホトレジストに
ネガタイプのOM几83(東京応化(株)商品名)を用
い、エッチャントにヒドラジンとエチレンジアミンの混
合液を用いて行なった。
The film thickness was 2 μm. The through holes between wiring layers and the openings of the bonding pads were formed by using negative type OM 83 (trade name, manufactured by Tokyo Ohka Co., Ltd.) as a photoresist and using a mixed solution of hydrazine and ethylenediamine as an etchant.

PSG膜は螢光X線分析よシP2O5換算で5I02と
のモル比が12:88であった。咬た、その厚さは0.
7μmとした。
The PSG film had a molar ratio of 5I02 to 5I02 of 12:88 in terms of P2O5 as determined by fluorescent X-ray analysis. The thickness is 0.
It was set to 7 μm.

また、このようにして形成した配線導体層け、Niを約
Q、 6w t%、Siを約1.5wt%含むAt合金
からなるものである。
Further, the wiring conductor layer thus formed is made of an At alloy containing approximately Q, 6 wt % of Ni and approximately 1.5 wt % of Si.

以上のようにして形成した配線に金線によるワイヤボン
ディングを行ない、エポキシ樹脂を用いて樹脂封止した
のち、I’CTを行なった。そして配線抵抗値を評価し
、配線抵抗値の上昇が観測されはじめる最初の201時
間を評価した。評価は第17脅、第2層とも純AAで構
成した試料との比較で行なった。その結果、純Atで抵
抗変化が観測された201時間は、第11脅、第2層と
もわずか数時間であったのに対して、本実施例の試料は
、第1層で約30倍、第2層で100倍以上の長時間が
必要であり、副食性はきわめて良好であった。
Wire bonding was performed using gold wire on the wiring formed as described above, and after resin sealing using epoxy resin, I'CT was performed. Then, the wiring resistance value was evaluated, and the first 201 hours at which an increase in the wiring resistance value began to be observed was evaluated. Evaluations were made by comparison with samples made of pure AA for both the 17th layer and the 2nd layer. As a result, the 201 hours during which the resistance change was observed for pure At was only a few hours for both the 11th layer and the 2nd layer, whereas the sample of this example had a resistance change of about 30 times for the 1st layer. The second layer required a 100 times longer period of time, and was extremely good as a side dish.

実施例2 配線導体層を形成するAt合金中のNi量とSN量をか
えたこと以外は実施例1と同様にして第1図に示す構造
の半導体装1r1を作成した。ただし第1層および第2
層の配線2ξt1体中のNi及びSiの濃度はそれぞれ
0.01wt%、0.5wt%とした。
Example 2 A semiconductor device 1r1 having the structure shown in FIG. 1 was produced in the same manner as in Example 1 except that the Ni and SN contents in the At alloy forming the wiring conductor layer were changed. However, the first and second layers
The concentrations of Ni and Si in the wiring 2ξt1 layer were 0.01 wt% and 0.5 wt%, respectively.

抵抗変化が認められたP C’1’時間a1純Atのそ
れに対して、第1層配線で20倍、第2層配線で70倍
となった。実施例1にくらべ、やや知かいが、ht−N
iの二元系にくらべれはなおはるかに面・1食性が増し
ており、効果が認められる。
The resistance change was observed in the first layer wiring by 20 times and in the second layer wiring by 70 times compared to that of pure At. Compared to Example 1, ht-N is slightly more sophisticated.
Compared to the binary system of i, it is much more monophagous and effective.

実施例3 配線導体層を形成するAt合金中のN I−Jjjと3
i量をかえたこと以外は実施例1と同様にして第1図に
示す構造の半導体装置を作成した。ただし第1層および
第2層の配+Vj!導体中のNi及びSiの濃度は、そ
れぞれ2.5 w t%、4wt%とじた。
Example 3 N I-Jjj and 3 in At alloy forming wiring conductor layer
A semiconductor device having the structure shown in FIG. 1 was produced in the same manner as in Example 1 except that the amount of i was changed. However, the arrangement of the first and second layers +Vj! The concentrations of Ni and Si in the conductor were 2.5 wt% and 4 wt%, respectively.

抵抗変化のはじまる201時間は、純A7のそれに対し
て、第1層配線で20倍、第2層配線で80倍であった
。実施例1にくらべやや炉かめではあるが、十分耐食効
果が認められた。
The 201 hours required for the resistance change to begin was 20 times longer for the first layer wiring and 80 times longer for the second layer wiring than that for pure A7. Although it was a little harder than Example 1, a sufficient corrosion resistance effect was observed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例における半導体装置を示す概
略断面図である。 1・・・半導体ウエーノ・、2・・・PSG膜(第1パ
ツシベーシヨン膜)、3・・・第1層配線溝体、4・・
・配線層間絶縁膜、5・・・第2層配線溝体、6・・・
保護膜165
FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor wafer, 2... PSG film (first passivation film), 3... First layer wiring groove body, 4...
- Wiring interlayer insulating film, 5... Second layer wiring groove body, 6...
Protective film 165

Claims (1)

【特許請求の範囲】 1 、0.01〜2.5 W 1%のNi、 o、s 
〜4.owt%のSiおよび残余がAtからなる組成の
合金で構成された配線導体層を半導体基板上に有するこ
とを特徴とする半導体装置。 2、前記合金力0.01〜2.5 W 1%(7)Ni
、1.0〜2、Qwt%のBiおよび残余がA4からな
る組成を有することを特徴とする特許請求の範囲第1項
記載の半導体装置。 3、前記合金がo、i 〜towt%のNlX0.5〜
4、 Q W 1%のSiおよび残余がAtからなる組
成を有することを特徴とする特許請求の範囲第1項記載
の半導体装置。 4、前記合金75” 0.1〜i、 o w 1%のN
i、1.0〜2、 Q w 1%のSiおよび残余がA
tからなる組成を有することを特徴とする特許請求の範
囲第1項記載の半導体装置。 5、前記配線導体層の少なくとも一部が、高分子樹脂に
よシ被腐されていることを特徴とする特許請求の範囲第
1項乃至第4項のいずれかの項に記載の半導体装置。 6、前記配線導体層の少なくとも一部を被腐する高分子
樹脂が、ポリイミド樹脂およびポリイミド・イソインド
ロ・キナゾリンジオン樹脂からなる群よシ選択された少
なくとも1樹脂であることを特徴とする特許請求の範囲
第5項記載の半導体装置。 7、前記半導体基板が少なくとも1表面に絶縁膜を有す
るものであシ、前記配線導体層は少なくともその一部が
該絶縁膜上に存在することを特徴とする特許請求の範囲
第1項乃至第6項のいずれかの項に記載の半導体装置。 8、前記絶縁膜がリンを含むガラスからなることを特徴
とする特許請求の範囲第7項記載の半導体装置。 9、前記絶縁膜が高分子樹脂からなることを特徴とする
特許請求の範囲第7項記載の半導体装置。 10、前記絶縁膜を構成する高分子樹脂が、ポリイミド
樹脂およびポリイミド・イソインドロ・キナゾリンジオ
ン樹脂からなる群より選択された少なくとも1樹脂であ
ることを特徴とする特許請求の範囲第9項記載の半導体
装置。 11、前記配線導体層が少なくとも2層からなり、その
上部側の配線導体層はその下に位置する配線導体層の少
なくとも一部を被履する高分子樹脂層上に形成され、且
つ該」一部側の配線導体層の少なくとも一部が高分子樹
脂により被履されていることを特徴とする特許Nt”f
求の範囲第5項乃至第10項のいずれかの項に記載の半
導体装置。 12、樹脂封止されてなることを特徴とする特許請求の
範囲第1項乃至第11JI’Jのいずれかの項に記載の
半導体装置。
[Claims] 1, 0.01-2.5 W 1% Ni, o, s
~4. 1. A semiconductor device comprising, on a semiconductor substrate, a wiring conductor layer made of an alloy having a composition of owt% Si and the balance At. 2. The alloy strength 0.01-2.5 W 1% (7) Ni
, 1.0 to 2.0 Qwt% of Bi and the remainder is A4. 3. The alloy has o,i ~twt% of NlX0.5~
4. Q W The semiconductor device according to claim 1, having a composition of 1% Si and the remainder At. 4. Said alloy 75'' 0.1~i, o w 1% N
i, 1.0~2, Q w 1% Si and the remainder is A
The semiconductor device according to claim 1, characterized in that the semiconductor device has a composition consisting of t. 5. The semiconductor device according to any one of claims 1 to 4, wherein at least a portion of the wiring conductor layer is corroded by a polymer resin. 6. The polymer resin that corrodes at least a portion of the wiring conductor layer is at least one resin selected from the group consisting of polyimide resin and polyimide isoindolo quinazolinedione resin. The semiconductor device according to scope 5. 7. The semiconductor substrate has an insulating film on at least one surface, and at least a portion of the wiring conductor layer exists on the insulating film. 6. The semiconductor device according to any one of Item 6. 8. The semiconductor device according to claim 7, wherein the insulating film is made of glass containing phosphorus. 9. The semiconductor device according to claim 7, wherein the insulating film is made of a polymer resin. 10. The semiconductor according to claim 9, wherein the polymer resin constituting the insulating film is at least one resin selected from the group consisting of polyimide resin and polyimide isoindolo quinazolinedione resin. Device. 11. The wiring conductor layer is composed of at least two layers, and the upper wiring conductor layer is formed on a polymer resin layer covering at least a part of the wiring conductor layer located below, and Patent Nt”f characterized in that at least a part of the wiring conductor layer on the side is covered with a polymer resin
The semiconductor device according to any one of claims 5 to 10. 12. The semiconductor device according to any one of claims 1 to 11JI'J, characterized in that it is resin-sealed.
JP13193382A 1982-07-30 1982-07-30 Semiconductor device Pending JPS5923542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13193382A JPS5923542A (en) 1982-07-30 1982-07-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13193382A JPS5923542A (en) 1982-07-30 1982-07-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5923542A true JPS5923542A (en) 1984-02-07

Family

ID=15069603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13193382A Pending JPS5923542A (en) 1982-07-30 1982-07-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5923542A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0272631A (en) * 1988-09-08 1990-03-12 Fuji Xerox Co Ltd Wiring structure in electronic device and image sensor having this wiring structure
JPH0423836A (en) * 1990-05-18 1992-01-28 Sumitomo Bakelite Co Ltd Pattern-containing sheet
JPH0468030A (en) * 1990-07-10 1992-03-03 Sumitomo Bakelite Co Ltd Decorative sheet
CN102110599A (en) * 2010-11-01 2011-06-29 兰州大学 Production process of soluble polyimide

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0272631A (en) * 1988-09-08 1990-03-12 Fuji Xerox Co Ltd Wiring structure in electronic device and image sensor having this wiring structure
JPH0423836A (en) * 1990-05-18 1992-01-28 Sumitomo Bakelite Co Ltd Pattern-containing sheet
JPH0468030A (en) * 1990-07-10 1992-03-03 Sumitomo Bakelite Co Ltd Decorative sheet
CN102110599A (en) * 2010-11-01 2011-06-29 兰州大学 Production process of soluble polyimide

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