JPS5922440B2 - Time division multiplex control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time division multiplex control system in which a control unit controls a controlled unit via a common transmission line.

When transmitting control signals using a time-division multiplexing method using a common transmission line, if multiple signals are sent simultaneously or partially overlapping, they will result in erroneous signals or become undetectable.

In order to prevent this, conventional methods have been used to stop transmission of signals from other control parts to the same controlled part at the same time that a certain control part sends a signal to a certain controlled part, or to give priority to signals. A method has been proposed in which the signal being transmitted is interrupted and only the priority signal is transmitted.
However, all of these require a signal detection function for detecting different types of control signals on the transmission line and a signal temporary stop function, making their configurations quite complicated. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a time division multiplex control system that can preferentially transmit a desired control signal with a simple configuration.

FIG. 1 is a block diagram of an m:n multiplex control system to which the present invention can be applied.

In the figure, A1 to Am are control units, in particular A1 is a central control unit having a synchronization pulse generation source 1. Each control part A1
~Am is the transmitting/receiving section 2, the control command section 3, and the controlled section B
Display monitoring unit 4 that displays signals sent from 1 to Bn
It is composed of B1 to Bn are controlled parts controlled by the control parts A1 to Am, and are composed of a transmitter/receiver part 5, a signal discrimination part 6, and a load actuation part 7, and these control parts A1 to Am and the controlled part B1 ~Bn is common transmission line 8
Signal transmission is performed by the . FIG. 2 is a waveform diagram of the synchronization pulse that is constantly sent to the common transmission line 8 from the synchronization pulse generation source 1 of the central control unit A1, and the control system shown in FIG. It is managed separately. That is, in the time period between the channel pulse C1 after the frame pulse F and the next channel pulse C2, a control signal for the channel CH1 (controlled unit B1) is sent from any control unit Ai to the controlled unit B1, When the controlled part B1 operates, the channel pulse C(
n+1] and channel pulse C(n+2), a display signal (for example, a signal indicating that the signal has turned 0N) is transmitted from the controlled unit B1 to the common transmission line 8. A time period has been set so that it will be sent out. Time management is performed similarly for channels CH2 to CHn. Note that the control units A1 to Am
In order to know the channel positions corresponding to the controlled parts B1 to Bn, for example, it is sufficient to count the number of channel pulses, and to tell the difference between frame pulse F and channel pulse C, it is necessary to change the pulse width or change the frequency. This can be easily done by making the difference. Note that the control signal is
The control signals are sent from the control units A1 to Am only when a control command is issued, and the control signal transmission is stopped when the controlled units B1 to Bn operate.
On the other hand, display signals are always sent out from the controlled units B1 to Bn. FIG. 3 is a block diagram of the central control section A1 in FIG. 1. In the figure, 11 is a frame pulse generator;
12 is a clock generator controlled by frame pulse F, 13 is a channel pulse generator, 14 is a channel selector circuit, 15 is a channel CHl to CHnf)
0N/0FF setting circuit for setting 0N/0FF control, 1
6 is a modulation unit for frame pulse F, 17 is a modulation unit for channel pulse C, 18 is a modulation unit for 0N-0FF control signal,
19 is 0N, 0F sent from controlled parts B1 to Bn.
F is a demodulation unit for display signals such as abnormality, 20 is a decoder unit when the display signal is coded, 21 is 0N, 0FF
This is a display section that displays abnormalities and the like. A clock generator 12 is operated by the frame pulse generator 11, and channel pulses C1 to C (2n) are obtained from the channel pulse generator 13 by this clock, and frame pulses F and channel pulses C are generated. are the modulators 16 and 16, respectively.
, 17 and sent out to the transmission line 8, and also manages time allocation for the entire system. In the 0N/0FF control setting circuit 15, for example, the 0N/0FF control signal is
It is encoded into a base code, set to either 0N or 0FF by n command switches, and is modulated by the modulation section 18 via the channel selector circuit 14, and is transmitted over the transmission line in the time period between channel pulses C shown in FIG. Sent on 8th.

The display signals sent from the controlled units B1 to Bn are demodulated by the demodulation unit 19, and the 0N/0FF and abnormal code signals are decoded by the decoder unit 20 and displayed on the display unit 21. FIG. 4 is a block diagram of an arbitrary controlled section Bi in FIG.

In the figure, 22, 23, 24 are demodulators for the frame pulse F1 channel pulse C and 0N-0FF control signal, 25 is a channel selector circuit, 26 is a clock generator, 27 is a control 0N/0FF code generator,
28 is a comparison unit that compares the signal from the control signal demodulation unit 24 and the signal from the 0N/0FF code generation unit 27, 29 is a display signal code generation unit, 30 is a driver unit, 31 is a load contact, and 32 is a display This is a signal modulation section. A display signal code generating section 29 and an 0N-0FF code generating section 27 are managed by contacts linked to the load contact 31. The frame pulse F, channel pulse C and 0N/0FF control signals sent via the transmission line 8 are sent to the demodulator 22,
23 and 24, and the channel selector section 25 knows the channel position based on the demodulated frame pulse F and channel pulse C, and at the same time, a clock pulse generator 26 outputs a clock. This clock period is the same as that of the clock generator 12 in FIG. The comparison section 28 compares the signal whose own channel position is confirmed by the channel selector 25, the signal demodulated by the control signal demodulation section 24, and the 0N/0F synchronized with the clock.
The signal from the F control signal code generation section 27 is compared, the driver section 30 is operated according to the control signal, and the load contact 31 is
Open and close. The display signal code generating section 29, which has a contact linked to the load contact 31, outputs a display signal to indicate that the load contact 31 has operated onto the transmission line 8 via the modulation section 32 during its own display signal time period. send out. Note that in the control units A2 to Am that do not have the synchronization pulse generation source 1, the synchronization pulse generation source 1 may be replaced with a synchronization pulse (frame pulse F and channel pulse C) detection unit. Since it can be considered in the same way as the receiving section of the control section, the explanation is omitted here.In such an m:n multiplex control system, different types of control signals are simultaneously sent from multiple control sections to a specific controlled section. The case will be explained with reference to FIG.

FIG. 5a shows channel pulses Ci, C(1+1) for managing the control signal time period of an arbitrary controlled unit Bi. Here, for convenience of explanation, the channel pulse is assumed to be the demodulated waveform after reception. B, c, d are AM modulation waveforms, E, f, g
shows the FSK modulation waveform, and B and e are (101×
), the 0FF control signal waveform of the coat configuration, C, f is (×
011) 0Nfb1J control signal waveform with code configuration, D
, g is (
1011) is shown. In addition, FSK
is a two-frequency wave F, which is a shift of the space and mark signals.
It is modulated by f'1 and is called frequency shift keying. Also, in the above explanation, 1 is a mark signal, 0 is a space signal,
× indicates no signal. FIG. 6 is a detailed circuit diagram of the main part of the central control section shown in FIG. 3, and FIG. 7 is a time chart thereof. In Fig. 6, 33 is a 3-bit binary counter, 34 is a NAND circuit, 35 is an 0R circuit, 36 is an inverter, 31 is a NAND circuit, and 15a is a controlled section B1 to B.
This is an 0N-0FF control command switch for n.

The switch 15a has a left contact as an ON switch, and a right contact as an OFF switch. For convenience of explanation, FIG. 7 shows a time chart for the controlled units B1 (CHl) and B2 (CH2). A clock pulse CK is generated from the clock generator 12 after a certain period of time from the fall of the frame pulse F, and pulses A, b, and c are obtained as outputs of a 3-bit binary counter 33 which receives this clock pulse CK as an input. Here, the inverter output J of the pulse c is used as a channel pulse, and the output pulse c becomes a control signal time period to the controlled parts B1 to Bn. In addition, an output d'('0FF/0N composite code 1011 is created from the NAND circuit 37 from pulses a and b. Also, pulses A, bf) NAND
Output e'('0FF control signal gate, the output f of the 0R circuit 35 inputting pulses A and b is used to create the 0N control signal gate. For example, CHl (B1)
If you want to set it to 0N, turn the command switch 15a (7) CH
When the switch for 1 is turned to the left, an 0N control signal (x011) is sent to the transmission line 8 from the composite modulator 18 of the 0N gate f of the channel CH1 and the output d via the channel selector 14. Similarly, for sending the 0FF control signal (101×), set the command switch 15af) CHl contact to 0.
Just move it to the FF side.

Note that if the control signal transmission is automatically stopped upon return of the control operation display signal from the controlled section B1, it becomes possible to transmit any control signal from the other control sections A2 to An. FIG. 8 is a detailed circuit diagram of the main parts of the controlled section in FIG. 4,
FIG. 9 shows the time chart. In Figure 8,
38 is an AND circuit of the reception control signal and the 0FF gate; 3
9 is an AND circuit with the same 0N gate, 40 and 41 are decoders for 0FF and 0N control signals, respectively, and 0N-0F.
This is the part to be compared with the code of the F code generation section 27. In FIG. 9, a is the channel pulse Ci,C(1+1
j, b are clock generators 2 by channel pulses Ci.
The clock generated at 6, the composite code signal obtained by demodulating the simultaneously received signal of the c&'@0N and 0FF control signals by the demodulator 24, and d is the time period (TO to T4) for the control signal of the controlled unit Bi by the channel selector circuit 25. (Such a gate can be easily obtained using the same principle as shown in Fig. 7), e is also the gate for the 0N control signal. In this case, the 0FF control signal is connected to the received signal c and the 0FF gate. The signal of f (
101×》 is obtained, 40K is input to the decoder section, and 0N・
Upon comparison with the output of the 0FF code generating section 21, the output is transmitted to the driver section 30. On the other hand, as the 0N control signal, the received signal c and the output (1011) via the 0N gate Ef) AND circuit 39 are the same as the composite code c, so there is no coincidence, and the signal is sent from the decoder section 41 to the driver section 30. There is no output.If 0NfrJ0 control signal C×01
If only 1) is received, g is (0011) 0N
Since the code is input to the 1 decoder section 41, reception is 0N.
The signal will be transmitted to the driver section 30. FIG. 10 is an explanatory diagram of another embodiment of the invention.

That is, in the control section, a BOOFF gate generates a Cf)20FF control signal code (x011) from the common code of a (1011), and an Ef)0N control signal code (10x1) is generated by a Df)0N gate. Then, in the controlled section, the Ff)0FF gate extracts the C47)0FF control signal code (×011), and the Ef)0N signal (1
0x1》, when the common code of a (1011》) is received, the 0FF control signal code (
×011) will be received preferentially. In other words, when the common code (1011) is extracted by the Gf)0N gate, it becomes (1011), which is different from Ef)0N control signal (10×11. In this way, in this embodiment, Controlled part B1 to Bn'80N・
When 0FF control signals are received at the same time, the width of the gate for the 0FF control signal, which is a priority signal, is greater than the width of the 0FF control signal gate, which is a non-priority signal.
By making the width of the N control signal gate wider, the 0FF signal is preferentially received during simultaneous reception. As a result, when control commands are issued from multiple locations simultaneously,
It becomes possible to detect one of them preferentially. Further, the present invention can also be applied when using many control signals such as a priority control signal and an emergency control signal from the central control unit A1. Although the explanation has been made using a 4-bit model, it goes without saying that it can be applied regardless of the number of bits. As described above, according to the time division multiplex control system of the present invention, a desired control signal among different types of control signals can be transmitted preferentially with a simple configuration.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an m:n multiplex control system to which the present invention can be applied, Fig. 2 is a signal waveform diagram for explaining its operation, and Fig. 3 is a block diagram of the central control section in Fig. 1. , FIG. 4 is a block diagram of arbitrary controlled parts in FIG. 1, FIG. 5 is a signal waveform diagram for explaining their operation, FIG. 6 is a detailed circuit diagram of the main part of FIG. 7 is a time chart thereof, FIG. 8 is a detailed circuit diagram of the main part of FIG. 4, FIG. 9 is a time chart thereof, and FIG. 10 is an explanatory diagram of another embodiment of the present invention.

Claims (1)

[Claims] 1. A plurality of control stations time-manage and time-division multiplex control a plurality of controlled stations using a frame pulse followed by a plurality of channel pulses sequentially arranged and respectively corresponding to the plurality of controlled stations. In the time division multiplexing control system, the control center includes a first bit part comprising a common bit part and an independent bit part including at least one mark bit.
and a control signal generation circuit that generates a time-sequentially arranged composite coded signal obtained by synthesizing a second control code immediately after each of the plurality of channel pulses, and A plurality of setting switches are individually set, and a composite coded signal generated by the control signal generation circuit corresponding to the setting state of each of the plurality of setting switches is selected as one of the first and second control side gate pulses. On the other hand, by gating one of the first and second coded signals each consisting of the first and second control codes immediately after the channel pulse corresponding to each of the plurality of controlled points; and a control-side channel selector that is placed on the transmission line during a time-division allocation period corresponding to the controlled station, and the controlled station includes a control side channel selector that is placed on the transmission line during a bit allocation period of the first control code immediately after a channel pulse corresponding to the controlled station. The first controlled side gate pulse is generated only during the bit arrangement period of the second control code and the first controlled side gate pulse.
a controlled-side channel selector that generates a second controlled-side gate pulse during a bit arrangement period of at least one mark bit of the independent bit portion of the control code;
a first gate for passing a received signal from the transmission line in response to a controlled side gate pulse; and a first gate for passing a received signal from the transmission line in response to the second controlled side gate pulse. 2 gates and space bits equal to the number of bits of the independent bit part of the second control code in the first control code.
a third control code added to the control code of and a fourth control code added to the second control code with space bits equal to the number of bits of the independent bit portion of the first control code. the circuit, and drives the load to one state when the third control code and the signal code of the output of the first gate match, and the fourth control code and the signal of the output of the second gate; and a drive circuit that drives the load to the other state when the code matches the code.