JPS5922273B2 - Automatic conversion device for fare display on buses, etc. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides automatic conversion of fare display devices, mainly in one-man buses with deferred fare payment system, in order to automatically display fares electronically in accordance with the operating location of the bus, etc. This invention relates to an automatic conversion device for fare display devices on new buses, etc., in which a semiconductor memory is provided in the control logic circuit of the automatic conversion device.

Conventionally, the control signals for the fare display and numbered ticket issuer were simultaneously recorded on the magnetic tape of a tape recorder that recorded information broadcasts on buses, etc., and the control signals were sequentially sent as the tape ran. There was a system that automatically operated the fare display and numbered ticket issuer according to the operating position of the bus, etc. However, the above-mentioned fare display device is equipped with a display scroll with the fare written on it behind the fare display window corresponding to the ticket number, and the display scroll is sequentially rolled up by the operation of a drive motor. Therefore, the fare was displayed in the fare display window according to the operating location of the bus or the like. It goes without saying that the drive motor operates based on the control signal recorded on the magnetic tape of the tape recorder that recorded the guidance broadcast.

In this way, conventional fare display devices display the fare by mechanically winding the display scroll, which makes changing the fare display troublesome when revising bus fares, etc. and required a large amount of expense.

In other words, the display rolls must be replaced with new ones that list the revised fares, and replacing the display rolls on many buses all at once would naturally cost a lot of money and time. required.

The present invention eliminates the above-mentioned conventional drawbacks and provides an automatic fare display conversion device that greatly simplifies the work of changing fare displays when fares for buses, etc. are revised. Furthermore, the present invention provides an automatic conversion device for a fare display in which a semiconductor memory is provided in the control logic circuit, and a large number of memory items can be stored, and the memory can be easily rewritten. .

In other words, the automatic fare display change device for buses, etc. of the present invention has a recording magnetic tape for in-vehicle announcements having recording sections for a plurality of tracks. A start signal for fare change is recorded at the location corresponding to the fare change, and this start signal is reproduced by a reproducing head to sequentially read out the required data from the semiconductor memory of the control logic circuit, and the information is displayed on the electronic digital fare display of the bus, etc. This system is characterized by an electronic digital display of fares appropriate to the operating location. Hereinafter, preferred embodiments of the present invention will be described based on the accompanying drawings.

FIG. 1 is a block wiring diagram of the apparatus of the present invention. In the figure, 1 is a tape recorder having a magnetic tape 2 and a reproducing head 3. When the start switch 4 is closed, a power supply current is supplied and the tape recorder is operated. A reproducing head 3 reproduces the recorded signal on the tape 2.

The magnetic tape 2 has a recording section of a first track T, a second track T2, a third track T3, and a fourth track T4 in the tape width direction, as shown in FIG. The first track t1, the second track T2, and the fourth track T4 each have an in-car broadcast signal A for stop information and station name information for buses, etc., a stop signal B for the tape recorder 1, and a rearrangement signal, respectively, as in the past. A signal D for the ticket issuer is recorded, and a start signal C for reading data from a semiconductor memory to be described later and changing the fare display is recorded in the third track T3. Any signal wave that is located in the same location as the broadcast signal acquisition unit, that is recorded in relation to each location corresponding to the area boundary where the fare is changed, and that can be recorded and reproduced magnetically. It's fine, but generally from 400Hz to 400Hz.
A 300 Hz sine wave or rectangular wave with a length of about 0.3 to 0.5 seconds is preferable. Reference numeral 5 denotes a control amplifier, which amplifies each signal A, B, C, D reproduced by the reproduction head 3, and the control amplifier 5 supplies the amplified start signal C to the control logic circuit 6. It is connected to an electronic digital fare display 7 via a semiconductor memory 10b.

Further, as in the conventional case, the control amplifier 5 derives the amplified in-vehicle broadcast signal A to the in-vehicle speaker 8, and also derives the amplified stop signal B to the control device (not shown) of the tape recorder 2. The amplified signal D for the numbered ticket issuer is connected to a control device (not shown) for the numbered ticket issuer.

The electronic digital fare display 7 has the following information in each display section corresponding to the numbered ticket number 7a written on the display surface.
Each of them is provided with an electric display section 7b consisting of a combination of an electric light tube, a liquid crystal type display, a light emitting diode, etc. each having the shape of a number from O to 9, for example. Note that the configuration of the control logic circuit 6 will be explained in detail later. Next, the operation will be explained.

When the start switch 4 is closed, the tape recorder 1 is activated, and its playback head 3 receives the in-car broadcast signal A, stop signal B, start signal C, and signal D for the numbered ticket issuer recorded on the magnetic tape 2. regenerate and control amplifier 5
amplifies the reproduced signals A, B, C, and D and outputs them to each connecting device.

Therefore, the in-car speaker 8 automatically broadcasts stop guidance and station name information based on the in-car broadcast signal A, and the numbered ticket issuer issues a predetermined numbered ticket based on the numbered ticket issuing signal D. Based on the start signal C, the digital fare display 7 automatically operates to issue the fare display items, and the digital fare display 7 displays the information on the surface based on the data read from a predetermined address of the semiconductor memory 10b in which fare display items are stored. A predetermined fare is automatically digitally displayed in each section corresponding to the written numbered ticket number 7a.

Furthermore, the tape recorder 2 automatically stops its operation based on the stop signal B.

The present invention is characterized in that the digital fare display 7 automatically digitally displays the fare according to the operating position of the bus, etc., based on the data read from the semiconductor memory 10b based on the start signal C. be.

Next, a specific example of the control logic circuit 6 will be explained.

FIG. 3 shows an example of the control logic circuit 6, and to explain the outline of the operation of the control logic circuit 6 in the figure, the start signal C is regenerated and amplified by the regeneration head 3 and control amplifier 5 similar to those described above. is converted by the signal shaping circuit 9 into a pulse signal with a very short time width that should be adapted to the data read time, and then introduced into the semiconductor memory control circuit 10a.

By the control function of the semiconductor memory control circuit 10a, the semiconductor memory 10 is controlled every time the start signal C is input.
Predetermined fare data is sequentially read from b, and this fare data is sent to each holding device 12 via the boundary final address detector 13a, and is also sent to each gate circuit 11 controlled by the carry detector 13b. The data signals are discriminated and sequentially taken into a predetermined holding device 12, and the holding device 12 holds the taken data and displays it on the electronic display section 7.
While maintaining the digital display of fare 7b, it is cleared by the signal output from the clear detector 14 in response to the next start signal, thereby wiping out the digital display contents of the electronic display section 7b. Therefore, the electronic display section 7b of each display section of the digital fare display 7 displays the fare corresponding to each ticket number 7a in electronic digital form according to the operating position of the bus or the like. In addition, 15 in the figure is a diode, and 16
is a high-voltage line for lighting the electric display section 7b of each section in the digital fare display 7, and +B is a power supply. Next, the control logic circuit 6 will be explained in more detail with reference to FIGS. 4 to 7.

First, FIG. 4 is an explanatory diagram showing the format of data in the semiconductor memory 10b and the relationship when that data is displayed as a fare.
D7 to DO of the ROM) are output data for one address, and the data is handled in units of 8 bits (in units of 1 byte) per address, and the data in "DE" stored in the first address is This is a header code for detecting the head position when selecting a bus route.Fare data is stored in the two addresses after the DE code, and is necessary to represent a single number from O to 9. The data is 4
Since it is expressed in bits, the upper 4 bits of the first 8 bits are the 1000th place of the fare, and the lower 4 bits are the 100th place.
The upper 4 bits of the next 8-bit byte are assigned to the 10th place, and the lower 4 bits are assigned to the 1st place. Also, "F" is a blanking (no display) code, so the 6FF80 shown in the diagram
゛ is data for a fare of 80 yen. Furthermore, 1DA1 code indicates the end of the fare data for that area, and when this ``DA'' code is read out, the reading operation is stopped and continues until the 1DA'' code is read out with the input of the next start signal.
Fares data composed of bytes (two addresses) are sequentially read out. For example, the data for the nth section is
If you divide it into 2 bytes, 6F200-゛Fl8
O-6F150゛1F120""FlOO- ゛FF9
O゛1FF80- ``DA゛, so 200, 18
0, 1501120, 100, 90, 80 are displayed.

Incidentally, the selection of the operating route is detected by reading and reading the 1DE code by skipping the number of designated numbers by designating the route number using a digital switch, for example. Next, the semiconductor memory control circuit 10a will be explained with reference to FIG. It is ANDed with the clock pulse Φ1 of the generator 0SC and inputted to the set terminal S of the first flip-flop FF1, thereby setting the flip-flop FF1.

The clock generator 0SC generates two-phase clock pulses Φ having a phase difference of 180° as shown in FIG. 7B and c.
1, Φ2. When the first flip-flop FF1 is set as described above, the clock pulse Φ1 is applied to the address counter AC consisting of an up-down counter via the second AND circuit A2.
The address data is incremented by 1 and outputted to the output terminals AO to Al2, and the addresses of the semiconductor memory 10b are sequentially designated. On the other hand, the clock pulse Φ2 delayed by 180 with respect to the clock pulse Φ1 is inverted by the first inverter 11 via the third AND circuit A3 to become the clock pulse Φ shown in FIG. Any one of the terminals YO to Y3 becomes low level, and the four P-ROMs forming the semiconductor memory 10b
One of the chip select terminals CS of γ1 to γ4 becomes active, and P-ROMs γ1 to γ4 are selected. or,
Since the inverted clock pulse Φ is applied to the output enable terminal 0E of the P-ROM γ1-γ4, the data at the designated address of the selected P-ROM γ1-γ4 is output to its output terminal D7-D7. The 8-bit fare data is input to both detectors 13a and 13b and fed back to the second decoder DE2, which detects the 6DA' code of the output data and detects the 1DA' code. When detected, the output becomes low level.

Until the 6DA code is detected, the clock pulse Φ
1, the address data of the address counter AC is loaded one by one, and the clock pulse Φ2 loads the address data of the address counter AC one by one.
Data of γ1 to γ4 is output.

Then, the 6DA'' code is detected and the second decoder DE2
When the output of the second inverter 1 becomes low level, this
2, the first flip-flop FFl is applied to the reset terminal R via the fourth AND circuit A4 and the second OR circuit 0R2, and the first flip-flop FFl is reset and its output Q becomes low level. 2. 3rd
AND circuits A2 and A3 both open their gates to block clock pulses Φ1 and Φ2, and the operation is interrupted. In such a case,
The second flip-flop FF2 is in the set state unless the manual return button HB is turned on, and its inverted output Q is at a high level. Incidentally, IR is an initial reset circuit, which generates a pulse signal for initializing when power is applied to the device, and resets the first and second flip-flops FF1 and FF2 and the address counter AC. Further, HF is a manual advance button, and when turned on, the same operation as that of generating a start signal is performed. Further, CO is a counter that operates together with the third OR circuit 0R3 and the second flip-flop FF2 when the manual return button HB is on, and returns the address by setting the address counter AC in the down mode until the 6DA code is detected. After that, the fare data for one section is read out. Next, in FIG. 6, the boundary final address detector 13a is
The third decoder DE3 is composed of a third decoder DE3 for detecting the A゛ code and a tri-state buffer TSB.
operates in the same manner as the second decoder DE2 described above, and the outputs DO to D7 of the semiconductor memory 10b become low level when the code is 6DA'', and are inverted by the third inverter 13.
The tri-state buffer TSB is connected in parallel or in cascade depending on the load since more loads will be connected later, and when the "DA" code is detected by the third decoder DE3, a high level signal is input to the DS terminal DS. This is to disable the output and reduce unnecessary current consumption.
The carry detector 13b is composed of an n-ary counter NC and a fourth inverter 14, and since the output data of the semiconductor memory 10b is sequentially output one byte at a time, the carry detector 13b is composed of an n-ary counter NC and a fourth inverter 14. Generates a movement signal.

That is, each time the address changes by one, the semiconductor memory control circuit 10a outputs the clock pulse Φ2.
Every time this clock pulse Φ2 is input to the clock terminal CK of the n-ary counter NC, it is sequentially outputted from each output terminal 00 to 0n and sequentially input to each gate circuit 11 as shown in FIG. 3 is set by the output of decoder DE3. The holding device 12 is each composed of a 4-circuit flip-flop 12a and a BCD code decimal decoder driver 12b. It is captured by a latch pulse as shown in FIG.
It is disconnected when a signal is input to the out-disable terminal 0D.

The BCD code decimal decoder driver 12b is a driver circuit that lights up the segments of the electronic display sections 7b00 to 7b9, and the BCD code decimal decoder driver 12b is a driver circuit that lights up the segments of the electronic display sections 7b00 to 7b9.
It converts the CD code into a decimal code of 0 to 9 and lights up the electronic display section 7b. The clear detector 14 is configured as an OR gate by three gate circuits 14a, 14b, and 14c, and when the clock pulse Φ2 is output, or when the clock pulse Φ2 is output from the output terminals 01 to 0n of the carry detector 13b, in other words, Then semiconductor memory 10b
Clear detector 1 while data is read out sequentially from
A high level signal is input from 4 to each out-disable terminal 0D of the holding device 12 to turn off the electric display section 7b, thereby preventing unnecessary lighting or flickering.

When the 6DA'' code is read out from the semiconductor memory 10b, a high level signal is output from the third inverter 13 of the boundary final address detector 13a as shown in FIG. counter NC
is reset and no longer input to the clear detector 14, and as shown in FIG.
D is no longer input, and each electric light display section 7b is lit up. Each gate circuit 11 is composed of an inverter circuit 11a and an AND circuit 11b, and receives the digit signal of the n-ary counter NC of the carry detector 13b and the clock pulse Φ.
2 and the fare data read out sequentially are taken into a predetermined four-circuit flip-flop 12a of the holding device 12.

At this time, if the data is taken in at the rising edge of the clock pulse Φ2, there is a risk that the timing with the output of the n-ary counter NC cannot be obtained, so the clock pulse Φ2 is inverted by the inverter 11a and the data is triggered at the falling edge of the clock pulse Φ2. Thus, the clock pulse Φ2 is delayed by a time corresponding to the pulse width of the clock pulse Φ2. Since the present invention has the configuration and operation described above, it produces the following effects.

That is, the start signal is recorded on one track of the magnetic tape, and the command signal is used to read out the semiconductor memory, so that the conventional magnetic tape can be used effectively, and the fare display section Since the fare is digitally displayed based on the start signal recorded on the magnetic tape that advances the address of the semiconductor memory that stores the fare display items, when the fares of many buses etc. are revised, the memory of the semiconductor memory Fares can be revised extremely easily and quickly by simply changing the details. This effect is remarkable even when compared with the automatic fare display conversion device of Japanese Patent Publication No. 5340776, which was filed and registered by the same applicant as the present application. In order to convert it into a signal and record it on one track of the magnetic tape, it is first necessary to create numeric string data, and for this purpose, key operations are performed on the input device based on the original fare list to enter one area. Create the necessary number string data for each number string, convert it into a serial data type signal to be recorded on magnetic tape, record this on a master tape of number string data, and then broadcast in the car from the master tape. This is an extremely complicated procedure in which the content of the in-car announcements is recorded on a tape at a designated location, and even when there is a partial revision of fares, the content of the numbers is recorded on the tape.
Frequently, the data content of the fare becomes too long to be recorded at the same location. In such a case, all recordings on the in-car broadcast tape must be re-recorded using the above procedure. In contrast, with the present invention, the in-car announcement tape is not involved at all when fare revisions are made, and only the data in the semiconductor memory needs to be changed. All you have to do is write the appropriate data, and it can be done in a much shorter time than changing magnetic tape. Furthermore, since the fare information recorded on a magnetic tape cannot be confirmed by playing back the recorded state as audio, a separate fare display device or equivalent monitor device is required; however, in the present invention, the P- R
Since the OM writer is equipped with a verification function for checking data, it has the great advantage of being able to accurately check the revision status in a short time. In particular, by making the semiconductor memory in the form of a power set and making it detachable from the control logic circuit, it is possible to quickly respond to freight rate revisions.

Furthermore, since the fare is displayed electronically digitally, the fare can be clearly displayed.

Furthermore, since the fare display is controlled by an electronic circuit,
This has the advantage of being able to provide an automatic changeover device for fare display devices on buses, etc., which is free from the possibility of displaying fares incorrectly due to vibrations, etc., and has excellent operational durability. In addition, a large number of memory items can be stored in semiconductor memory, the memory can be easily rewritten, it can be used permanently even if the power supply is cut off, and it can be recorded on a tape recorder. An additional related main patent application, which has various effects such as being able to display the activation signal of the fare display in a digital manner extremely easily and without malfunction, is Japanese Patent No. 958465 (Japanese Patent Publication No. 53-407).
No. 76), and as is clear from the claims, the invention related to the main patent application is ``a recording magnetic tape for in-vehicle broadcasting having a plurality of recording sections for in-vehicle broadcasting on one track. In order to correspond to the content, a high frequency signal for digital fare display is recorded, and after the high frequency signal for digital fare display is reproduced by a reproducing head, it is sent to the electronic digital fare display via a control amplifier and a control logic circuit. An automatic conversion device for a fare display on a bus, etc., characterized in that the electronic digital fare display displays a fare corresponding to the operating location of the bus, etc., in an electronic digital manner.

”. The present invention makes the main part of the above structure an essential part of the structure by disposing a semiconductor memory in the control logic circuit,
When the fares of a large number of buses, etc. are revised, the displayed fares can be revised very simply and in a short time by simply changing the contents stored in the semiconductor memory.

Therefore, the purpose of the present invention is the same as that of the invention related to the main patent application, which is to display the fare display electronically and digitally.
It achieves that purpose.

[Brief explanation of the drawing]

FIG. 1 is a block wiring diagram of an automatic conversion device according to the present invention;
FIG. 2 is an explanatory diagram of the recording section of the magnetic tape used in the automatic conversion device according to the present invention, and FIG. 3 is a specific example of a control logic circuit included in the automatic conversion device according to the present invention. Figure 4 is an explanatory diagram showing the relationship between semiconductor memory data and its display, Figure 5 is a wiring diagram of the semiconductor memory control circuit and semiconductor memory, and Figure 6 is a diagram of the control logic circuit. Some of the wiring diagrams and FIG. 7 are timing charts. 1...Tape recorder, 2...Magnetic tape, 3...Playback head, 4...Start switch, 5...Control amplifier , 6...
...Control logic circuit, 7...Digital fare display, C...Start signal, 10a...
- Semiconductor memory control circuit, 10b...Semiconductor memory.

Claims (1)

[Claims] 1. On one track of a recording magnetic tape for in-car announcements that has multiple recording sections, a fare change mark is placed at each location corresponding to the area where the fare is to be changed in accordance with the contents of the in-car announcements recorded on the tape. a semiconductor memory control circuit which records a start signal and is driven by the start signal reproduced by a reproducing head; and a semiconductor memory control circuit in which fare data is stored in advance as a digital signal according to a certain method and is controlled by the semiconductor memory control circuit to start the start signal. A semiconductor memory from which data at a predetermined address is sequentially read out each time a signal is input, and control for switching the display of a digital fare display according to the operating position of the bus or the like based on the data read out from the semiconductor memory. An automatic conversion device for a fare display on a bus, etc., characterized in that it is provided with a logic circuit for the purpose of use.