JPS5922155A - Exclusive controlling method of multiprocessor system - Google Patents

Abstract

PURPOSE:To realize application software which is simple and does not spoil the responsibility of a program by performing exclusive control over a common resource in a main memory when a processor executes the program. CONSTITUTION:The contents of the main memory 1 are referenced from main frames 32a and 32b through a memory bus 2. An exclusive state memory 4 is stored with the exclusive state of the memory 1 and the address of the memory 1 placed in an exclusive state and the number of a processor in an exclusive state are written therein. Program counters 31a and 31b are registers which indicate the current execution address of the program. Control registers 33a and 33b are registers which control the processor main frames 32a and 32b respectively and hold their states. Namely, STOP/RUN states, exclusive queue states, and interruption inhibition states of the processors are stored. For this purpose, the contents of the registers 33a and 33b are rewritten to inhibit the corresponding processors from being interrupted by other programs.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an exclusive control method when resources on a main memory in a multiprocessor type electronic computer are shared by a plurality of processors.

[Technical background of the invention]

In order to improve the usage efficiency of electronic computers, multi-programming methods have been adopted in recent electronic computers.

Multiprogramming means processing several bales σ with one processing device.
The program is time-divided so that these programs appear to run at the same time. In other words, it has the ability to perform multiple tasks at the same time.

Therefore, when multiple programs access the same resource, it is necessary to exclude resources between the programs. Here, exclusive means to prohibit other programs from accessing the same resource.
The circumstances that require resource exclusion between multiple programs are as follows. For example, assume that program A and program B share resource X and are executing multi-processing Y:. In this case, when exclusion is established between both programs, execution of program A and program B and access to shared resource X are performed independently in a time-sharing manner. As a result, you can write all the expected output for any program. However, when there is no exclusion between the two programs, the situation becomes completely different. This is because program A has access to shared resource X.

This is because program B accesses shared resource X separately under different conditions, resulting in logical inconsistency. For example, program A shares ■resource
While accessing this shared resource, program B accesses this shared resource and changes the state of shared resource.
Assume that program A continues to access the shared resource X times after that. Then, program A accesses shared resource X'Y without knowing that the state of shared resource X has been changed by program B.

In this way, if exclusion is not taken.

The state of the shared WIJ source ], resulting in an inconsistency in the logic. That is,
To the program 〇 Conversion for common child resource X” Fa (
xl - Fb conversion for program B's shared resources
Assuming (x), when exclusion is established between program A and program B, the state of common NIJ source X is "
a(Fb(x)) or Fb(Fa (phantom), and Fa
(Fb(x))=Fb(Fa(X)). However, when exclusion is not established between program A and program B, the state of resource X is either Fa(x) or Fb(x
) or all (unexpected results),
At least you won't get the expected output.

Typically, such exclusion is required for main memory, peripheral devices, transmission devices, etc. that are shared between mutually independent programs. On the other hand, exclusive control is generally achieved by the following method.

The first method is to centralize the execution management of programs and prevent conflicts between programs when accessing shared resources. Second, an arrangement is made between competing programs to issue a predetermined exclusive control macro instruction before performing all processes that require exclusive control f11.
This is a method of checking the exclusive status of shared resources in advance. The third thing is.

This is a method to prevent the processing of one program from being interrupted while the other program is running.

Generally, the scope of the first method is limited to one device, such as a peripheral device, and is usually serviced by an operating system. Therefore, the methods used in application software are usually the second and third methods mentioned above. T1
or the time T2 required to execute the process itself that requires exclusion, which is shorter. That is, in the case of T1>T2, the third method is preferable in terms of program response and is often simpler. On the other hand, if T□<T2.

It is better to use the second method above.

[Problems with background technology]

However, in multiprocessor electronic computers,
For such common [+J sources, it is necessary to ensure exclusion between each processor.

In this case, the third method cannot be used. because,
Even if requests for new interrupt signals to the electronic meter are completely stopped, programs are already running in each processor, and these programs cannot be mutually exclusive. Also, it is not preferable to use the second method. This is because, if the second method is used, it is necessary to issue an exclusive control macro command to everything that requires an exclusive control method and to analyze it. This is not only extremely complicated to process, but also takes an enormous amount of time to obtain exclusion, which is not desirable in terms of computer usage efficiency.

By the way, in multiprocessor electronic computers.

The easiest way to allocate tasks is to make each processor's processing completely independent. However, if this is achieved using conventional methods, the usage of the multiprocessor is extremely limited and its capabilities cannot be fully utilized.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned shortcomings of the prior art, and provides an exclusive control method χ that is simple and does not impair program responsiveness for the use of application software in multiprocessor electronic computers. It is completely white.

[Summary of the invention]

In order to achieve the above objective YX, the present invention checks whether the specified address on the main memory to be loaded into the content request processor is in the exclusive state, and if it is not in the exclusive state, the content is (exclusive read command) to load and put it in exclusive state.

Check whether the specified address in the main memory where you want to store the processor's contents is in an exclusive state. If it is not in an exclusive state, store the processor's contents and clear the exclusive state (release storage command). ), or by placing a specified address in an exclusive state (exclusion instruction) or canceling the exclusive state (release instruction), and checking the exclusive state of main memory at the stage when each processor executes a program, Exclusive access to shared resources 1IIJ ii
+4'j nl/other control methods are provided.

[Examples of inventions]

An embodiment of the present invention will be described with reference to FIGS. 1 to 3. First, with reference to FIG. 1, the configuration of the apparatus used in the exclusive control method of this invention will be explained. Memory in main memory 1
Four exclusive state memories are connected to the arithmetic and control units 3a and 3b through each switch. The arithmetic and control units 3a and 3b are
Program counter 31a.

31b, processor bodies 32a, 32b, and control registers 33a, 33b. The main memory 1 can be referenced from either processor body 32a or 32b via the memory path 2. The exclusive state memory 4 is the exclusive state memory of the main memory 1, and this is done by reading the address of the main memory 1 which is in the exclusive state and the number of the processor which is in the exclusive state. Note that the exclusive state memory 4 may be connected to a normal memory path as shown in FIG. 1, but a cache memory is preferable for faster speed. Program counter 31a.

Reference numeral 31b denotes a register indicating the execution location of the program at that time, which is included in each processor body 32a.

32b. Processor main body 32a.

32b consists of a microprogram and its control section. The control registers 33a and 33b are registers that control the respective processor bodies 32a and 32b and hold their states. For example, as shown in FIG. 2, they control the 5TOP/RUN state of the processor, the exclusive wait state of the processor, and the It should consist of an area for remembering the interrupt-prohibited state.

Therefore, by rewriting the contents of the control registers 33a and 33b, it is possible to disable interrupts to other programs.

Next, an exclusive read instruction (LX) and a release store instruction (LX) prepared for use by application software are provided.
STX), release command (REX), and exclusive command (Ex)
and 7 will be explained with reference to FIG.

p43 F Figure (a) is a flowchart for explaining the exclusive read instruction (LX).
C) Take out the instruction according to 31a and 31b (block 101), calculate the operand part and determine the address to load (block 102). Then, it checks whether the address in main memory 1 to be loaded is in an exclusive state by referring to the exclusive state memory 4, and if it is in an exclusive state in another processor, repeats the above operation and If it is not in an exclusive state with Zorocessor, then proceed to step 103 (block 103). If the address to be loaded is not in the exclusive state, the state of the processor is stored in the exclusive state memory 4 (block 1o4), and interrupts to other programs are prohibited by rewriting the entire contents of the control registers 33a and 33b of the own processor. state M (block 105). Then, by writing the address and processor number in the exclusive state memory 4, a predetermined address on the main memory 1 is placed in an exclusive state (block 106), and after loading the contents of the specified address on the main memory 1 (block 107), Program color/
The PCs 31a and 31b are updated and proceed to the next step (block 108).

FIG. 3(b) is a flowchart for explaining the release/store instruction (STX).
C) Block 201) fetches the instruction χ according to 31a t 31b, calculates the operand part and determines the address 7 to be stored (block 202). and.

Check whether an address in main memory 1 to be stored is in an exclusive state by another processor by referring to the exclusive state memory 4, and if it is in an exclusive state by another processor, perform the above operation. Repeatedly, if no other processor is in the exclusive state, proceed to the next step (block 203). If the address to be stored is not in an exclusive state by another processor (and is in an exclusive state in its own processor), the specified address and its own processor number are deleted from the exclusive state memory 4, and (Block 204).Then, after restoring the state of the processor to the state stored in the exclusive state memory 4 (Block 205), the data is stored at the specified address of the main memory I71 (Block 206), and the program counter is (PC) 31a and 31bχ are updated and the process proceeds to the next step (block 207).

FIG. 3(C) is a flowchart for explaining the release command (RE, 0). First, the program counter (PC) 31
Block 301 for fetching instruction 7 according to a, 31b
) and the operand part to determine the address (block 302). When the address is in the exclusive state, the address is deleted from the exclusive state memory 4 to release the exclusive request (block 303), and the program counter (PC)
31a, 31b Y update and proceed to the next step (block 304).

FIG. 3(d) is a detailed flowchart explaining the exclusive instruction (EX). First, the program counter (PC) 31
Block 40 for fetching instruction 7 according to a, 31b
1), Operand part? Address 7 is calculated (block 402). Then, the address xt! is stored in the exclusive state memory 4! block 403 )
, program counter (PC) 31a.

31b Update and proceed to next step (block 40)
4).

Meanwhile, the two arithmetic and control units jif 3a and 3b run two program counters h and l, respectively, and X on the main memory l.
The exclusive control method of the present invention will be explained by taking as an example the case where the area is accessed. It is assumed that programs A and B are configured as shown in the following table.

Program A Program B Here, it is assumed that there is no exclusive access to main memory 1 in the initial state.

1. When program A running on processor body 32a issues an LX command, the contents of area X of main memory 1 become R.
The number of the processor main body 32a and the address of the area X are written into the exclusive state memory 4, and the area X of the main memory 1 is placed in the exclusive state. Further, the contents of the control register 33a are changed in order to disable interrupts to other programs executed by the processor main body 32a. As a result, subsequent interrupts to the processor are placed in a waiting state.

Next, when program B being executed in the processor body 32b issues an LX command to area X, the exclusive state memory 4 is checked to see if area X is in the exclusive state. At this time, since the area X is in an exclusive state by the processor main body 32a, the state χ of the processor main body 32b
At the time of exclusion, the program counter 31b is not updated until the exclusion of area X is released, and the same instruction continues to be repeated. In this state, the processor main body 32b
If there is an interrupt by a program (different from programs A and B) that accesses an area other than area X, the processor body 32b will perform a service χ for that program. After A finishes the MPY (multiply) instruction, the STX instruction is issued, the exclusive information about area X is deleted from the exclusive state memory 4, and the interrupt inhibited state of the processor main body 32a is released. Then.

In the processor body 32b, at σ, when the LX instruction by program B is repeatedly executed, after the exclusive state of area X is released, the contents of area will be done.

In this manner, the present invention eliminates the problem of different programs running on separate processors accessing a shared resource under different conditions.

Note that the contents written in the exclusive state memory 4 are the same as those in the main memory 1.
It may be in a mapping format for each unit, or it may be in a format in which address ranges 171I are registered. Alternatively, the various operations of each processor may be converted into x-codes and registered. The exclusive state memory 4 may be used as part of the main memory 1 or may be made independent.

In addition to the above-mentioned LX, STX, REX, and EX, the following instructions may be used by the application software. In other words, instructions for exclusive control of all areas in the main memory 1, and processor operations other than accessing the main memory 1 by encoding various operations of each processor and registering the codes in the exclusive state memory 4. This is an instruction to exclude between each processor.

〔Effect of the invention〕

Thus, according to the present invention, when a plurality of programs executed independently of each other on separate processors access a shared resource, the LX described above can be used.

Since each program can use the STX, EX, and REX instructions independently, these programs will not access shared resources under different conditions, and when accessing shared resources, each program will Since the program independently checks whether the corresponding address of the shared resource is in the exclusive state or not and executes the command, exclusive control can be realized easily and without compromising the responsiveness of the program.

As a result, according to the present invention, the computational processing load on the software is small, and therefore the responsiveness of the program is less likely to be affected by how the software is used. Also,
Since the resources to be excluded are limited and identifiable, processes other than those related to those resources are not affected at all. Furthermore, there is no difference in appearance from the existing exclusive system (goods) in a single ZOP processor, and it is extremely easy to modify existing software.

[Brief explanation of drawings]

FIG. 1 is a flowchart for explaining the instructions used in the device control method used in the exclusive control method of the present invention. 2...Memory path, 3a, 3b... Arithmetic control unit. 370- Hanging diagram 3 (cL) (b) (c)
(d) 371-

Claims (1)

[Scope of Claims] (1) A main memory, a plurality of processors connected to the main memory, a program counter indicating the execution address of a program being executed by the processor, and which address of the main memory is exclusive to which processor; Are you in a state? An exclusive control method for a multi-processor system comprising: an exclusive state memory for storing an exclusive state; and a control register for storing whether the processor is in an interrupt-disabled state for other processors. 1111 If the specified address in the main memory that the program running on the - processor attempts to load is in an exclusive state by another processor due to an exclusive read instruction, the load instruction will not be executed until it is released. Execution is interrupted, and when this specified address is placed in an exclusive state by the processor of D, the content of this specified address is loaded into this processor, and this specified address is placed in an exclusive state, and this processor is placed in an interrupt-disabled state. The program counter for the Nishikatsuko processor is updated and the program proceeds to the step where the execution of the program is completely interrupted, and the specified address in the main memory to which the program running on the - processor attempts to store is set to another address by the release store instruction. When the processor is in an exclusive state, execution of the store instruction is suspended until the exclusive state is released.
If this specified address is not in an exclusive state by another processor, the contents of this - processor are stored in this specified address, the exclusive state of this specified address is removed, and the program for this - processor is stored. updating a counter and proceeding the program execution to the next step; using an exclusive instruction, the specified address of the main memory is placed in an exclusive state; using a release instruction, the specified address of the main memory is released from the exclusive state; and each of the processors 1. A method for exclusive control of a multi-processor system, characterized in that a program executed in the W') exclusively controls a common source on the main memory.