JPS59218733A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59218733A
JPS59218733A JP58092837A JP9283783A JPS59218733A JP S59218733 A JPS59218733 A JP S59218733A JP 58092837 A JP58092837 A JP 58092837A JP 9283783 A JP9283783 A JP 9283783A JP S59218733 A JPS59218733 A JP S59218733A
Authority
JP
Japan
Prior art keywords
region
semiconductor
semiinsulative
substrate
semiconductor film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58092837A
Other languages
Japanese (ja)
Inventor
Yasuo Shibata
柴田　康雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58092837A priority Critical patent/JPS59218733A/en
Publication of JPS59218733A publication Critical patent/JPS59218733A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To contrive the increasing of yield voltage when a reverse bias is impressed by a method wherein a semiconductor region having one conductive type is formed on the surface of a semiconductor region having other conductive type and a semiinsulating compound semiconductor film is formed on the P-N junction in contact to these regions. CONSTITUTION:A P type region 2 has been formed by diffusion in an N type semiconductor substrate 1 and a semiinsulative semiconductor film 6 doped with oxygen and made of a semiinsulative crystalline gallium or arsenic, etc., has been formed on both the surfaces of the substrate 1 and the region 2 by chemical vapor-phase growth method in such a way as to directly cover the P-N junction, which is formed by the substrate 1 and the region 2. An ohmic current can be run to the interface between this semiinsulative semiconductor film 6 and the semiconductor substrate 1 or the P type region 2 through numerous trapping levels, which are generated by the lattice mismatching due to the disagreement of lattice constant or dangling bonds that exist in the crystal grains. Accordingly, the electric potential distribution in the semiinsulative semiconductor film 6 and that in the surface of the semiconductor substrate 1 at the time when a reverse bias is impressed coincide mutually, thereby enabling to obtain a high yield voltage.

Description

【発明の詳細な説明】 本発明はｐ−ｎ験合部を具えるプレーナ型半導体装置の
逆バイアス時降参電圧全高める構造ＶＣ関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure VC for increasing the total breakdown voltage during reverse bias of a planar semiconductor device including a p-n junction.

従来、プレーナ型半導体装置の逆バイアス時降伏電圧を
高めるため九県１図に示すような構造がために１表＠Ｕ
Ｙｃ絶縁膜３全形成し、その絶縁膜３上ｃ、Ｐ型領域２
と半導体基板ｌとにオーミック啜触するように高抵抗膜
４全形収している。−万Ｐ型領域２からの電極導出はＰ
型領域２に吸飲する配線層５で行っている。Conventionally, in order to increase the breakdown voltage during reverse bias of a planar semiconductor device, a structure as shown in Figure 1 of Kyushu was created.
The entire Yc insulating film 3 is formed, and the P-type region 2 is formed on the insulating film 3.
The entire high-resistance film 4 is housed in ohmic contact with the semiconductor substrate 1 and the semiconductor substrate 1. - Electrode lead from P-type region 2 is P
This is done with a wiring layer 5 that absorbs into the mold region 2.

かかるプレーナ半導体装置によれば、′＃−導俸導板基
板１型領域２との限合？逆バイアスした時の電位勾配は
、この高抵抗膜４により、高抵抗膜４下で均一にされる
。このため、半導体基板ｌの表面での逆バイアス時窒乏
層を更に延ばすことができ、ＰＮ吸合の高耐圧化と、そ
の安定化上はかることができる。According to such a planar semiconductor device, the limit of the '#- conductive plate substrate 1 type region 2? The potential gradient when reverse biased is made uniform under the high resistance film 4 by this high resistance film 4. Therefore, the nitrogen depletion layer on the surface of the semiconductor substrate 1 during reverse bias can be further extended, and it is possible to increase the breakdown voltage of PN absorption and to stabilize it.

しかしながら、絶縁膜３が高抵抗膜４全半導体基板ｌか
ら絶縁しているため、高抵抗膜４の電位分布と、半導体
基板１の表１での電位分布とは一致せず、電位のアンバ
ランスを生じｈ　十５＋４い師永電圧が得られないと言
う欠点を持っていた○本発明の目的はプレーナ型半導体
装置において逆バイアス時降４に電圧を高めることにあ
る。However, since the insulating film 3 is insulated from the high resistance film 4 and the entire semiconductor substrate l, the potential distribution of the high resistance film 4 and the potential distribution of the semiconductor substrate 1 in Table 1 do not match, resulting in potential imbalance. However, the object of the present invention is to increase the voltage during reverse bias in a planar type semiconductor device.

本発明１ｃよれば半導体基板上のＰへ咲合部ゲ半絶縁性
の半導体、特ｃｍ−ｖ族や■−■族の化合物半導体で直
吸おおった半導体装置を得る。According to the present invention 1c, a semiconductor device is obtained in which P on a semiconductor substrate is directly covered with a semi-insulating semiconductor, especially a cm-v group or ■-■ group compound semiconductor.

次に図面を用いて本発明をより詳細に説明する。Next, the present invention will be explained in more detail using the drawings.

第２図は１本発明の一実施例によるプレーナ型半導体装
置である。へ型半導体基板ｌｃＰ型領域２が拡散等で形
Ｆｉｙ、されており、これらで形成されるｐ−ｎ腰合金
直咲おおうように表面上（酸素ドープの半絶縁性多結晶
ガリウム砒素等の半絶縁性半導体膜６紫化学的気相成長
法にニジ形成させている。この半絶縁性半導体膜６と、
半導体基板ｌあるいはＰ壁領域２との界［ＩＩ］ｒｃは
、格子定数の不一致による格子不整もしくは、結晶粒界
に存在するダングリングボンドによって発生する多くの
トラップ準位を介してオ五ミック電流を流すことができ
る。したがって、逆バイアス印加時における半絶縁性半
導体膜６中の電位分布と半導体基板１表向の電位分布と
が一致し、従来のアンバランスは生ぜずより高い降イ匁
電圧を得ることができる。FIG. 2 shows a planar semiconductor device according to an embodiment of the present invention. The LCP type region 2 of the hexagonal semiconductor substrate is shaped by diffusion, etc., and the surface is covered with a p-n alloy (such as oxygen-doped semi-insulating polycrystalline gallium arsenide). An insulating semiconductor film 6 is formed using a purple chemical vapor deposition method.This semi-insulating semiconductor film 6 and
The boundary [II]rc with the semiconductor substrate l or the P wall region 2 generates an ohmic current through many trap levels generated by lattice mismatch due to lattice constant mismatch or dangling bonds existing at grain boundaries. can flow. Therefore, the potential distribution in the semi-insulating semiconductor film 6 and the potential distribution on the surface of the semiconductor substrate 1 when a reverse bias is applied match, and a higher motherme voltage can be obtained without causing the conventional unbalance.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体装置の断面図、第２図は本発明の
一実施例による高耐圧プレーナ型半導体装置の断面図で
ある。 ｌ・・・Ｎ型半導体基板、２・・・Ｐ型領域、３・・・
絶縁膜、４・・・高抵抗膜、５・・・電極配線層、６・
・・半絶縁性化合物半導体膜FIG. 1 is a sectional view of a conventional semiconductor device, and FIG. 2 is a sectional view of a high voltage planar semiconductor device according to an embodiment of the present invention. l...N-type semiconductor substrate, 2...P-type region, 3...
Insulating film, 4... High resistance film, 5... Electrode wiring layer, 6...
・Semi-insulating compound semiconductor film

Claims (1)

【特許請求の範囲】[Claims] 一導電型１に有する半導体領域の表面に他導電型を有す
る半導体領域が形成され、これら半導体領域で形成する
ｐ−ｎ１１合上にこれらの領域１０戦して半絶縁性化合
物半導体膜を形成させたことを特徴とする半導体装置。A semiconductor region having another conductivity type is formed on the surface of a semiconductor region having one conductivity type 1, and a semi-insulating compound semiconductor film is formed on the p-n11 junction formed by these semiconductor regions by forming 10 of these regions. A semiconductor device characterized by:
JP58092837A 1983-05-26 1983-05-26 Semiconductor device Pending JPS59218733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58092837A JPS59218733A (en) 1983-05-26 1983-05-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58092837A JPS59218733A (en) 1983-05-26 1983-05-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59218733A true JPS59218733A (en) 1984-12-10

Family

ID=14065538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58092837A Pending JPS59218733A (en) 1983-05-26 1983-05-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59218733A (en)

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