JPS592148A - Loop processing system - Google Patents

Abstract

PURPOSE:To make it unnecessary to execute a line form-processing at every loop processing, by positioning an entry instruction of a loop at a word boundary position, and interposing a no-operation instruction instead, in case when the entry instruction concerned does not exist in the word boundary position. CONSTITUTION:In case when a 1-word length instruction is stored as 4-byte from a word boundary position (code 4), the whole of a desired 1-word length instruction can be inputted by fetching of once. In case when the 1-word length instruction is stored as 4-byte from a position which is not the word boundary position (code 5), usually the first half of the instruction concerned 5 is inputted by fetching of the first 1-word portion, the latter half of the instruction concerned 5 is inputted by fetching of the following 1-word portion, and it becomes necessary to form a line by a line form-processing function 3, but first of all, the instruction is positioned in the word boundary position (code 6), instead of which a no- operation instruction of a non-1-word length instruction is interposed (code 7). In this way, it is unnecessary to execute a line form-processing at every loop processing, and the efficiency can be improved as a whole.

Description

DETAILED DESCRIPTION OF THE INVENTION (4) Technical Field of the Invention The present invention relates to a loop processing method, in particular, to storing an entry instruction of a sequence of instructions constituting a loop in a program at a word boundary position in a main memory, and The present invention relates to a loop processing method in which a no-operation instruction is executed to perform storage.

(B) Technical Background and Problems Traditionally, main memory has had a mix of one-word long instructions and half-word long instructions, but when fetching instructions from main memory, Move the so-called word boundary position upward 1
Seven etches are performed for each word. For this reason, as the above-mentioned half-word length instructions are mixed, for example, the storage address of the one-word length instruction may not be located at the above-mentioned word boundary position. Two words including a one-word length instruction are fetched and fetched (fetched in two steps), and a desired one-word length instruction is extracted by performing alignment processing.

Fetching that involves such sorting processing only requires an extra time of, for example, 2τ, but in a government-funded program for scientific and technical calculations such as FORTRAN, it is necessary to Most of the execution time is often spent processing loops in a few places,
It is important to efficiently process these loops.

(C1 Purpose and Structure of the Invention The present invention aims to provide a method for solving the above-mentioned problems.) The loop processing method of the present invention is such that a one-word length instruction is mixed with a one-word length instruction. a main memory in which a non-one-word length instruction is stored; and a processor that fetches the instruction from the main memory and proceeds with processing, and the main memory starts at a word boundary position. In a data processing system configured to transfer one word, an entry instruction located at the loop entrance of a sequence of instructions constituting a loop is not stored at a storage address aligned with the word boundary position, and the above A no-operation instruction for aligning the storage address of the entry instruction with the word boundary position is inserted between the instruction before the entry instruction and the entry instruction, and the entry instruction of the instruction sequence forming the loop is inserted. It is characterized in that it is fetched from the word boundary position.

This will be explained below with reference to the drawings.

(DJ Embodiment of the Invention FIG. 1 is an explanatory diagram for explaining the meaning of word boundaries in the present invention, and FIG. 2 is an explanatory diagram for explaining the main part of one embodiment of the present invention.

In FIG. 1, 1 is a main storage device, 2 is a processor, and 3 is a main storage device.
represents the sorting processing function section. In the case shown, 1 word 4
The location where the lower two bits of the address in the main memory 1 indicate "00", which is shown as a byte, corresponds to the word boundary location according to the present invention. When an instruction is fetched from the main memory 1, four bytes (ie, one word) starting from the word boundary position are transferred to the promoter 2 at one time.

For this reason, if the instruction is stored as 4 bytes from the 5-word boundary position, such as the 1-word length instruction shown by reference numeral 4, the entire desired IM-length instruction f can be fetched in one fetch. However, when the 1-word length instruction shown in the figure 5 is stored as 4 bytes starting from a position that is not a 1-word boundary position, the first 1 [i! The first half of the instruction 5 is taken in by the 7/7 etch, and the next 7/7
Due to ecchi, the second half of the instruction 5 is now included,
It is necessary to perform the alignment using the alignment processing function section 3.

As mentioned in the "Technical Background and Problems" section above, if the loop entry instruction is located in a way that requires the above sorting process, the above sorting process will be necessary every time the loop is repeated. , which can greatly affect the overall processing.

For this purpose, in the case of the present invention, when the entry instruction of a loop is located as shown by the symbol 5, the entry instruction is located at a word boundary position as shown by the symbol 6, and for this compensation, A no-operation instruction, which is a non-one-word-length instruction, is interposed as indicated by the reference numeral 7 in the figure. Of course, the no-operation instruction does not need to be placed immediately before the loop entry instruction.

By doing so, although there is a time loss associated with the execution of the no-meeting operation command, the above-mentioned sorting is not performed every time the loop processing is performed, and the overall efficiency is improved. Figure 2 illustrates this point.

That is, the illustration in Figure 2 shows the case of a DO loop in which the operation A (I) A (I) 10 B (I) is repeatedly executed until the value ``1'' becomes the value rNJ. There is. FIG. 2 (Bl shows a case in which word boundaries are not considered for the loop entry instructions (I, E) K, and FIG. 2 (C1 shows an embodiment according to the present invention). Both are programs that execute the DO loop shown in FIG. 2 (4).

Figure 2 (B) (In C1, the column labeled "r bytes" indicates the byte length of each instruction;
The column labeled “Position” indicates the byte position r oo on main memory #1.
J, roIJ, r to J, r 1
1J is shown by the way, and the column labeled "Address" indicates the address of main memory #1.

In FIG. 2 (Bl (C1), the instruction (Ll) is stored as a 1-word length instruction indicated by reference numeral 5 in FIG. 1. , command (L)
is stored in 4 bytes starting from byte position ti&rlOJ. This requires the alignment described above. In addition to this, in the case shown in FIG. 2(C), a half-word no-operation instruction r BCRO, OJ is inserted, and the entry instruction (L) is a 4-bit instruction from the word boundary position. It is stored in bytes.

Note that the insertion of the above-mentioned no-operation instruction creates an opportunity for the compiler to optimize the target program.
It will save you a lot of money if you tell them the address of the population command and have them do it as needed.

(H) As described in detail, according to the present invention, inconveniences such as occurrence of loops and wide alignment processing are eliminated, and the overall processing time is significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram illustrating the meaning of a word boundary in the present invention, and FIG. 2 is an explanatory diagram illustrating a main part of an embodiment of the present invention. In the figure, 1 represents a main memory, 2 a processor, and 3 an alignment processing function section. Patent applicant Fujitsu Limited

Claims (1)

[Claims] A main memory in which non-one word length instructions having a length other than one word mixed with one word length instructions are stored, and a processor which fetches the above instructions from the core memory and proceeds with processing. 1 with the main memory starting at the word boundary position.
In a data processing system configured to transfer word segments, an entry instruction located at a loop entry of a sequence of instructions constituting a loop is not stored at a storage address aligned with the word boundary position, and A no-operation instruction for aligning the storage address of the entry instruction to the word boundary position is inserted between the instruction before the instruction and the entry instruction, and the entry instruction of the instruction sequence forming the loop is A loop processing method characterized by fetching from word boundary positions.