JPS59212781A - Voltage comparator - Google Patents

Abstract

PURPOSE:To decrease an offset voltage with simple constitution by providing a hysteresis characteristic by a feedback control to a gate amplifier which outputs a binary signal according to the difference between plural input voltages with a prescribed biasing potential as a boundary. CONSTITUTION:The analog switches S11, S13 of a comparator 10 are turned on by the clock from a clock generator 11 and the electric charge corresponding to an input voltage V1 and the input terminal voltage to provide a bias potential for a gate amplifier G forming an inverter when input and output terminals are short-circuited is accumulated in a capacitor C1. Then the switch S13 is turned on by the inverted clock, the accumulated charge of the capacitor C1 changes according to an input voltage V2 and generates a binary output of 1 or 0 in the gate G according to whether the voltage V1 or V2 is larger with the biasing potential as a boundary. On the other hand, the binary output is fed back via a hysteresis circuit 14 and a capacitor C2 by which a hysteresis characteristic is provided to the gate G and an offset is decreased. The comparison of the slight voltage of a low frequency is stably accomplished by the simple constitution of a digital system.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a method for controlling the madder ellipticity V even when a low frequency minute signal is generated.
The present invention relates to a voltage comparison circuit that performs a C comparison operation.

[Technical background of exemption and its problems]

As a conventional i{j pressure comparator circuit, as shown in Fig. 1, the output of an operating l with a Hikyoryu is manually operated by 8I! +I
'This correct%i}*11. L, hysteresis %+lJ for performing a comparison operation: There is something in favor of A. That is, this voltage comparator circuit has a voltage applied to the inverting input terminal via the resistor R1,
the first input voltage signal el, and the non-inverting input j'(iAi
The standard terminal pressure er. l! l: the operational amplifier It/thus the ratio 11 and the first input voltage 4
When No. 5 el is higher than the reference terminal ゛cancellation pressure er, the low
Outputs a high level signal ``0'', and outputs a high level signal ``1'' when the reverse VL first input voltage 1t is also lower than the terminal voltage e1. It is something to do. Note that the reference terminal voltage er"l'J: is the second voltage applied to the non-inverting input terminal tl of the operational amplifier via the resistor Rz'yti.
A different number of peeking pressures {+I'
, is set to .

However, according to the above-mentioned four-component voltage comparison circuit, the circuit configuration of the operational amplifier f1ζ is complicated, and the offset voltage of the operational amplifier l is ? 1. For example, if the frequency e of the input rectangle 7 pressure 4Fr+ie1 is low and the signal level is small on the 11th day of the rotation test (J- issue), it is impossible to compare the accuracy of the rod. There are drawbacks.

[Purpose of the invention]

A tree invention that eliminates the above-mentioned drawbacks and allows for simplification and integration of circuits.
It is an object of the present invention to provide a voltage ratio converter circuit which can perform a stable comparison operation with high precision even when a minute signal of a high frequency is inputted by suppressing the offset voltage to a small level.

[Summary of the invention]

In the present invention, the acid level that appears at the input terminal K when the input and output terminals are connected by turning on the switch is set as a bias potential, and a plurality of input voltage signals are
．． f; ii↓r,r=gate that outputs binary information depending on the day. T? I want to provide an i width amplifier and a hysteresis circuit that applies hysteresis to the voltage corresponding to the output of this gate amplifier and applies it to the input terminal of the gate amplifier. ? It is r.

[The length of the invention {/, +l) 4 ri 21 nu 1 is a circuit diagram showing an embodiment of this invention]; In the same line 1, 811 and S12 are analog switches that alternately turn on and off according to the clock signal CP7 outputted from the clock signal source 1 and the inverted clock signal CP2 of the clock signal CP1 generated by the inverter 12. Then, one analog switch SJ7
When VC9+R is turned on, l1 is applied to the input pressure signal of younger brother 1 which does not change, and when the other analog switch S12 is turned on, V2 is the second input voltage signal V2 which changes sequentially.
It has the ability to import. The output terminals of these analog switches S771 and S72 are common @Continued No. 1, for example, M
It is connected to -11% of the capacitor C of about 5 to 100 PP' created by the OS or the like. The input of the amplifier G, which has a single input impedance created by an inverter, is the input of the amplifier G, which has the same input impedance as the inverter. (The input/output of this gate amplifier C is connected to
3, the middle 2 h1 is controlled on/off by a clock CP7.

In addition, the output ax of the gate width device G, } has a clock signal C.
P,? A latch circuit 13 that performs a latch operation is connected. Kowa, et al. Sx1~Sl3, Cl
+G+13 makes the comparator 0. Between the output terminal of the latch circuit 13 and the input t:M of the gate amplifier G, there is a signal 'α corresponding to the output of the latch circuit l3.
A hysteresis circuit hal4 is provided for feeding back the pressure signal by giving it a hysteresis characteristic.

14 hysteresis circuits, 81 analog switches
1 to S13, a gate amplifier G, a latch circuit 13, etc., this circuit provides hysteresis characteristics to the comparator 10, and is mainly composed of an inverter 15, a clock inverter group 16, a hysteresis width setting circuit 17, a capacitor 02, etc. . The clock 1...The inverter group 16 includes, for example, four clocks.
It consists of inverters 161-164, among which inverters 161 and 162 have a clock signal J'rCPi of 1
“When the inverter is HI! It has the function of maintaining high impedance during dynamic f + shi and other times.

Next, set the hysteresis width += path 17, resistor Rll,
Itl2 is connected in series, and the other end of resistor Rl7 is connected.
144 of the inverters 161 and 163, and connected to the other end of the other resistor RJ2 or the output end of the clocked inverter 162, 164.
: is connected to the input voltage, and both resistors R11, R.
The hysteresis width is changed by 4· with the resistance ratio of l2.

The capacitor C2 may be a capacitor having a capacitance of 5 to 1oF)lp made by 1νIOS, for example, one end of which is connected to the connection point of both resistors Rll and Rz, and the other end or connected to the human power end of gate amplifier G.
, , a voltage having a certain hysteresis width that can be outputted from the hysteresis width setting circuit 17 is charged.

Next, the operation of the heart pressure comparison circuit configured as described above will be explained.

(1) First, operation of the comparator IO excluding the hysteresis circuit 148: When the clock signal CPi is "1", the input and output terminals of the gate amplifier G are short-circuited by turning on the analog switch S"1eS12. In this short-circuit state, as shown in FIG. When inputted, an electric current of QJ=(,7(VJ-VA)---=(1)) is charged across both ends of the capacitor C.

Next, when the clocked 7Cr'z is 61, the analog switch S72 is turned on [2, and the voltage at the input terminal of the capacitor C7 becomes 2. At this point, if the potential at point A, which is the input ☆l+11 of K1/amplifier G, is VAl and 1-, then
゛N%+=QJ′l of capacitor c, QJ′=C7(V.?−VA′)−(2). Since this ``lord'', tfalse sum does not change drastically, in a certain node υj Ifl, the electric wire Q7 and Q1/ are equal, and the gate value when the block clock 5CP2 is X 1''. τJ width {the input 'raisi.' of C can be expressed as

yAt=(vz-V)+VA・---------(3) However, VA is a bias potential. Therefore, (V2-V7
) is positive, ゝゝ0' appears at the output terminal of the Kate amplifier G functioning as an inverter, and when (V2-VJ) is negative, the output 3゛(/c) of the same amplifier G appears as ゝゝ1. `` appears.Sho 3 1 shows such a category.And,
Gate amplifier G when clock number CP2 is "1"
The output of (1) is latched by the latch circuit 13 by the clock number CP2, and this similar VO is output from the comparator IO. - Comparator lo(ri, V2
-Vl(D~θ=ゝゝ0'', V2(V1(1
), Vo-ゝ゛1'' becomes 0 (second order K, comparator IOVC hysteresis times tl
Operation when +''il4 is added.

1', When the output of the latch circuit l3 is 1, and the clock signal Cp1 becomes 1, Rj' is written. !XO" is applied to the output terminal of the clocked inverter 161, while the clocked inverter 161 operates as
Output end of inharter 162. ``Nike'1'' appears.

Therefore, L1. 'jlJ Tsukuda ゝゞ0'', resistance R72
According to one rule, ゝゝ1'' is the sign nonoa δE1, and this 7''L charges the capacitor C2 with a charge Q2 like a Q-order type.

However, VDDI'l'Clocked Fist Imperter 161~
``'ノ'r+jSource1+.yIEToru.Nao, VDD
(V) corresponds to i1ii1i;l'ijゝゝゝ1//shiko, and OM is tied to logic ゝゝゝゝゝゝゝゝゝゝ.

Next (finally, when the output of the latch circuit 13 is 91", the evening lock signal CI) is "0" (the clock signal - Sc..E
) When p becomes ゝゝ1“), Clot ● I7 Hata 16
．． i, 164 as an inverter, sword 11-shi, unbuilt '+'. Rll i rule ゝゝ1'', mountain resistance 'Ftl2$4
11D, ko, 0" appear respectively. Therefore, ku1"
When the Tsuk iiff No. CPl is "1", the condensation n
In c2, the charge that can be fully charged in C7 and C2 (:) ivQ2tQl'
, Q2''s "to}go KfdQ1+Q2=Q1'+Q2'
Since the relationship holds true, the voltage 'VA' is determined by equations (1), (2), (4), and (5). In order to simplify the above equation, let us take the example of 07-C2, and it can be expressed as follows. Therefore, from equation 6y, the difference voltage (V2
-VJ) vc vs. heel}tsugi! I'yl1vDDRxl+R
A voltage with a hysteresis characteristic of 1z is applied. In other words, the comparative voltage circuit shown in FIG.
R2z is added. Similarly, v2>V, and the electric charge becomes discharged. Therefore, when the capacitor is vO-ゝゝO'', the voltage vA/ becomes, and at point A -L = R77
, V[)I) hysteresis Rll·toR12 cis'i+Ji, the pressure is b. Here, the frequency of the clocked %CP9CP2 is the input '[d pressure No. 16 V'
Since it has a high circumference (10 ta) compared to V21c, it is possible to operate the circuit shown in FIG. 2 as a sampling converter.

According to the above-mentioned withering, the pile is comparator 10
As a digital circuit joint (one inharter {, one'
Gate +; :
．． W;、IL! 1i It is due to the accumulation of stuttering and the small size of the stutter.゛ma/(, the input end bias of the gate N, R width 4110G changes, and with this bias potential as the boundary, the difference in pressure between the two input pressure signals is positive or negative, and the gain is 1. Amplification r: 4 ÷
Since the output of G is constant, and it is clear from equations (6)' and (6y'!:.C, the input voltage of gate amplifier G is high as lJχ
The comparison operation can be performed stably even if the capacitance of the capacitors C1 and C2 changes, and furthermore, the input voltage of the gate amplifier G, ! i, please add lysis voltage j7
Therefore, even if the input calm pressure signal V2 changes slowly, 4"V.l@L operation is performed compared to the low voltage. Also, the comparator 1 node 10 and the hysteresis circuit 14 both M
'This can be easily realized using OS Digital Toryo technology. Also, the hysteresis width is determined by the resistance R. 71,Rl
It can be easily varied by the ratio of 2, and the resistance t7R1, R
Since it does not depend on the variation in the absolute value of lz, it can be said that the annual accumulation is easy in this respect.The hysteresis width is determined by resistors Rll, R12 and capacitors CI, Cz, and the input air pressure signal Even if a high-impedance source is used for the voltage source that outputs V7 and VZ, stable operation can be ensured, and the current consumption of the entire circuit can be reduced.

In addition, in the present invention, the above-mentioned fruit cannot be directly determined by 49ji&. For example, in the above embodiment, V7 is an unchanging voltage signal and v2 is a changing voltage signal, but these voltage signals may be completely reversed, or both voltages may be expressed as +; V7, V2.
1-' is also good.

丑, ノ1′ とは・fll,7,′d:;゛/Bark is also good, 1 switch SII ~ SL 3 analog switch 1000-ji Rokuka-8 FT, ET? - (A, 7) Even if it is a switching element: No. (/4S+-7 teresis circuit 14)
Instead of using ``coffin'', it is also possible to use a coffin like ``1''.
~R2. ? Serial V? When the contact hC is applied, an inverter l5 is connected to both ends of the stiff resistance circuit W1, and the sum 'l
Then, the resistance [[-11
Voltage applied to the line (1 ton 21~l?.23) 4.・Anti-1・
One tau, analog switch 814lSl5t-t! !
', and outputs it. This place R22 1-nuterishi left 14; id, Sat-Rz7+R2z〒
“It will be 100 DD. In addition, Honzu [Yuj] can be realized by making various changes within the scope of V without departing from its gist.

〔Effect of the invention〕

As described in detail above, the wooden invention has the advantage of not being able to convert power into digital masonry circuits easily, but with manual voltage control, which does not shift even if the frequency is low and the signal is minute. Usumi provides a voltage comparison circuit that can perform a wide range of tJC comparison operations.

[Brief explanation of the drawing]

Fig. 1 shows the configuration of the push-button circuit L''I, iA = 2 (Fig. 1). The figure is an input/output characteristic diagram of the gate i7;・amplifier in FIG. Kus・r sona, G...game 1・''゛old breadboard, lO...combarek, Cノ, C
2...con answer, no 3...ratsuna round de, l4...
・Hysteresis circle path, l6...Closet 1-・Inperter phase, l7...Hysteresis 1 [hull setting circuit.

Claims (2)

[Claims] (1) Switch control A: 1 and 2 which alternately turn on in response to No. 8 and alternately take in No. 16 of pressure due to multiple inputs.
a capacitor for swinging a voltage corresponding to the input voltage input by turning on these switches; and a capacitor connected to the output side of this capacitor and turned on in response to the switch control I. The potential appearing at the input terminal when the input and output terminals are short-circuited by turning on the third switch and the switch J1, which is provided between both terminals of the third switch, is defined as the bias mI☆. , a gate amplifier which outputs a binarized signal h based on the difference between the plurality of input voltage signals with this bias level as a border, and a holding amplifier which holds the output of this gate amplifier. circuit and
A voltage comparator circuit comprising: a hysteresis circuit that connects a voltage corresponding to the output of the length holding circuit to the input terminal of the gate amplifier with a predetermined hysteresis width; (2) The gate amplifier uses an inverter that handles a high input impedance.The voltage comparator circuit described in item (1) of the patent claim is characterized in that: Switch control {In response to the Th signal, inverter operation is started; a clocked inverter group that alternately inverts the output voltage according to the output of the voltage regulator circuit, and a voltage output from this clocked inverter group. This device includes a hysteresis width setting circuit that provides hysteresis to the gate amplifier, and a capacitor that stores the output of this hysteresis width setting circuit, and applies a voltage with hysteresis characteristics to the input terminal of the gate amplifier through this capacitor. A voltage comparison circuit according to claim (1).