JPS59210649A - Mounting structure of semiconductor device - Google Patents
Mounting structure of semiconductor deviceInfo
- Publication number
- JPS59210649A JPS59210649A JP8944984A JP8944984A JPS59210649A JP S59210649 A JPS59210649 A JP S59210649A JP 8944984 A JP8944984 A JP 8944984A JP 8944984 A JP8944984 A JP 8944984A JP S59210649 A JPS59210649 A JP S59210649A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chips
- electrodes
- melting point
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- 208000025174 PANDAS Diseases 0.000 claims 1
- 208000021155 Paediatric autoimmune neuropsychiatric disorders associated with streptococcal infection Diseases 0.000 claims 1
- 240000000220 Panda oleosa Species 0.000 claims 1
- 235000016496 Panda oleosa Nutrition 0.000 claims 1
- 238000002844 melting Methods 0.000 abstract description 10
- 230000008018 melting Effects 0.000 abstract description 10
- 229910000679 solder Inorganic materials 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 6
- 239000004593 Epoxy Substances 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 4
- 125000006850 spacer group Chemical group 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 28
- 230000017525 heat dissipation Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000008188 pellet Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は半導体装置の実装構造に関するものである。[Detailed description of the invention] The present invention relates to a mounting structure for a semiconductor device.
最近、電気機器の小型化にともなって半導体集積回路装
置（ＩＣ）の高集積化への要求は一層大きくなっている
。2. Description of the Related Art Recently, with the miniaturization of electrical equipment, the demand for higher integration of semiconductor integrated circuit devices (ICs) has become even greater.
この要望に答えるための実装構造として半導体チップ（
ベレット）を一つの配線基板に多数組込むマルチチップ
実装構造が適する。そして、マルチチップ実装において
は、主として全ての半導体チップを画一的に組込めるＣ
ＣＢ（コントロール・コラプス・ボンディング）方式が
採用される。A semiconductor chip (
A multi-chip mounting structure in which a large number of chips (such as pellets) are incorporated into one wiring board is suitable. In multi-chip packaging, C is mainly used to uniformly incorporate all semiconductor chips.
The CB (control collapse bonding) method is adopted.
このＣＣＢ方式は半導体チップにバンプと称する突出電
極を設け、配線基板の配線面に直接対向させて接続する
ものである。In this CCB method, protruding electrodes called bumps are provided on a semiconductor chip, and these are directly opposed to and connected to the wiring surface of a wiring board.
このようなＣＣＢ方式として特公昭４７−６１３０号公
報に示すようなものがある。As such a CCB system, there is one shown in Japanese Patent Publication No. 47-6130.
しかし、ＣＣＢ方式による実装においては、バンプ電極
が一般に小形であり、配線基板の絶縁体と各半導体チッ
プを構成するシリコンとの間の熱膨張率の差による影響
を直接受け、同時に動作時に半導体チップから発生する
熱の放散も十分でないことから、上記熱膨張率の差に起
因する半導体チップの破損及び熱放散性の悪いことによ
る半導体装置の特性劣化が生じ１いた。However, in mounting using the CCB method, the bump electrodes are generally small and are directly affected by the difference in thermal expansion coefficient between the insulator of the wiring board and the silicon that constitutes each semiconductor chip. Since the heat generated from the semiconductor chip is not sufficiently dissipated, the semiconductor chip is damaged due to the difference in the coefficient of thermal expansion, and the characteristics of the semiconductor device are deteriorated due to poor heat dissipation.
これらを防止するためには、配線基板に熱放散性を良く
する何んらかの手段を講じる必要があり、また熱膨張率
の差を少べするために各半導体チップにそれぞれ大形の
バンプ電極を作る必要がある。In order to prevent these, it is necessary to take some measures to improve heat dissipation on the wiring board, and also to install large bumps on each semiconductor chip to reduce the difference in thermal expansion coefficient. We need to make electrodes.
しかしそうすると、配線基板を大きく精巧なものとし、
半導体チップも大きなバンプ電極を形成する分だけ大形
化しなければならずその結果半導体装置の集積度が低下
し、またこのように実装された半導体装置が高価なもの
となっていた。However, in doing so, the wiring board would have to be large and sophisticated, and
The semiconductor chip also has to be increased in size to accommodate the formation of large bump electrodes, resulting in a reduction in the degree of integration of the semiconductor device and also making the semiconductor device mounted in this manner expensive.
本発明は上記を考慮してなされたもので、その一つの目
的は半導体装置の実装密度の向上を図るものであり、他
の目的は配線基板と半導体チップの間の熱膨張率の差に
起因するチップの破損の防止にあり、又他の目的は半導
体チップよりの熱放散性の悪いことに起因する半導体装
置の特性劣化を防止するものであり、さらに他の目的は
高集積化半導体装置を安価に提供することにある。The present invention has been made in consideration of the above, and one purpose thereof is to improve the packaging density of semiconductor devices, and another purpose is to improve the packaging density of semiconductor devices due to the difference in thermal expansion coefficient between the wiring board and the semiconductor chip. Another purpose is to prevent the deterioration of the characteristics of semiconductor devices due to poor heat dissipation properties than semiconductor chips. The aim is to provide it at a low price.
以下本発明の詳細な説明する。The present invention will be explained in detail below.
第１図は本発明の前提となる半導体装置の実装構造の一
実施例を示すものである。FIG. 1 shows an embodiment of a mounting structure of a semiconductor device, which is the premise of the present invention.
同図に示すように一エポキシ系材料からなる絶縁基板ａ
の一生面上に配線層１ｂを形成した比較的広い配線基板
１の上に、シリコンを主体とする基板３ａの一生面上に
配線層３ｂを形成し半田からなる大形のバンブ電極２を
有するシリコン配線基板３を上記バンブ電極２を介して
フェイスボンディングにより接続されている。上記シリ
コン配線基板３の縦横の寸法は例えば１ｃｒｎ２ とし
、その−主面周辺部にそってＰｂ／Ｓｎ ＝ ６０ ／
４０からなる０、２０φ〜ＩＩＩＩＩ径の大形のバン
ブ電極２が多数配設されている。これを配線基板１に対
し配線面を対向させて半田ディツプにより接続する。シ
リコン配線基板３の配線面上には内部に多数の回路素子
によりＩＣを構成し１周辺部に半田からなる小形のバン
ブ電極４を有するシリコン半導体チップ（ペレット）５
を上記バンブ電極４を介してフェイスボンディングによ
り接続されている。上記シリコン半導体チップ５の寸法
は例えば数ｍｍ”とし、その基板表面周囲にＰｂ／５ｎ
＝９５１５からなる小形のバンブ電極４を多数配設され
ている。As shown in the figure, an insulating substrate a made of epoxy material
A wiring layer 3b is formed on the entire surface of a substrate 3a mainly made of silicon, and a large bump electrode 2 made of solder is provided on a relatively wide wiring substrate 1 on which a wiring layer 1b is formed on the entire surface of the substrate. A silicon wiring board 3 is connected via the bump electrode 2 by face bonding. The vertical and horizontal dimensions of the silicon wiring board 3 are, for example, 1 crn2, and Pb/Sn = 60 / along the periphery of the main surface thereof.
A large number of large bump electrodes 2 having a diameter of 0.20 to 3.40 mm are arranged. This is connected to the wiring board 1 with the wiring surface facing it using a solder dip. On the wiring surface of the silicon wiring board 3, there is a silicon semiconductor chip (pellet) 5, which has a small bump electrode 4 made of solder on the periphery, and has a large number of circuit elements forming an IC inside.
are connected via the bump electrode 4 by face bonding. The size of the silicon semiconductor chip 5 is, for example, several mm, and the periphery of the substrate surface is Pb/5n.
A large number of small bump electrodes 4 made of =9515 are arranged.
、これとシリコン配線基板３とをそねぞれ配線面と対向
させ、半田ディツプにより接続する。, and the silicon wiring board 3 are connected to each other by solder dips, with the wiring surfaces facing each other.
第２図は本発明による半導体装置の実装態様の一例を組
立類に示したものである。FIG. 2 shows an example of an assembly of a semiconductor device according to the present invention.
（ａ）ＣＣＢ用の小形のバンブ電極４をシリコン半導体
チップ５上に形成する。このバンブ電極４に使用した半
田（Ｐｂ／Ｓｎ ＝ ９５ ／ ５ ）の融点は約３４
０℃である。(a) A small bump electrode 4 for CCB is formed on a silicon semiconductor chip 5. The melting point of the solder (Pb/Sn = 95/5) used for this bump electrode 4 is approximately 34
It is 0°C.
一方、シリコンを基板としその上面に配線層を形成した
シリコン配線基板３を用意する。On the other hand, a silicon wiring board 3 having a silicon substrate and a wiring layer formed on its upper surface is prepared.
（ｂｌ そして、各シリコン半導体チップ５をバンブ
電極４の融点よりも若干高い３５０℃〜３７０℃で加熱
してシリコン配線基板３上にフェイスボンディングによ
り同時に取付ける。(bl) Then, each silicon semiconductor chip 5 is heated at 350° C. to 370° C., which is slightly higher than the melting point of the bump electrode 4, and simultaneously mounted on the silicon wiring board 3 by face bonding.
（ｃｌ 次に半導体チップ５を取付けたシリコン配線
基板３の上記主面周辺部に他の配線基板との接続用〕大
形のバンブ電極２を形成する。このバンブ電極に使用す
る半田（Ｐｂ／Ｓｎ ＝６０／４０ ）の融点は約１８
０℃である。(cl) Next, a large bump electrode 2 (for connection with another wiring board) is formed around the main surface of the silicon wiring board 3 on which the semiconductor chip 5 is attached.Solder (Pb/ The melting point of Sn = 60/40) is approximately 18
It is 0°C.
（ｄｌ その後、第１図に示すように半導体チップ５
を取付けたシリコン配線基板３を大形のバンブ電極２の
融点よりも若干高い１９０℃〜２００℃で加熱しエポキ
シ系材料の配線基板１に取付ける。(dl Then, as shown in FIG. 1, the semiconductor chip 5
The silicon wiring board 3 with the attached silicon wiring board 3 is heated at 190 DEG C. to 200 DEG C., which is slightly higher than the melting point of the large bump electrode 2, and attached to the wiring board 1 made of an epoxy material.
なお、このとき各半導体チップ５を固定しているバンブ
電極４はシリコン配線基板３を固定している大形のバン
ブ電極２の融点よりも充分高い融点を有するので、この
シリコン配線基板３の取付けのときにバンブ電極４が融
けて半導体チップ５が取れてしまうことは全くない。At this time, since the bump electrodes 4 that fix each semiconductor chip 5 have a melting point that is sufficiently higher than the melting point of the large bump electrode 2 that fixes the silicon wiring board 3, the mounting of the silicon wiring board 3 is difficult. At this time, there is no possibility that the bump electrode 4 will melt and the semiconductor chip 5 will be removed.
本発明は上記半導体装置の実装構造をさらに改善したも
のであり、第３図に示すように熱放散性を良くするため
に、シリコン半導体ペレット５とエポキシ系材料の基板
１との間の空間部に放熱性のよい金属板からなるスペー
サ６を介挿するものである。これにより半導体チップ５
から発生した熱は小形のバンブ電極４と同時にこの金属
板６を通して放散されるので熱放散が極めてよくなる。The present invention further improves the mounting structure of the semiconductor device described above, and as shown in FIG. 3, the space between the silicon semiconductor pellet 5 and the substrate 1 made of epoxy material is A spacer 6 made of a metal plate with good heat dissipation properties is inserted between the two. As a result, the semiconductor chip 5
The heat generated from the metal plate 6 is dissipated simultaneously with the small bump electrode 4, so that heat dissipation is extremely improved.
このような本発明によれば、シリコン半導体チップがシ
リコン配線基板にバンブ電極を介して取付けられている
から、半導体チップと配線基板との材料が同じであり両
者の間の熱膨張率の差が全くなくなるっ又、上記したよ
うに半導体チップ５から発生した熱は放熱体となる金属
板６を通して放熱される。According to the present invention, since the silicon semiconductor chip is attached to the silicon wiring board via the bump electrode, the semiconductor chip and the wiring board are made of the same material, and the difference in thermal expansion coefficient between them is minimized. In addition, as described above, the heat generated from the semiconductor chip 5 is radiated through the metal plate 6 serving as a heat radiator.
したがって、半導体チップは熱膨張率の差による影響を
直接受けることなく、又、半導体チップから発生する熱
の放散もよいことがら、熱膨張率の差に起因する半導体
チップの破損及び熱放散性の悪いことに起因する半導体
装置の特性劣化を充分に防止することができるものであ
る。Therefore, the semiconductor chip is not directly affected by the difference in the coefficient of thermal expansion, and since the heat generated from the semiconductor chip is well dissipated, damage to the semiconductor chip due to the difference in the coefficient of thermal expansion and heat dissipation are reduced. This makes it possible to sufficiently prevent characteristic deterioration of the semiconductor device due to unfavorable circumstances.
さらに、半導体チップが組込まれたシリコン配線基板は
大形のバンブ電極を介して他の配線基板に取付けられて
いるから、シリコン配線基板と他の配線基板との間に熱
膨張率の差が比較的大きくてもその差によるストレスを
両者間に介在させた大形のバンブ電極により吸収するこ
とができ、シリコン配線基板の破損は全くなくなる。Furthermore, since the silicon wiring board on which the semiconductor chip is embedded is attached to other wiring boards via large bump electrodes, there is a difference in thermal expansion coefficient between the silicon wiring board and other wiring boards. Even if the target is large, the stress caused by the difference can be absorbed by the large bump electrode interposed between the two, and the silicon wiring board will not be damaged at all.
また、本発明によれば、シリコン配線基板に大形のバン
ブ電極を形成するが、これとて、各半導体チップに大形
のバンブ電極を形成して配線基板に直接取付けて熱膨張
率の差によるチップの論損を防止し熱放散性を良好によ
るものに比べれば。Further, according to the present invention, a large bump electrode is formed on a silicon wiring board, and this is achieved by forming a large bump electrode on each semiconductor chip and attaching it directly to the wiring board, so that the difference in coefficient of thermal expansion It prevents the loss of the chip and has good heat dissipation compared to the one due to the heat dissipation.
大形のバンブ電極を形成する数もずっと少なく。The number of large bump electrodes formed is also much smaller.
使用する他の配線基板も充分小面積のものでよい。The other wiring boards used may also have a sufficiently small area.
したがって、半導体装置の高集積化が図れるとともに実
装された高集積化半導体装置が安価なものとなる。なお
、本発明によれば、半導体チップはシリコン配線基板と
他の配線基板に包囲されているので５機械的保護が確実
となる。Therefore, the semiconductor device can be highly integrated, and the mounted highly integrated semiconductor device can be made inexpensive. Furthermore, according to the present invention, since the semiconductor chip is surrounded by the silicon wiring board and another wiring board, mechanical protection is ensured.
以上本発明によれば、実装による半導体装置の高集積化
が図れ、熱膨張率の差に起因する半導体チップの破損及
び熱放散性の悪いことによる半導体装置の特性劣化が防
止でき、さらには安価な高集積化半導体装置が提供でき
る等の顕著な効果を奏するものである。As described above, according to the present invention, it is possible to achieve high integration of semiconductor devices through packaging, prevent damage to semiconductor chips due to differences in thermal expansion coefficients and deterioration of characteristics of semiconductor devices due to poor heat dissipation, and furthermore, reduce costs. This provides remarkable effects such as the ability to provide highly integrated semiconductor devices.
第１図は本発明の前提となった半導体装置の実装構造の
縦断面図、第２図は第１図に示す実装構造の実装工程を
示すもので、（ａ）〜（ｃ）は各〒程の縦断面図、第３
図は本発明に従った実施例の縦断面図である。
′１・・・配線基板、２・・・大形のバンブ電極、３・
・・シリコン配線基板、４・・・小形のバンブ電極、５
・・・シリコン半導体チップ、６・・・スペーサ。
第 １ 図
第 ２ 図
第 ３ 図FIG. 1 is a vertical cross-sectional view of the mounting structure of a semiconductor device, which is the premise of the present invention, and FIG. 2 shows the mounting process of the mounting structure shown in FIG. 1. Longitudinal cross-sectional view of the area, 3rd
The figure is a longitudinal sectional view of an embodiment according to the invention. '1... Wiring board, 2... Large bump electrode, 3...
...Silicon wiring board, 4...Small bump electrode, 5
...Silicon semiconductor chip, 6...Spacer. Figure 1 Figure 2 Figure 3
Claims (1)
プ電極を介してシリコンを主体とする基板に取付け、上
記複数の半導体チップのパンダ電極が接続される側とは
反対の側に放熱体を設けたことを特徴とする半導体装置
の実装構造。1. A plurality of semiconductor chips mainly made of silicon are attached to a substrate mainly made of silicon via bump electrodes, and a heat sink is provided on the side opposite to the side to which the panda electrodes of the plurality of semiconductor chips are connected. A mounting structure for a semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8944984A JPS59210649A (en) | 1984-05-07 | 1984-05-07 | Mounting structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8944984A JPS59210649A (en) | 1984-05-07 | 1984-05-07 | Mounting structure of semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51088150A Division JPS6019658B2 (en) | 1976-07-26 | 1976-07-26 | Semiconductor device mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59210649A true JPS59210649A (en) | 1984-11-29 |
Family
ID=13970992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8944984A Pending JPS59210649A (en) | 1984-05-07 | 1984-05-07 | Mounting structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59210649A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2697125A1 (en) * | 1992-10-20 | 1994-04-22 | Thomson Csf | A method of mounting a microstructure and microstructure mounted according to the method. |
| US6515370B2 (en) | 1997-03-10 | 2003-02-04 | Seiko Epson Corporation | Electronic component and semiconductor device, method for manufacturing the same, circuit board have the same mounted thereon, and electronic equipment having the circuit board |
-
1984
- 1984-05-07 JP JP8944984A patent/JPS59210649A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2697125A1 (en) * | 1992-10-20 | 1994-04-22 | Thomson Csf | A method of mounting a microstructure and microstructure mounted according to the method. |
| US6515370B2 (en) | 1997-03-10 | 2003-02-04 | Seiko Epson Corporation | Electronic component and semiconductor device, method for manufacturing the same, circuit board have the same mounted thereon, and electronic equipment having the circuit board |
| US6803663B2 (en) | 1997-03-10 | 2004-10-12 | Seiko Epson Corporation | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board |
| US6989605B2 (en) | 1997-03-10 | 2006-01-24 | Seiko Epson Corporation | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board |
| US7119445B2 (en) | 1997-03-10 | 2006-10-10 | Seiko Epson Corporation | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board |
| US7436071B2 (en) | 1997-03-10 | 2008-10-14 | Seiko Epson Corporation | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board |
| US7598619B2 (en) | 1997-03-10 | 2009-10-06 | Seiko Epson Corporation | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board |
| US7932612B2 (en) | 1997-03-10 | 2011-04-26 | Seiko Epson Corporation | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board |
| US8134237B2 (en) | 1997-03-10 | 2012-03-13 | Seiko Epson Corporation | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board |
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