JPS59207091A - Data output circuit of dynamic memory - Google Patents

Abstract

PURPOSE:To display a high speed property due to the adoption of a nibble mode function sufficiently by expanding a data window down to about the minimum value of cycle time necessary for a circuit. CONSTITUTION:One of respective nodes to be gate inputs of a load transistor (TR) of an output part and a drive TR in accordance with the data of a DO line coupler to be a data transfer node of a 4-bit latch holding 4-bit data at a nibble mode is connected to Vss potential and the other is connected to a signal driving the output part to form a circuit for the data output of the DO line coupler. Until the data from the 4-bit latch are outputted to the DO line couple, the output part outputs the same data as the data outputted to the DO line couple in the preceding cycle and then new data are outputted from the 4-bit latch to the DO line couple and then the 4-bit latch is reset, so that the output circuit can be operated even if the output circuit is not reset at the time of precharging.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data output circuit for a dynamic memory having a nibble mode function.

[Technical background of the invention and its problems]

In a dynamic memory with a nibble mode function, for example, having a capacity of 256 bits, the whole cell is divided into four cell groups Ca, cb, cc, and cd, each having 64 bits, as shown in Figure 1. It is set up.

That is, each cell group ca', Cb, cc, cdH
Each row address A is 8 bits. , ~A7R and the 8-bit column address A. It has 64 bits of memory cells selected by C-A7cK.

For example, in the case of a nibble mode read cycle, for each cell group Ca
, Cb, and C6Cd are read out and loaded into a 4-bit latch LhK. Thereafter, each content of the 4-bit latch Lh is sequentially and cyclically read out via the read register Rr every time cAs is completely changed. Output as tJT.

Similarly, in the case of the write cycle of the nibble mode, the input data D1n is sequentially stored in each bit of the 4-bit latch Lh via the write register Wr''f, and the corresponding address of the descendant cell group Ca, Cb+C0+Cd is stored in sequence. A write is made to the cell.

What, I-? P in Figure 1. High-order bit A8R% of row address signal Most significant bit A of column address signal
BC is given, and it performs a cyclic counting operation according to changes in CAS, and depending on the count value, it selects a specific 1 bit from the 4-bit latch Lh)? This is the program counter to select. Tis.

is a selector which selects either read register Br-4 or write register Wr to input/output data according to designation of read cycle and write cycle.

FIG. 2 is a waveform diagram showing the operation of the read cycle, in which the address signal A is applied during the valid period when the row address selection signal is at the "L" level.

~As? The row address is set as the row address, and the column address selection signal is set to the It L # level and the address signal Ao=Aa', which is applied during the valid period, is set as the column address. After selecting the valley address of the row and column in this way, the contents of the cell of the 4-bit register Lh are changed from row address A8R% to column address A every time the surface changes.
The cell specified by 8o is output next and cyclically, starting with the cell specified by 8o.

Similarly, in the case of the input cycle, as shown in the waveform diagram shown in FIG. 3, when the door is at the "L" level and the address signal AO-A8 is applied during the valid period, the address signal AO-A8 is set as the low address.
Furthermore, it is assumed that the address signal A, -Ag'i column address, is applied during the valid period when CAS becomes "L" level. After each row and column address signal is selected in this manner, writing is performed every time the write signal @@Vl/BIT becomes valid and the door changes. For example 4
Where the contents of bit branch Lh are C+ d r a + b, data e + f + g r h + 1 r
Assuming that j+k+A+m+n+0 are given in sequence, data C is first replaced by f'-tae. Then data d to f, a to g, b
from h r from e to if from j, from g to h from A
One replacement is performed from rt to m, from j to n, and from k to 0. And each cell group c, , Cb, cc, specified by the above row address and column address.
The last rewritten data is written into the cell corresponding to c, and the previous data becomes invalid. Therefore, cell a of 4-bit latch Lh.

Each cell group Ca*Cb+Cc corresponding to b+c+d
The contents of the cells corresponding to +cd are each data. .

A+mrn.

In other words, in a dynamic memory having such a nibble mode function, the above column address 9 address 1 bar selection signal can be converted into an address signal by changing CAS k in short cycles while holding T'tAS at "L" level. It is possible to read and write 4-bit data of a series of addresses at high speed in synchronization with .

In the young epsilon extraction cycle of the Shikabichi pull mode, the waste falls as shown in the time chart shown in FIG. 4, and data is output after a certain period of time tNcAc. Then, the above image rises, and data output stops after a certain period of time toffO. Here, the above fixed time tNchc + t+off
is a constant value determined by the circuit. On the other hand, the cycle time tNc is the minimum value tN that guarantees the circuit operation of the precharge time tNcP and the base pulse width hJcAs of CAS.
(It can be set arbitrarily as long as it is greater than or equal to the minimum value tNcmin determined from Hp min r tNCASmin.

Here, the data is received from the memory, and the important thing is the output data D. u, no” VALID DA'rA
``period'', that is, a period during which data is valid, a ``data window.'' A memory with a wide period can be easily used with fewer restrictions when designing peripheral circuits. In order to widen this “data window”, the width tN
It would be possible to increase cAs, but this would mean increasing the cycle time tNC, and as a result, the high speed characteristic of the nibble mode function would be sacrificed. For this purpose, it is desirable to obtain the maximum data window # at the minimum cycle time tNC.

Here, the period of 6 data windows can ideally be extended to the cycle time tNC, but the door width tNcA &
cannot be summed up in words too small.

stomach. The reset time of the data output circuit is controlled by a series of clocks starting from the start of precharge at 9, so it takes time t. ff cannot be made so large either, and is approximately up to the minimum value tNcp, mln of the precharge time. Therefore, the practical maximum of 6 data windows is tNcA
s tNcAc"tNcp min. This means that when operating with the minimum cycle time tN cmln, the value of the "data window" is tN(m1n-t
It becomes about the same as NCAC and becomes significantly narrower.

Also, in order to widen the "data window", the time t. It is also conceivable to make ff significantly larger. However, since the data output circuit is reset using a precharge system clock, if the time toffk is increased, the reset clock must be delayed considerably from the rise of the refill.

In other words, if the precharge time tN(, p k is made too small, the reset clock will not rise and the next cycle will start at the fall of the clock, which will inevitably reduce the minimum value of the precharge time tNcPmin. As a result, the minimum value axis (min) of the cycle time increases, and the high sensitivity of the nibble mode is sacrificed.

Figure 5 is a circuit diagram showing a conventional data output section, which includes three MO
S-FETs 1, 2, and 3 are connected in series and the power supply V
It is inserted between DD. And the above MO8-FET J
, 2 and 3, the data DO and Do read out from the 4-bit latch Lh shown in FIG.
A pair of data transfer nodes that transfer the data are all connected. In addition, each series connection point is connected to the power supply V via MOS-FETs 4 and 5f.
S8, and also connected to r-to of MOS-FETs 9 and 8 via S-FETs 7 and 6 (MC). Then, the precharge clock φ is provided to each date of MO8, -FET1.2.3, and the lv
'IO8-FETs 6 and 7's dates are connected to the power supply vDD. and output drive signal φ. UT to MOS-
FET8. It is connected to the power supply vss through each series circuit of IO and MOS-F'ET9.1. In addition, the gate 9 of MOS-FET 4 is connected to MOS-F
Connect to power supply V88 via ET-2, and connect the MO8-FE
T12's r-to-head discharge charge clock φPk is provided. And the top Me MOS-, FET 4 dirt M
It is commonly connected to the series connection point of each gate of OS-FgTZZ, Is and MOS-FET8, 1θ. Also, the dirt of MOS FET 5 is MOS
- Connect to power supply vs8 through F'ET13 and connect to MO8
-FET13 r-) precharge clock φpft
give. And the above MO8-FET note'&M
OS-FET No. 0, 14 No. each date and MOS
-FET9.

It is commonly connected to the series connection point of 1. Furthermore, MOS which is a load transistor and a drive transistor
-FET 14, 15' (i - power supply vI in series)
The output 0output f is obtained from the data output node inserted between the D I VsS and derived from this series connection point.

In such a configuration, for example, as shown in the timing chart shown in FIG. 6, when CAS is precharged to the "H# level", the precharge clock φp i'j: vp
(> VDD + V7), and the data Do.

Direct is V, level. Therefore, MnS-FET
6 , 8/lJlノ/ -TO''N3 OJ:HIMO8-
The potential of node N4 between FET 7゜9 is "DD"T
becomes. In addition, the node Nl connected to the 9th frame of MnS-FET 15 and MnS-FET I
The potential of the node N2 connected to the gate 4 reaches the v8S level, and the MnS-FBTs 14 and 15 are turned off, resulting in an output of 0.
output becomes high impedance.

When 6■ goes to "L" level, precharge clock φ2 also goes to "L" level, and when data D0 (1) is applied, the nodes N3 and N4 have potentials according to the data.Then, output clock φout goes to ■When the voltage rises to P, node N 1 + N 2 becomes V, level according to the data.Here, node N 1 + N 2
The potential of MnS-FET 8, 6, MnS-F'ET
9.7, the data is returned to Do and Do to ensure data transfer. Then, depending on the potential of the node N1+N2, one of the MnS-FETs 14 and 15 is turned on, and the output 0output is the power supply VDD or the voltage m+V,...
Level and 1r. When the stone rises, the precharge clock φ also rises, and both nodes N 1 + N2 are
It becomes the ss level, and the output (') u tput becomes high impedance. In this case, time t. , f can be increased by delaying the rising edge ff of the precharge clock φ2, but if it is too slow, it will not be possible to rise within the CAS precharge cycle as shown by ψa/ in FIG. 6, and the data l)O ,D.

is not precharged and data cannot be transferred at the next falling edge cycle. Therefore, the above time t. ff can be delayed only within the time range in which the precharge clock φ can rise, and this time is the minimum value of the precharge time t N (2p '
On the order of m 1 n, it is difficult to obtain a sufficient "data window" period.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is possible to widen the data window to the minimum value of the cycle time necessary for the circuit, thereby fully demonstrating the high speed by adopting the nibble mode function. The object of the present invention is to provide a data output circuit for a dynamic memory that can perform the following functions.

[Summary of the invention]

In other words, the main point is D, which is a 4-bit latch data transfer node that secures 4-bit data in nibble mode.
Depending on the data of the O, v51 pair, one of the V! is 'i;, and connect all the other output parts to the signal to be driven.
A circuit is provided for data output of the o line pair. Then, until the data from the 4-bit latch is output to the Do line pair, the output section outputs the same data as the data output to the Do line pair in the previous cycle.
New data from Bitstratch.

By outputting to the wire pair and resetting, there is no reset when the output circuit V1.7'' is recharged.
The main feature is that it can be operated even on a machine that does not have one, and the data for the next cycle can be spread out just before it is output.

[Embodiments of the invention]

Hereinafter, an embodiment of the present invention will be explained in detail with reference to the circuit diagram shown in FIG. 7, in which the same parts as in FIG. 5 are given the same reference numerals. That is, MnS-FET1.

2.3 between each series connection point and MnS-FET 4,
MnS-FETs 2J and 22 are inserted between the MnS-FETs 27 and 22, and a date clock φg is commonly applied to each dart of the MnS-FETs 27 and 22. Also, MnS
- Series connection point of FET2 and 4 and MnS -FET
22.

A MnS-FET is connected between the series connection point of 5 and the power supply vsS.
23.24 and this MnS-FET2
,? , 24 darts are given a common precharge clock φ, ll-. Furthermore, nodes Nl, N2 and Mn
MnS between the dates of 4 and 5
- FET25.26 is inserted, and the MO8-FET 25
, 26 are given a clock ψ. The above M
O3-FET 4, 5 fast node N5 on each date
.

MnS-FET 27 between N6 and power supply V8S,
28, and the MO3-FETs 27, 28 (
A clock ψnY is given to the note D'f''-N1.

MOS-FET 29 between N2 and electric aXVs
, 30 are inserted, and the MO8-FETs 29 and 30 are connected to the MOS through nodes N7 and N8, respectively.
-FET4.21 and MOS-FET5,22
connected to each series connection point.

For example, if the configuration is as shown in the timing chart shown in Fig. 2, RAS falls and CAS falls to v.
When precharging TH, the precharge clock ψ is at a level 1 which is the power supply voltage vDD plus the threshold voltage VT of the MOS-FET (DD+v7) or higher, and the clocks ψ and ψ8' are at the level of the power supply VDD. Therefore, in FIG. 7, DO cat vs. Do, MOS
-FET 1, 2, ? is on, so the VD
D is charged. Each node other than the DO line pair has a MOS-FET whose dart input is one of the clock ψP and ψ8°ψ8', and is connected to the ground potential VSS. Therefore the output is 0output
is disconnected from any of the power supplies VDD and IV8S.

When the clock falls here, the clock ψ2. ψ8゜ψ8' falls, MOS-FET 1, 2, 3, 12
°.

13.23, 24.27.2FI are turned off and the DO line pair becomes a floating vDD level.

All nodes other than the OdaDO line pair are at floating V8s level. Then, data is output from the 4-bit latch to the DO line pair, one of which is connected to V88% and the other to VDD. At this time, the clock ψg rises to VP, and then the clock ψ rises to VDD. Here, depending on the output of the 4-bit latch, the voltage on the DO side is VDD, DO
Assuming that it is connected to the side capacitor vss, MOS-FgT
21 and 22 are turned on, and the node N7 is connected to Do via the switch element, ie, MOS-P'ET 21, and changes to the DD level.
, that is, at the vs8 level. Then, by changing the node N7 to the vDD level, the MOS
- FET 29 is turned on and node N.

For example, it is connected to VSS via a MOS-FET 29.

Also, the level of node N7 is given to /-)'N4 via MOS-FET 7, and its l/h/l/f VD
D-V.

, turns on transistor 9, and sets node N2 to ψ. Connect to U. After this ψ. When U rises to VP, node N4 becomes connected to the gate of MOS-FET 9 and ψ. u
By coupling with t, MOS-FE for Maria
Lift linode N2 to the level of vP to be T 7
The level becomes 1dVp. At this time, MOS-l”ET 2
6 Since it is on, the node is at the NeuvDD-vT level. Level changes at these nodes cause the MOS
-dot ETs 5, 10, and 14 are turned on. And I~
When 4O8-FET 5 is turned on, node N8, which was connected to v8s by I, is connected to v8s. When MOS-FET lO is turned on, MOS-F
Node Nl connected to “ss” via ET 29
k and further connected to Vss.

Further, the MOS-FET 14 has a dirt level of vp level, and is connected to the output (Output e Vy)p VC. Then, the data of the Do line pair is output from the output 0output. After the data is output, the clock ψ falls to vss after a while, and the MOS-FET
21 and 22 are turned on, and node N7 is disconnected from Do and turned off.

It becomes a rotating vDD level, and node N8 is disconnected from I and connected to vs8 only by MOS-FET 5. At this time, the DO line pair is disconnected from the output of the 4-bit latch and becomes a floating level.

Then, when the reed rises, the bite clock ψ1 rises to vP υ
, if the clock ψ is Vl! Falling at 8. The MOS-FETs 1, 2, and 3 are activated by the rising edge of the clock ψ2.

23.24 turns on. and MOS-FET 1
.

2.3, the Do line pair is connected to VDD and charged. MOS-FET 23 is set to node Ny'eVH level, MOS-FET 29 f is turned off, and node N4 is set to MOS-FET 7' (through 5
level and turn off MOS-FET 9. When the clock ψ falls, the MOS-FET 25
, 26 are turned off, disconnecting the node N5 from the node Nl and disconnecting the node N6 from the node N2, respectively, to a floating level. At this time, node N2 is set to floating vP level, and node N1 is set to MOS-FE.
It will be connected to vs8 only by T l O. After this, the clock ψ rises near vD, and the clock ψ. U, fall to bav8B. When Kuro and Riψ stand up,
MOS-FETs 27 and 28 turn on, and node N5
, N6 are connected to VssK, and the potential of the note 9N6, which was at VDD VT, is set to the vs8 level. For this reason, M.O.
S-FET 5 fi off, Note 6N8 MOS
- V8sK connected by FET 24 only.

In addition, the clock ψ. Even if U falls, Δ40S -FE
T 9 id is off, so node N2? Stay at VP level. Also, if the charge time TNcP is designed to be a minimum cycle close to the minimum allowable value TNCP min, CAS falls before clock ψ8' rises, and in the end, clock ψ,' does not rise. l1os
-FET 12. Js remains off. Therefore, the node N2 is still at the VP level even when CAS falls, the MOS-FET 14 is on, and the booter output circuit continues to output data. Then, when CAS falls in the next cycle while data is still being output, clock 2. ψR11-1: Falling, MOS-FET 1
, 2 , 3 , 23 , 24 .

27 and 28 are turned off, and the DO line pair becomes a floating VDD level. No PN again.

N8, N5, and N6 become floating v8s levels. Thereafter, data is output from the 4-bit latch to the DO line pair, and one of the Do line pairs is connected to VDD% and the other to vs8. At this time, the clock ψgFiVP level is reached, and then the clock ψ rises to VDD. The subsequent operation depends on the data on the DO line pair.

1) When Do is connected to VDD + DO is connected to Vss.

The main operation is the same as the first cycle, but /-doN2
There is also a difference because it is a floating VP level. In other words, when the clock ψ rises, the MO
S-FET'21f to the node NyUVH) level.

This turns on the MOS-FETs 29 and 9.

Node N1 is connected to ``ss'' by MOS-FET 29, and node N2 is connected to ψ. by MOS-FET 9. Since ψ.ut is at the VSS level, the node 9N20 level changes to VSS and the MOS
-FET 7θ, 14 is turned off. At this moment, the output is 0.
output is disconnected from VDD. After a short time,
φ. u t 7"'"P rises to node N2? in the same way as in the previous cycle. Change to VP level and M again
Turn on OS-FET 14 and output Output
The data output circuit connected to u VDD outputs the data of the Do line pair.

2) Do is Vss r DO is V. When connected to 0.

When the clock ψ rises, MOS-FET 2 J
.

22 is turned on, no PN8 easily changes to vDD. Node N7 is connected to vss via DO. When the node N8 changes to the VDD level, the MOS-FET 30 is turned on, and the node N2 changes to the Vp level, or v6s. This change causes the MOS
-FET14 is turned off and the output is 0output f VD
It is disconnected from D, and the output of the data of the previous cycle is stopped.

The change in PN8 causes node N3 to change to the level of VDD-vT. Turn on. and MOS-FET 10 U/-t,,N
2 changes to the Vs8 level, 9 turns off, and the node N1 becomes φ via the MOS-FET 8. , is connected to. At this point, the data output circuit is set to IJ and DO
The line pair data output is set.

Clock φ. , rises to the vP level, the node N3 and MOS-FET 8 perform the same operations as the node PN4 and MOS-F'ET9 in the previous cycle, and the node 9N1 changes to the VP level. From then on, M'O8-F
ET 14, left and right MOS in Figure 7 except for l 5
-'If the FET and node are swapped, the operation will be exactly the same as last time. In other words, when the node N changes to the VP level, the MOS-F'ET15 turns on and the output becomes 0utpu.
t is connected to vss and outputs the data of the DO line pair.

In subsequent cycles, the above-described operations are repeated in the same way.

Then, when CAS rises in the last cycle of the nibble mode operation, there is sufficient precharge time this time, and the clock ψ8' rises to vDD. ,13
Turn on node N1 and ''' N 2 k' VB
Connect B K, turn off MOS-FET14.15, and output 0output'zVDD and v.

The chair force is also cut 1'j [fj l,, data output'ff stops.

In such a case, for example, as shown in the timing chart shown in Fig. 8, the nibble mode operation is performed at the minimum falling cycle tNcrrIin of CAS following KRAS, and the precharge time is jN(p mIn). In this figure 8, 0output l is the 5th
This shows the operation of the conventional output circuit shown in the figure, in which the data output circuit is reset by the precharge system clock ψl.

If this clock ψl does not rise, the data output circuit will not be able to output data without being reset, so the data window" must be made considerably smaller than tNcnlIn.

On the other hand, 0output 2 indicates the data output when a data output circuit as shown in FIG. 7 is used, and the clock ψ8' is a precharge system clock that resets the entire circuit. Time t. In order to make ffe sufficiently large, the rise of clock ψ8' is delayed by a large amount from the rise of 'iCAS, so that it cannot rise during the minimum nibble mode cycle. However, since the data output circuit is reset and set according to the level of the DOi pair, the circuit operates abnormally, and
The data window" can be very easily used, extending as wide as the minimum cycle tNcmln.

Although the circuit of the above embodiment has been described using a MOS-FET as an example, it goes without saying that other so-called transistors such as field effect transistors and bipolar trannostars may be used as appropriate.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to widen the data window to about the minimum cycle tN (Hmin), thereby making it possible to fully utilize the cycle avoidance and speed in the nibble mode. data output circuits can be provided.

4.Darkness of the drawings [9.Bright Figure 1 is a block diagram that fully explains the nibble mode functions, Figure 2 is a waveform diagram that fully explains the operation of the read cycle in nibble mode, and Figure 3 shows the trough in nibble mode. A waveform diagram explaining the operation of the cycle, Figure 4 is a data window in the read cycle?A waveform diagram explaining the operation of the cycle, Figure 5
The figure is a circuit diagram showing an example of a conventional data output circuit, No. 6 is a waveform diagram explaining the operation of each data output circuit, and No. 7 is a waveform diagram explaining the operation of each data output circuit.
The figure is a circuit diagram showing one embodiment of the present invention, and FIG.
6 is a waveform chart showing the operation of the circuit diagram shown in FIG. 5 in comparison with the conventional example shown in FIG. 5. FIG.

1 to 30-M2S-FET5Do, DO...Data transfer node, 21.22...MOS-FET (
switch element), N1 to N8...node, φ. .・
...Output, drive signal.

Applicant's agent: Patent attorney Takehiko Suzue Figure 5 Figure 6 Figure 7 V[)D

Claims (1)

[Claims] In a data output section that outputs the memory contents of a memory cell, a pair of data transfer nodes to which data read from the memory cell is transferred as a potential change, and a pair of intermediate nodes connected to each data transfer node via a switch element. node, a node that serves as the gate input of the load transistor inserted between the data output node and the source, and a node that serves as the date input of the drive transistor inserted between the data output node and ground. , a transistor inserted between the node serving as the r-to input of the load transistor and the ground and having one of the intermediate nodes as a date input, and a node serving as the date input of the load transistor, and an output and a drive signal provided. A transistor connected between the node and the other node '1r-) input of the intermediate node, and a transistor connected between the node serving as the gate input of the drive transistor and ground and the other node of the intermediate node as the dirt input. and a transistor connected between a node serving as a dart input of the drive transistor and a node to which the output drive signal 7 is applied, and serving as an input to one node kf-) of the intermediate nodes, Depending on the potential level of the transfer node, one of the node serving as the gate input of the load transistor and the node serving as the r-) input of the drive transistor is electrically connected to ground, and the other is electrically connected to a node to which an output drive signal is applied. A data output circuit of a dynamic memory with ft% characteristics.