JPS59205659A - Data storage and display device - Google Patents

Abstract

PURPOSE:To obtain a data memory display device which excels in portability by separating a central processing part including a display panel from a keyboard. CONSTITUTION:A data input device is used to constitute an external device, and a device main body B is put on a magnetic transfer part F on the upper surface side of the input device. Then data are sent successively to an RAM12 within the main body B with operation of a keyboard E. When storage of data is over, the main body B is detached from the data input device and then loaded to a wrist belt. Then a button switch D of the device is operated to deliver the control signal to a CPU10 from a switch control circuit 18. Thus the function of an electronic memo mode is obtained. Thus the CPU10 delivers the signal to the RAM12 via an address data bus to send the stored data to an I/O bus 15 and displays the data equivalent to a screen to a display panel 17 via a display controller 14. In addition, the function of an ordinary digital timepiece is also secured with operation of the switch D.

Description

[Detailed description of the invention] The present invention relates to a data display storage device that is convenient to carry.

In recent years, with remarkable progress in semiconductor technology, hand-belt type computers that can execute full-scale programs have been put into practical use.

By the way, such small-sized computers have attracted attention for their ability to store large amounts of data, and are being used not only for processing information but also as electronic memos.

However, conventional calculators are constructed by integrating a central processing unit including a display panel and a keyboard, so
There was the inconvenience of having to carry functions that are not required depending on the purpose of use.

In view of these circumstances, the present invention makes it possible to separate the central processing unit including the display panel from the keyboard.
The purpose is to provide a data display storage device that is convenient to carry.

Therefore, details of the present invention will be explained below based on illustrated embodiments.

FIG. 1 shows an external appearance of a device showing an embodiment of the present invention.The device main body B is configured to be attached to the wrist by a bell A, and has a fine liquid crystal display panel in the center of two sides. Cf/
lf inset, a button switch height display panel C is inset in the lower part, and a button switch D is provided in the lower part.

FIG. 2 is a cross-sectional view showing the structure of the main body of the device, and the reference numeral 1 in the figure is a case in which a housing is formed by fitting a glass plate 2 on the top surface and a back cover 3 on the bottom surface, which is close to the glass plate 2. A circuit board 6 on which a liquid crystal display panel 4 is arranged and a signal processing circuit connected to this panel 4 via a connector 5.
A battery 7 for supplying power is housed between the circuit board 6 and the back cover 3, and a transmitting/receiving coil 8 surrounds the outer periphery of the battery 7 to exchange data with external equipment.
It is configured by arranging.

FIG. 3 is a block diagram of a circuit showing one embodiment of the above-mentioned signal processing circuit, and reference numeral 9 in the figure is a transmitting/receiving circuit that sends and receives data by magnetic transfer with an external device; As shown in the figure, there is an interface unit 9a that sends and receives data using magnetic lines of force as a medium, and a serial signal received by the interface unit 9a that is converted into a parallel signal and output to a data bus, and a data Serial-to-parallel conversion circuit 9 outputs to parallel 19a from bus
b, and the parity of the parallel signal output from this conversion circuit 9b is detected and the central processing unit (hereinafter, CP
A parity check addition circuit 9C outputs an error signal to the converter circuit 10 (referred to as U) and adds a parity bit to the parallel signal input from the data bus to the conversion circuit 9b.
and an interrupt generation circuit 9d for detecting the interrupt signal -53 from the signal output to the data bus from the conversion circuit 9b and interrupting the CPU, and each circuit is controlled by a transmission/reception control signal from the CPU. The configuration is such that the transmission mode and reception mode are switched in response to this. Returning again to FIG. 3, 10 is the aforementioned CPU, which is connected via an address data bus 11 to a RAM 12 that stores utility programs and data, and a ROM 13 that stores a control program. 14
is l107.7□54. Connect 6 tables 7, yaw, a,. The data read from the RAM 12 via 1o←10 is output to the liquid crystal display panel 17 via the display driver 16. 18 is a switch control circuit 1, which sends a control signal to the CPU10 via the I10 bus 15 by operating the button switch D, and cyclically switches the functions of the device as shown in FIG. It is configured to select each mode: memo mode, alarm mode, stopwatch mode, and time correction mode. Note that reference numeral 19 in the figure indicates a register connected to CPU10.

FIG. 6 is a block diagram of a circuit showing an embodiment of the above-mentioned interface section, which includes an AND gate 20 to which transmission data consisting of HL signals and a clock signal are input;
A transmission system consisting of two transistors that turns ON-OFF by No. 43 and outputs a signal to the transmitting/receiving coil 8.
and a pulse shaping circuit 22 that shapes the signal received by the transmitting/receiving coil 8 into a pulse signal, and a D type that inputs the signal from this to a reset terminal via an inverter 23 and demodulates it into an HL signal synchronized with a clock signal. It consists of a receiving system consisting of flip-flops 25 and 26. Note that the symbols T1, T2, and T3 in the figure indicate transistors for switching between transmission and reception, respectively.

Next, the operation of the apparatus configured as described above will be explained.

FIG. 7 is an external view showing an example of a data input device constituting an external device, in which a keyboard E and a magnetic transfer unit F are arranged on the top surface, and data input from the keyboard E is transferred to the above-mentioned transmitting/receiving circuit ( It is configured to perform magnetic transfer using exactly the same circuit configuration as in Figure 6).

Place the device main body B on the magnetic transfer section F of the data input device; then input the control character ""C2" from the +-board E, which is converted into a serial signal by the transmission/reception circuit of the data input device (8th Figure B), the magnetic flux from the magnetic transfer section becomes device B.
(Fig. 8C). This magnetic flux is detected by the transmitting/receiving coil 8 of the device and converted into an electrical signal (
FIG. 9A) is shaped into a signal synchronized with the clock by the pulse shaping circuit 22 (FIG. 9B), and the flip-flop 2
6 is demodulated into a space mark signal (E). This signal is converted into a parallel signal by the serial-parallel converter 9b and inputted to the CPU10 via the data bus 15. By inputting the control character "'C2"', CPU10 transfers the data transmitted thereafter to RAM12.
It determines that it is in the data storage mode to store data in the
K'' is sent to the data input device via the transmitter/receiver circuit 9.

At this stage, the data input device sends out the start address of the data to be stored in the RAM 12 to set the storage address, and then the data to be stored are sent out one after another. When data transmission is completed, a transmission end control character "XMT" is transmitted from the data input device to the device. CPU10 sends the message transmission end control character "'
It is determined whether or not there is an error in the reception of the series of data from C2"° to ""XMT'" sent from the data input device by reception of "MT", and if there is no error, an affirmative character "A" is output. CK” to the data input device,
Store the data in RAM12. In addition, if there is an error in data reception, a negative response character “N A K
” to request data transmission again.

When data storage is completed in this way, the device main body B is removed from the data input device and worn on the wrist. If the button switch D of the device is operated at this stage, a control signal is output from the switch control circuit 18 to the CPU10, and the electronic memo mode is set. As a result, the CPU10 outputs a signal to the RAM12 via the address data bus, outputs the stored data to the I10 bus 15, and displays one screen worth of data on the liquid crystal display panel 17 via the display controller 14. . At this time, when button switch D is pressed, the data stored in the RAM 12 is input to the LCD panel 17 one screen at a time, and the contents are updated one after another and new data is displayed, allowing the user to select the desired information. be able to.

Furthermore, by operating the button switch D to change to the clock mode, the CPU 10 generates a clock signal, functions as a normal digital clock, and displays the time on the liquid crystal display panel.

As explained above, according to the present invention, the central processing unit,
Since the data storage means, display means, and data transmission/reception means are integrated, and data input is performed from a separate keyboard, the main body of the device can be made compact and lightweight, making data storage convenient for carrying. A display device can be realized.

[Brief explanation of the drawing]

Figure S1 is an external view of the device showing one embodiment of the present invention;
The figure is a sectional view showing the internal structure of the above device, FIG. 3 is a circuit block diagram showing one embodiment of the signal processing circuit in the above device, and FIG. 4 is a circuit diagram showing one embodiment of the transmitting/receiving circuit. Block diagram: FIG. 5 is an explanatory diagram showing mode switching of the above device; FIG. 6 is a block diagram of a circuit showing an embodiment of the transmitting/receiving interface; FIG. 7 is an illustration of inputting data to the above device. Figures 8 and 9 are waveform diagrams illustrating the operation of the above circuit, respectively. 1... Case 2... Glass plate 3... Back cover 4... Liquid crystal display panel 5... Connector 6... Circuit board 7... Battery D...・・・
Applicant: Daini Seidokusha Co., Ltd. Agent: Patent attorney: Kei Nishikawa, Katsuhiko Kimura 5 Collection of illustrations Otsu Ward 7 Ougi 3 Diagram (β) Send data Ougi I CF) Send Il! Continuing from page 1 of 2 I51 0 Inventor Jun Tsubouchi - 6-31-1 Kameido, Koto-ku, Tokyo 395 Inside Daini Seidamasha Co., Ltd.

Claims (1)

[Claims] a central processing means controlled by a control program; a transmitting/receiving means for transmitting and receiving data via a transmission medium; a storage means for writing and reading data from the means under control of the central processing means; a display means for displaying data stored in the storage means; a switch control means for sending a control signal to the central processing means to switch data in the storage means; and a power supply means for driving these means; A data storage/display device comprising each of the above-mentioned means housed in a housing in such a manner that the display means can be viewed from above.