JPS5920305U - sequence controller - Google Patents

sequence controller

Info

Publication number
JPS5920305U
JPS5920305U JP11583282U JP11583282U JPS5920305U JP S5920305 U JPS5920305 U JP S5920305U JP 11583282 U JP11583282 U JP 11583282U JP 11583282 U JP11583282 U JP 11583282U JP S5920305 U JPS5920305 U JP S5920305U
Authority
JP
Japan
Prior art keywords
unit
sequence controller
main body
terminal portion
reception terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11583282U
Other languages
Japanese (ja)
Inventor
藤田　貞三
Original Assignee
和泉電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 和泉電気株式会社 filed Critical 和泉電気株式会社
Priority to JP11583282U priority Critical patent/JPS5920305U/en
Publication of JPS5920305U publication Critical patent/JPS5920305U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図面はこの考案の実施例を示し、第１図は本体と各ユニ
ットを集設して構成したシーケンスコントローラの平面
図、第２図はＩ１０ユニットの接続結合を示す要部断面
図である。 １・・・ＣＰＵ本体、２・・・ＰＳユニット、３・・・
Ｉ１０ユニット、６・・・受栓端子、７・・・挿栓端子
。The drawings show an embodiment of this invention, and FIG. 1 is a plan view of a sequence controller constructed by assembling the main body and each unit, and FIG. 2 is a sectional view of a main part showing the connection and combination of the I10 unit. 1...CPU main body, 2...PS unit, 3...
I10 unit, 6... plug terminal, 7... plug terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＣＰＵ本体に対して電源ユニット及び入出カニニットを
互いに結合できるようにそれぞれ独立して構成するとと
もに、前記ＣＰＵ本体及び各ユニット間の結合は、並列
して集設する前・後部側面にそれぞれ信号接続用挿・受
栓端子部を設けて各ユニットの集設取付時に前記挿・受
栓端子部の結合により信号回路が接続できるように構成
したことを特徴とするシーケンスコントローラ。The power supply unit and the input/output crab unit are each configured independently so that they can be connected to the CPU main body, and the connections between the CPU main body and each unit are provided for signal connections on the front and rear sides, which are arranged in parallel. 1. A sequence controller characterized in that an insertion/reception terminal portion is provided so that a signal circuit can be connected by coupling the insertion/reception terminal portion when each unit is assembled and mounted.
JP11583282U 1982-07-29 1982-07-29 sequence controller Pending JPS5920305U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11583282U JPS5920305U (en) 1982-07-29 1982-07-29 sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11583282U JPS5920305U (en) 1982-07-29 1982-07-29 sequence controller

Publications (1)

Publication Number Publication Date
JPS5920305U true JPS5920305U (en) 1984-02-07

Family

ID=30267249

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11583282U Pending JPS5920305U (en) 1982-07-29 1982-07-29 sequence controller

Country Status (1)

Country Link
JP (1) JPS5920305U (en)

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