JPS59201436A - Measurement of density distribution of semiconductor carrier - Google Patents

Measurement of density distribution of semiconductor carrier

Info

Publication number
JPS59201436A
JPS59201436A JP7514383A JP7514383A JPS59201436A JP S59201436 A JPS59201436 A JP S59201436A JP 7514383 A JP7514383 A JP 7514383A JP 7514383 A JP7514383 A JP 7514383A JP S59201436 A JPS59201436 A JP S59201436A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
sample
carrier density
substrate
density distribution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7514383A
Other languages
Japanese (ja)
Inventor
Hisao Hayashi
久雄 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP7514383A priority Critical patent/JPS59201436A/en
Publication of JPS59201436A publication Critical patent/JPS59201436A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Abstract

PURPOSE:To realize a simple, quick and highly accurate measurement by a method wherein, when a surface of a semiconductor substrate is removed in stages and the sheet resistance of the surface is measured at every stage to know the carrier density distribution along the depth direction of the substrate, the substrate and a monitor sample are put into a same processing chamber and their surfaces are subjected to dry etching at the same time and each sheet resistance is measured. CONSTITUTION:A rotary shaft 3, protruded from a driving mechanism 8, penetrates into a cylindrical processing chamber 1 and a sample table 5 is provided to the tip of the shaft 3 through an attachment member 4. On one end part of this sample table 5, a semiconductor substrate 6 to be measured and a monitor sample 7 are put side by side. The substrate 6 and the sample 7 are held between an electrode 9 and a facing electrode 10 and the gas from a plasma producing gas source 13 is introduced between two electrodes 9, 10 and the substrate 6 and a sample 7 are subjected to plasma etching simultaneously. This operation is repeated and at every operation the sample table 5 is rotated to make the substrate 6 and the sample 7 touch a probe of a resistance measuring instrument 14. The sheet resistance values are displayed by a diagram in an output equipment 17 through a processor 15 and the signal is also supplied to a memory 16 in which the concerning equations are memorized.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体基板の深さ方向のキャリア密度分布の
測定方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for measuring carrier density distribution in the depth direction of a semiconductor substrate.

背景技術とその問題点 従来、この種の測定方法としては、ホール効果を測定す
る方法、pn接合の容量変化を測定する方法、拡がり抵
抗を測定する方法等がある。しかし、これらの方法はい
ずれも簡便性、精度、測定可能な不純物濃度の範囲が狭
いという点で実用的でないという欠点を有する。
BACKGROUND ART AND PROBLEMS Conventionally, this type of measurement method includes a method of measuring the Hall effect, a method of measuring capacitance change of a pn junction, a method of measuring spreading resistance, and the like. However, all of these methods have drawbacks in that they are impractical due to their simplicity, accuracy, and narrow range of measurable impurity concentrations.

より改善された測定方法として、陽極酸化と化学エツチ
ングとを組み合わせてキャリア密度分布を測定する一連
の工程をマイクロ・コンピュータを用いて自動的に行う
方法がある。この方法によれば、陽極酸化法により半導
体基板の表面に薄い酸化膜を形成し、次に化学エツチン
グにより酸化膜と共に基板表面の微小量を除去し、四探
針法による基板表面pシート抵抗ρSを測定する工程を
繰り返して行うことによって、これらの測定値と半導体
基板の上記微小のエツチング量とから半導体基板の深さ
方向の比抵抗変化を順次求め、これらの比抵抗変化から
キャリア密度分布を計算によって求めるようにしている
As a more improved measurement method, there is a method in which a microcomputer is used to automatically perform a series of steps for measuring carrier density distribution by combining anodic oxidation and chemical etching. According to this method, a thin oxide film is formed on the surface of the semiconductor substrate by anodic oxidation, then a minute amount of the substrate surface is removed together with the oxide film by chemical etching, and the p-sheet resistance ρS of the substrate surface is formed by the four-probe method. By repeating the process of measuring , the resistivity changes in the depth direction of the semiconductor substrate are sequentially determined from these measured values and the minute etching amount of the semiconductor substrate, and the carrier density distribution is determined from these resistivity changes. I try to find it by calculation.

しかしながら、この測定方法においては半導体基板の実
際のエツチング量を測定せずに、化学エツチングにより
除去される酸化膜及び半導体基板の厚さの間の既知の関
係式からエンチング量を得るようにしているため、基板
表面からの深さ精度が十分でないという欠点がある。ま
た、この測定方法は陽極酸化さ化学エツチングを用いて
いるため、洗浄、乾燥等の処理が必要である。従って、
これらの処理を行うための設備が必要であるばかりでな
く、工程、屏多くなるので測定に時間がかかるという欠
点を有する。さらに、エツチング液としてフン酸等の化
学薬品を用いるため公害の点からも好ましくない。
However, in this measurement method, the actual etching amount of the semiconductor substrate is not measured, but the etching amount is obtained from a known relational expression between the oxide film removed by chemical etching and the thickness of the semiconductor substrate. Therefore, there is a drawback that the depth accuracy from the substrate surface is not sufficient. Furthermore, since this measurement method uses anodic oxidation and chemical etching, treatments such as cleaning and drying are required. Therefore,
Not only does it require equipment to perform these treatments, but it also requires a large number of steps, so it has the drawback that it takes time to measure. Furthermore, since a chemical agent such as hydronic acid is used as an etching solution, it is not preferable from the viewpoint of pollution.

発明の目的 本発明は、上述の問題にかんがみ、半導体基板の深さ方
向のキャリア密度分布を簡易迅速にしかも高精度で測定
することのできるキャリア密度分布の測定方法を提供す
ることを目的とするものである。
Purpose of the Invention In view of the above-mentioned problems, an object of the present invention is to provide a carrier density distribution measuring method that can easily and quickly measure the carrier density distribution in the depth direction of a semiconductor substrate with high precision. It is something.

発明の概要 本発明による半導体基板の深さ方向のキャリア密度分布
の測定方法は、半導体基板表面を段階的に除去しその都
度前記半導体基板表面のシート抵抗を測定することによ
って前記半導体基板の深さ方向のキャリア密度分布を測
定する方法において、(a)、前記半導体基板とモニタ
用試料とを同一処理室内に配して前記半導体基板表面と
前記モニタ用試料表面とを同時にドライエツチングする
工程、(b) %前記処理室内において@2半導体基板
表面と前記モニタ用試料表面のそれぞれのシート抵抗を
測定する工程、(C)、前記モニタ用試料表面のシート
抵抗の前記測定値から前記半導体基板表面のエツチング
量を得、前記半導体基板表面の前記エツチング量と前記
半導体基板表面のシート抵抗の前記測定値とから前記半
導体基板表面からの前記エツチング量に相幽する深さに
おける前記半導体基板のキャリア密度を得る工程をそれ
ぞれ具備し、上記(a)〜(c)の工程を順次繰り返し
て行うようにしている。このようにすることによって、
半導体基板の深さ方向のキャリア密度分布を簡易迅速に
しかも高精度で測定することができる。
Summary of the Invention A method for measuring the carrier density distribution in the depth direction of a semiconductor substrate according to the present invention is to remove the surface of the semiconductor substrate stepwise and measure the sheet resistance of the surface of the semiconductor substrate each time. In the method of measuring the carrier density distribution in the direction, (a) the step of arranging the semiconductor substrate and the monitor sample in the same processing chamber and dry etching the semiconductor substrate surface and the monitor sample surface simultaneously; b) measuring the sheet resistance of the @2 semiconductor substrate surface and the monitor sample surface in the processing chamber; (C) determining the sheet resistance of the semiconductor substrate surface from the measured value of the sheet resistance of the monitor sample surface; Obtain the amount of etching, and calculate the carrier density of the semiconductor substrate at a depth that corresponds to the amount of etching from the surface of the semiconductor substrate from the amount of etching on the surface of the semiconductor substrate and the measured value of the sheet resistance of the surface of the semiconductor substrate. The above steps (a) to (c) are sequentially repeated. By doing this,
The carrier density distribution in the depth direction of a semiconductor substrate can be measured simply, quickly, and with high precision.

実施例 以下本発明による半導体基板の深さ方向のキャリア密度
分布の測定方法の一実施例(こつき図面を参照しながら
説明する。
EXAMPLE Hereinafter, an example of a method for measuring the carrier density distribution in the depth direction of a semiconductor substrate according to the present invention will be described with reference to the drawings.

第1図は本実施例を説明するためのキャリア密度分布測
定装置の概略的な構成図である。第1図において、円筒
形状の処理室(1)は真空排気系(2)によって高真空
に排気されている。回転軸(3)の一端には取付は部材
(4)を介して試料台(5)が取り付けられている。こ
の試料台(5)上には、キャリア密度分布を測定すべき
半導体基板(6)及びエツチングのモニタ用試料(7)
が互いに隣接して載置されている。
FIG. 1 is a schematic configuration diagram of a carrier density distribution measuring device for explaining this embodiment. In FIG. 1, a cylindrical processing chamber (1) is evacuated to a high vacuum by a vacuum evacuation system (2). A sample stage (5) is attached to one end of the rotating shaft (3) via a mounting member (4). On this sample stage (5) are a semiconductor substrate (6) whose carrier density distribution is to be measured and a sample for monitoring etching (7).
are placed adjacent to each other.

試料台(5)は処理室(1)の外部にある駆動機構(8
)によって回転軸(3)の回りに回転可能である。処理
室(1)の内部には電極(9)と対向電極(10)が設
置されており、電極(9)には処理室(1)の外部にお
いて高周波電源t1υが接続されている。また、電極(
9)は温度制御器(1カにも接続されている。処理室(
1)番こ−は電極(9)及び対向電極(lO)の近傍に
おいて、プラズマ発生用のガス源(131が接続されて
いる。
The sample stage (5) is connected to a drive mechanism (8) located outside the processing chamber (1).
) around the rotation axis (3). An electrode (9) and a counter electrode (10) are installed inside the processing chamber (1), and a high frequency power source t1υ is connected to the electrode (9) outside the processing chamber (1). In addition, the electrode (
9) is also connected to the temperature controller (1).The processing chamber (
1) A gas source (131) for plasma generation is connected in the vicinity of the electrode (9) and the counter electrode (lO).

処理室(1)内部の回転軸(3)に関して電極(9)及
び対向電極(10)の反対側の部位には、四探針法によ
るρS測定装置(1@が設置されている。このρS測定
装装置には、処理室(1)の外部において演算器([ω
、メモリ叫及び出力装置(17)が接続されている。
A ρS measurement device (1@) using a four-probe method is installed at a location on the opposite side of the electrode (9) and counter electrode (10) with respect to the rotation axis (3) inside the processing chamber (1). The measuring device includes a computing unit ([ω
, memory and output device (17) are connected.

次に上述の如くに構成された第1図に示すキャリア密度
分布測定装置を参照して本実施例による半導体基板の深
さ方向のキャリア密度分布の測定方法につき説明する。
Next, a method for measuring the carrier density distribution in the depth direction of a semiconductor substrate according to this embodiment will be explained with reference to the carrier density distribution measuring apparatus shown in FIG. 1 configured as described above.

まず、キャリア密度分布を測定すべき半導体基板(6)
及びエツチングのモニタ用試料(7)を試料台(5)上
に互いに隣接して載置して所定の位置にそれぞれ配置し
た後、駆動機構(8)により回転軸(3)を回転させて
試料台(5)を移動させて電極(9)と対向電極(10
)との間に位置させる。次に半導体基板(6)及びモニ
タ用試料(7)をエツチングするためのガスをガス源(
13)から処理室(1)内に導入する。処理室(1)の
真空度が所定の値になるまでガスを導入してから真空度
が安定した時点で、高周波電源tll)により電極(9
)に高周波を印加する。このとき電極(9)と対向電極
uo)との間の空間において上記ガスが放電を開′始し
て活性ガスイオンが発生する。この活性ガスイオンは電
極(9)及び対向電極(lO)の近傍にそれぞ1′1.
生ずる垂直な電界に沿って半導体基板(6)及びモニタ
用試料(7)のそれぞれの表面に入射する。これにより
半導体基板(6)とモニタ用試料(力の両者の深さ方向
にRIEが同時に進行する。
First, the semiconductor substrate (6) whose carrier density distribution is to be measured
After the specimens (7) for monitoring etching are placed adjacent to each other on the specimen stage (5) and placed at predetermined positions, the drive mechanism (8) rotates the rotation shaft (3) to remove the specimens. Move the stand (5) to connect the electrode (9) and the counter electrode (10).
). Next, a gas source (
13) into the processing chamber (1). Gas is introduced until the degree of vacuum in the processing chamber (1) reaches a predetermined value, and when the degree of vacuum becomes stable, the electrode (9
). At this time, the gas starts to discharge in the space between the electrode (9) and the counter electrode (uo), and active gas ions are generated. These active gas ions are located near the electrode (9) and the counter electrode (lO) at 1'1.
The generated vertical electric field is incident on the surfaces of the semiconductor substrate (6) and the monitoring sample (7), respectively. As a result, RIE progresses simultaneously in the depth direction of both the semiconductor substrate (6) and the monitoring sample (force).

所定の時間上記のエツチングを行った後、電極(9)に
対する高周波の印加を停止する。次に駆動機構(8)に
より回転軸(3)を回転させて試料台(5)をρS測定
装置側側に移動させる。この後ρS測定装置Hの探針を
下降させて半導体基板(6)の表面とモニタ用試料(7
)の表面のそれぞれのρBを順次測定する。
After performing the above etching for a predetermined period of time, the application of high frequency to the electrode (9) is stopped. Next, the rotating shaft (3) is rotated by the drive mechanism (8) to move the sample stage (5) toward the ρS measurement apparatus side. After this, the probe of the ρS measuring device H is lowered to touch the surface of the semiconductor substrate (6) and the monitor sample (7).
) is sequentially measured.

この場合、試料台(5)上の所定位置に配置されてG)
る半導体基板(6)及びモニタ用試料(力の何れか一方
の表面まで上記探針を下降させてそのρSを測定し、次
いでこれらの探針を一旦上昇させてから上記他方の表面
に対応した位置まで水平移動させ、次いで上記探針を上
記他方の表面まで下降させてそのρSを測定することが
できる。このρS測定が完了した時点で、駆動機構(8
)により回転軸(3)を回転させて試料台(5)を再び
移動させて電極(9)と対向電極α0)(11) との間に位置させる。次に高周波電源1より電極(9)
に高周波を印加して、半導体基板(6)及びモニタ用試
料(7)のそれぞれの表面を既述の如(にして同時にエ
ツチングする。このエツチングを所定時間行った後、電
極(9)に対する高周波の印加を停止し、次に駆動機構
(8)により回転軸(3)を回転させて試料台(5)を
再びρS測定装置0(イ)側に移動させた後、既述の如
くにして半導体基板(6)表面とモニタ用試料(力表面
のそれぞれのρSを測定する。以下同様にして、半導体
基板(6)表面及びモニタ用試料(力表面のそれぞれの
エツチングとρB測測定を繰り返す。
In this case, G) is placed at a predetermined position on the sample stage (5).
A semiconductor substrate (6) and a monitoring sample (the probes were lowered to one of the surfaces to measure the ρS, and then these probes were raised once and then the probes were moved to the other surface. position and then lower the probe to the other surface to measure its ρS. Once this ρS measurement is complete, the drive mechanism (8
) to rotate the rotating shaft (3) and move the sample stage (5) again to position it between the electrode (9) and the counter electrode α0) (11). Next, electrode (9) from high frequency power source 1
The surfaces of the semiconductor substrate (6) and the monitoring sample (7) are simultaneously etched as described above by applying high frequency waves to the electrodes (9). After stopping the application of , the rotating shaft (3) is rotated by the drive mechanism (8) to move the sample stage (5) again to the ρS measuring device 0 (A) side, and then as described above. Measure the ρS of the semiconductor substrate (6) surface and the monitoring sample (force surface).Etching and ρB measurement of the semiconductor substrate (6) surface and the monitor sample (force surface) are repeated in the same manner.

ρB測定装装置(イ)で測定された半導体基板(6)の
表面及びモニタ用試料(力の界面のそれぞれのρSのデ
ータは順次演算器け5)に送られる。なおメモリ(16
)には、モニタ用試料(力のエツチング量とρSの関係
及び半導体基板(6)とモニタ用試料(力のそれぞれの
エツチング量の関係をあらかじめ実験的に求め記憶させ
てある。また上記メモ!j a6)には、ρSの測定値
からキャリア密度を求めるための後述の関係式(【)σ
Dも予め記憶させ′Cある。従ってエツチング量及びρ
Sについて実験的に求めた上述の関係とρSの測定値か
らキャリア密度を求めるための上述の関係式と上述のρ
Sのデータとから、半導体基板(6)のエツチング量に
相当する深さにおけるキャリア密度を上記演算器けωに
おいて求めることができる。このキャリア密度の測定値
は、出力装置αηによって数値又はグラフ上の点、ある
いはこれらの両者として出力されてよい。
The surface of the semiconductor substrate (6) measured by the ρB measuring device (a) and the ρS data of the monitoring sample (the respective ρS data of the force interface are sequentially sent to the arithmetic unit 5). Note that memory (16
), the relationship between the etching amount of the force and ρS and the relationship between the etching amount of the semiconductor substrate (6) and the monitoring sample (the force) have been experimentally determined and memorized in advance. Also, note the above! j a6) contains the relational expression ([)σ
D is also stored in advance. Therefore, the etching amount and ρ
The above relational expression for determining the carrier density from the above relationship experimentally determined for S and the measured value of ρS and the above ρ
From the data of S, the carrier density at a depth corresponding to the amount of etching of the semiconductor substrate (6) can be determined using the arithmetic algorithm ω. This measured value of carrier density may be output as a numerical value, a point on a graph, or both by the output device αη.

上述の如<、RIKによるエツチング、ρS測定及びキ
ャリア密度の算出を複数回繰り返すことにより、半導体
基板(6)の深さ方向のキャリア密度分布を求めること
ができる。
As described above, by repeating etching by RIK, ρS measurement, and carrier density calculation multiple times, the carrier density distribution in the depth direction of the semiconductor substrate (6) can be determined.

次に半導体基板(6)の表面のρSの測冗値からこの半
導体基板(6)の深さ方向のキャリア密度分布を求める
ための方法につき詳細に説明する。
Next, a method for determining the carrier density distribution in the depth direction of the semiconductor substrate (6) from the redundant value of ρS on the surface of the semiconductor substrate (6) will be described in detail.

半導体基板(6)の初期の表面を原点さして深さ方向に
X軸の正の向きをとる。xiの深さにおけるρBの測定
値をρsiとする。ここにおいて、i=1゜2.3.−
   であり又xi+1〉xiである。
The initial surface of the semiconductor substrate (6) is set as the origin, and the positive direction of the X-axis is taken in the depth direction. Let ρsi be the measured value of ρB at a depth of xi. Here, i=1°2.3. −
and xi+1>xi.

xi≦X≦xi++ (xi→1−xi−△xi  と
する)の領域における半導体基板(6)の平均比抵抗を
ρi とすると、 訂−△xi / (1/ρsi −1/ρsi+1)(
I)と表される。一方、半導体基板(6)の比抵抗、キ
ャリア密度及び移動度をXの関数としてそれぞれρω、
n(→及びμ(x)で表すと、 ρに)=1/qす(ト)・n(2)       0と
辰される。ここにqは単位電荷である。μ(2)は一般
にはさらにn(→の関数でもあるが、キャリア密度が均
一であるとみなぜるような微小領域を深さ方向に考えれ
ば移動度は一定となるから、公知のIrvjnの曲絆よ
りρとnの開田を求めるこ七ができる。従って、上述の
(I)式により求めた肩 を(社)式のρに代入するこ
とによって、ρi に対応するキャリア密度niを求め
ることができる。このniをxi≦X≦zi−+1のど
の位1面のキャリア密度とするかについては任意性があ
るが、例えば()(i++ −xi)/2におけるキャ
リア密度とする方法がある。
If the average resistivity of the semiconductor substrate (6) in the region of xi≦X≦xi++ (xi → 1−xi−△xi) is ρi, then the following equation is obtained: correction−Δxi / (1/ρsi −1/ρsi+1)
I). On the other hand, the specific resistance, carrier density and mobility of the semiconductor substrate (6) are expressed as ρω, respectively as a function of X.
n (expressed as → and μ(x), ρ) = 1/qs(t)・n(2) 0. Here q is unit charge. Generally, μ(2) is also a function of n(→, but if we consider a micro region with uniform carrier density in the depth direction, the mobility will be constant, so it is the well-known Irvjn equation. From the bonds, it is possible to find the Kaida of ρ and n.Therefore, by substituting the shoulder obtained by the above equation (I) into ρ of the (Company) equation, the carrier density ni corresponding to ρi can be found. It is possible to set this ni to the carrier density in one plane, where xi≦X≦zi−+1, but there is a method of setting it to the carrier density in ()(i++−xi)/2, for example.

以上の如くにしてniを順次求めることによって、半導
体基板(6)の深さ方向のキャリア密度分布が得られる
By sequentially determining ni as described above, the carrier density distribution in the depth direction of the semiconductor substrate (6) can be obtained.

次にキャリア密度分布を測定すべき半導体基板(6)が
Si基板である場合につき本実施例で用いるモニタ用試
料(刀の購造及び作製法の一列を説明する。
Next, a method for purchasing and manufacturing a monitoring sample (sword) used in this example will be explained in the case where the semiconductor substrate (6) whose carrier density distribution is to be measured is a Si substrate.

第2図はモニタ用試料(刀の断面・溝造を示す拡大部分
断面図である。このモニタ用試料(7)は次のようにし
て作製する。ます、Si  基板(2υの表面に5t0
2  膜(2功を成長させ、次にこの5i02  膜曽
上にCVD法により、リンを十分にドーピングした多結
晶Si膜(ハ)を被着させる。均一なドーピングを行え
ば、この多結晶S i 1l123の膜厚とρSの間の
関係は通比例関係に近くなるので、エツチングの進行に
伴う多結晶Si膜(至)のρSの変化からこの膜のエツ
チング晋を測定することができろ。しかし、一般には上
記の逆比例関係は厳密には成り立たないので、多角′占
晶Si膜1.−,3)のノ庚厚とρSの関係をあらかじ
め冥験的に求めて2くのが好ましい。
Figure 2 is an enlarged partial sectional view of the monitor sample (sword cross section and groove structure). This monitor sample (7) is fabricated as follows.
2 film (2) is grown, and then a polycrystalline Si film (c) sufficiently doped with phosphorus is deposited on this 5i02 film by CVD method. Since the relationship between the film thickness of i1l123 and ρS is close to a proportional relationship, the etching depth of this film can be measured from the change in ρS of the polycrystalline Si film as etching progresses. However, in general, the above inverse proportionality relationship does not hold strictly, so it is preferable to find the relationship between the core thickness and ρS of the polygonal crystalline Si film 1.-, 3) empirically in advance. .

半導体基板(6)とモニタ用試料(7)の1回のエツチ
ング量は必要に応じて選択することができ、霜密な干ヤ
リア密度分布を得る必要がある場合には小さく、またぞ
うでないときは大きく取ればよい01回のエツチング量
の一例としては200Aが挙げられる。エツチング量が
この程江であれば、かなりイ′a密な・セヤリアが度分
布を得ることができる。
The amount of etching of the semiconductor substrate (6) and the monitoring sample (7) at one time can be selected as required. An example of the amount of etching for 01 times which should be large is 200A. If the amount of etching is as high as this, it is possible to obtain a fairly dense A/Seyaria distribution.

毎回のエンチング量が異なってもよいことは言うまでも
ない。
It goes without saying that the amount of enching may be different each time.

1回のエンチング量を上述のようにt、、?lえば20
0Aとすると、エツチング開始からキャリア密度の値を
得るまでの1サイクルの所要時間は6〜4分程度であり
極めて短い。
As mentioned above, the amount of enching per time is t,... If it is 20
When 0A is used, the time required for one cycle from the start of etching to obtaining the carrier density value is about 6 to 4 minutes, which is extremely short.

上述の実施例は次のような多くの利点を有する。The embodiment described above has many advantages, including:

第1に、半導体基板とモニタ用試料のエツチング及びρ
S測定を同一処理室内において行うようにしているので
、キャリア密度分布の測定を簡易迅速に行うことができ
る。第2に、半導体基板とモニタ用試料とを同時にエツ
チングしてこのモニタ用試料のエツチング量から前記半
導体基板のエツチング量を得るようにしているので、深
さ精′度の高いキャリア密度分布を簡便に得ることがで
きる。
First, etching of the semiconductor substrate and monitoring sample and ρ
Since the S measurement is performed in the same processing chamber, the carrier density distribution can be measured easily and quickly. Second, since the semiconductor substrate and the monitoring sample are simultaneously etched and the etching amount of the semiconductor substrate is obtained from the etching amount of the monitoring sample, carrier density distribution with high depth accuracy can be easily obtained. can be obtained.

第6に、RIEにより半導体基板とモニタ用試料のエツ
チングを行うようにしているので、化学エツチングの場
合に必要な洗浄、乾燥等の処理が不要となり、従ってこ
れらの処理を行うための設備も不要となる。第4に、真
空状態にある処理室内において半導体基板とモニタ用試
料のエツチング及びρS測定を行うようにしているので
、これらの半導体基板やモニタ用試料が大気に露出され
ることにより生ずるエツチング量及びρSの測定誤差を
除去することができる。第5に、演算器やメモリを用い
てデータ処理を行うようにしているので、キャリア密度
分布を自動的に測定することができる。
Sixth, since the semiconductor substrate and the monitoring sample are etched by RIE, there is no need for cleaning, drying, or other processes that are required for chemical etching, and therefore no equipment is required to perform these processes. becomes. Fourth, since the etching and ρS measurements of semiconductor substrates and monitor samples are performed in a processing chamber in a vacuum state, the amount of etching and ρS caused by exposure of these semiconductor substrates and monitor samples to the atmosphere can be reduced. The measurement error of ρS can be removed. Fifth, since data processing is performed using an arithmetic unit and memory, the carrier density distribution can be automatically measured.

上述の実施例においてはRIEによりエツチングを行っ
ているが、エンチング量の均一性が良ければ他のドライ
エツチング法を用いることも可能である。また、ρBの
測定方法も四探針法に限定されるものではない。
In the above embodiments, etching is performed by RIE, but other dry etching methods may be used as long as the uniformity of the etching amount is good. Furthermore, the method for measuring ρB is not limited to the four-point probe method.

モニタ用試料は、キャリア密度分布を測定すべき半導体
基板の種類により、必要に応じて変更すべきことは勿論
である。
Of course, the monitor sample should be changed as necessary depending on the type of semiconductor substrate whose carrier density distribution is to be measured.

発明の効果 本発明による半導体基板の深さ方向のキャリア密度分布
の測定方法によれば、キャリア密度分布を測定すべき半
導体基板とそニタ用試料とを同一処理室内に配してこれ
らの表面のドライエツチング及びρS測定を行うことに
よりキャリア密度を求め、これらの各工程を順次繰り返
すことによってキャリア密度分布を測定するようにして
いる。従って、キャリア密度分布を測定するために必要
な工程、設備及び時間を大幅に低減することができ、キ
ャリア密度分布の測定を簡易迅速に行うことができる。
Effects of the Invention According to the method for measuring the carrier density distribution in the depth direction of a semiconductor substrate according to the present invention, the semiconductor substrate whose carrier density distribution is to be measured and the sample for monitoring thereof are placed in the same processing chamber, and the surface of these substrates is measured. The carrier density is determined by dry etching and ρS measurement, and the carrier density distribution is measured by sequentially repeating these steps. Therefore, the steps, equipment, and time required to measure the carrier density distribution can be significantly reduced, and the carrier density distribution can be measured simply and quickly.

また、モニタ用試料の表面のρSの測定値から半導体基
板のエツチング量を求めるようにしているので、深さ精
度の高いキャリア密度分布を測定することができる。
Furthermore, since the etching amount of the semiconductor substrate is determined from the measured value of ρS on the surface of the monitoring sample, it is possible to measure the carrier density distribution with high depth accuracy.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の詳細な説明するためめキャリア密度分
布測定装置の概略的な構成図、第2図は本発明の実施例
で用いるモニタ用試料の一例の断面構造を示す拡大部分
断面図である。 なお図面に用いた符号において、 (1)   ・   処理室 (5)・・   試料台 (6)    ・半導体基板 (力  ・  モニタ用試料 u4)  ・ ・・   ρB測定装置(15)   
−・・・ 演算器 (IOメモリ Uη −−・ 出力装置 しυ ・・・・・ ・ St基板 四   ・5102膜 (2)・・・ −多結晶St膜 である。 代理人 上屋 勝 常包芳男 杉浦俊貴
FIG. 1 is a schematic configuration diagram of a carrier density distribution measuring device for explaining the present invention in detail, and FIG. 2 is an enlarged partial sectional view showing the cross-sectional structure of an example of a monitoring sample used in an embodiment of the present invention. It is. In addition, in the symbols used in the drawings, (1) ・Processing chamber (5)・・Sample stage (6)・Semiconductor substrate (force・monitoring sample u4)・・ρB measuring device (15)
-... Arithmetic unit (IO memory Uη - - Output device υ... - St substrate 4 - 5102 film (2)... - Polycrystalline St film. Agent Katsutsuneaki Ueya Yoshio Toshiki Sugiura

Claims (1)

【特許請求の範囲】 半導体基板表面を段階的に除去しその都度前記半導体基
板表面のシート抵抗を測定することによって前記半導体
基板の深さ方向のキャリア密度分布を測定する方法にお
いて、 (a)、前記半導体基板とモニタ用試料とを同一処理室
内に配して前記半導体基板表面と前記モニタ用試料表面
とを同時にドライエツチングする工程、 (b)、、前記処理室内において前記半導体基板表面と
前記モニタ用試料表面のそれぞれのシート抵抗を測定す
る工程、 (C)、前記モニタ用試料表面の/−ト抵抗の前記測定
値から前記半導体基板表面のエツチング量を得、前記半
導体基板表面の前記エツチング量と前記半導体基板表面
のシート抵抗の前記測定値とから前記半導体基板表面か
らの前記エツチング量に相当する深さをこおける前記半
導体基板のキャリア密度を得る工程、 をそれぞれ具備し、上記(a)〜(C)の工程を順次繰
り返して行うことを特徴とする半導体基板のキャリア密
度分布の測定方法。
[Scope of Claims] A method for measuring the carrier density distribution in the depth direction of the semiconductor substrate by removing the semiconductor substrate surface stepwise and measuring the sheet resistance of the semiconductor substrate surface each time, comprising: (a) arranging the semiconductor substrate and the monitor sample in the same processing chamber and dry etching the semiconductor substrate surface and the monitor sample surface at the same time; (b) the semiconductor substrate surface and the monitor sample in the process chamber; (C) obtaining the amount of etching on the surface of the semiconductor substrate from the measured value of the sheet resistance on the surface of the sample for monitoring; and the step of obtaining the carrier density of the semiconductor substrate at a depth corresponding to the etching amount from the surface of the semiconductor substrate from the measured value of the sheet resistance of the surface of the semiconductor substrate, respectively, and (a) A method for measuring carrier density distribution in a semiconductor substrate, characterized in that the steps from (C) to (C) are repeated in sequence.
JP7514383A 1983-04-28 1983-04-28 Measurement of density distribution of semiconductor carrier Pending JPS59201436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7514383A JPS59201436A (en) 1983-04-28 1983-04-28 Measurement of density distribution of semiconductor carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7514383A JPS59201436A (en) 1983-04-28 1983-04-28 Measurement of density distribution of semiconductor carrier

Publications (1)

Publication Number Publication Date
JPS59201436A true JPS59201436A (en) 1984-11-15

Family

ID=13567674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7514383A Pending JPS59201436A (en) 1983-04-28 1983-04-28 Measurement of density distribution of semiconductor carrier

Country Status (1)

Country Link
JP (1) JPS59201436A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5434089A (en) * 1992-07-30 1995-07-18 Sgs-Thomson Microelectronics S.A. Method for testing the sheet resistivity of diffused layers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5434089A (en) * 1992-07-30 1995-07-18 Sgs-Thomson Microelectronics S.A. Method for testing the sheet resistivity of diffused layers

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