JPS59201435A - Etching pattern inspecting method - Google Patents

Etching pattern inspecting method

Info

Publication number
JPS59201435A
JPS59201435A JP58075014A JP7501483A JPS59201435A JP S59201435 A JPS59201435 A JP S59201435A JP 58075014 A JP58075014 A JP 58075014A JP 7501483 A JP7501483 A JP 7501483A JP S59201435 A JPS59201435 A JP S59201435A
Authority
JP
Japan
Prior art keywords
chip
pattern
etching
etching pattern
inspection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58075014A
Other languages
Japanese (ja)
Inventor
Masanori Sato
正憲 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58075014A priority Critical patent/JPS59201435A/en
Publication of JPS59201435A publication Critical patent/JPS59201435A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)

Abstract

PURPOSE:To facilitate a secure and simple resolution test of a formed pattern by a method wherein light energy such as laser beam is applied to a semiconductor chip to be tested and a wave signal corresponding to an etching pattern is obtained by a reflected signal and this wave signal is compared with a reference wave signal. CONSTITUTION:Light energy such as laser beam 13 is applied to a mask chip 12 in a photomask on which a reference etching patten 11 is formed and the pattern 11 is scanned to the direction expressed by an arrow (a). Then an etching pattern 11a, which corresponds to the etching pattern 11 and is formed on a semiconductor chip 14 to be imspected, is scanned in the same way. After that, reflected signals from the chips 12 and 14 are converted into respective pulse wave signals and their shapes are compared and difference between them is detected. If their wave shapes are identical, it is judged that the photoetching is performed accurately and if they are not, it is judged that the pattern is defective.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、半導体装置製造過程のフォトエツチング工
程において、例えば所定のエツチングパターンが形成さ
れたフォトマスクに対応してフォトエツチングされた半
導体ウェハのエツチングパターンを自動検査するだめの
エツチングパターン検査方法に関する。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to etching of a semiconductor wafer that is photo-etched in accordance with a photomask on which a predetermined etching pattern is formed, for example, in a photo-etching process of a semiconductor device manufacturing process. This invention relates to an etching pattern inspection method for automatically inspecting patterns.

〔発明の技術的背景〕[Technical background of the invention]

例えば、半導体装置製造過程のフォトエツチング工程に
おいて、ノソターン形成された半導体ウェハを検査する
には、ウエノX自動検査装置が使用される。この検査装
置は半導体ウエノ)の複数のチップそれぞれに、レーザ
光等の光エネルギーを照射し、その反射光の強弱を検出
して上記半導体チップの表面に存在するごみ、傷1の検
査を行なうもので、この検査装置はまた、フォトマスク
表面のごみ、傷等の検査を行なう場合にも同様にして使
用されるものである。
For example, the Ueno-X automatic inspection apparatus is used to inspect a semiconductor wafer on which a noso turn has been formed in a photoetching process of a semiconductor device manufacturing process. This inspection device irradiates each of a plurality of semiconductor chips with light energy such as a laser beam, detects the strength of the reflected light, and inspects for dust and scratches on the surface of the semiconductor chips. This inspection device is also used in the same way when inspecting the surface of a photomask for dust, scratches, etc.

ここで、この検査装置は、主として半導体ウェハ表面ま
たはフォトマスク表面のごみ、傷等を検査するものであ
り、ウェハまたはフォトマスク自体に形成されたエツチ
ング・々ターンを検査することはできない。すなわち、
フォトマスクまたは半導体ウニへの複数のチップそれぞ
れ〔背景技術の問題点〕 しかし、このように人間の目により半導体ウェハまたは
フォトマスクに形成されたエツチングパターンを検査し
たのでは、例えばフォトエツチング後の半導体ウェハを
検査する場合、次のような4つの項目について検査しな
ければならない。
Here, this inspection apparatus is mainly used to inspect dust, scratches, etc. on the surface of a semiconductor wafer or a photomask, and cannot inspect etching or turns formed on the wafer or photomask itself. That is,
Multiple chips on a photomask or semiconductor wafer [Problems in background technology] However, if the etching pattern formed on a semiconductor wafer or photomask is inspected by human eyes in this way, for example, the semiconductor after photoetching cannot be inspected. When inspecting a wafer, the following four items must be inspected.

(1)レジスト膜の剥れ具合。(1) Peeling condition of resist film.

(2)ウェハ表面の異物、傷等の存在の有無。(2) Presence or absence of foreign matter, scratches, etc. on the wafer surface.

(3)エツチングノぐターンの解像度。(3) Resolution of etching turns.

(4)ウニ八整理番号。(4) Sea urchin eight serial number.

すなわち、このような多数の項目について、フォトエツ
チングされたクエへを一枚一枚検査したのでは、非常に
多くの検査時間を費やしてしまうと共に、特に上記項目
(3)の解像度検量においては、検査難度が高く目の疲
労が著しいため、しばしばパターン不良の生じたウェハ
を見逃してしまう等の不都合が発生するものである。
In other words, for such a large number of items, if each photo-etched image was inspected one by one, an extremely large amount of inspection time would be consumed, and especially in the resolution calibration of item (3) above, Inspection is highly difficult and causes significant eye fatigue, resulting in inconveniences such as often overlooking wafers with pattern defects.

〔発明の目的〕 この発明は上記のような問題点に鑑みなされたもので、
例えば半導体ウェハの複数のチップそれぞれに形成され
たエツチングパターンの解像度を検査する際に、多くの
検査時間を費やすことなく、確実且つ簡単に検査するこ
とが可能となるエツチングパターン検査方法を提供する
ことを目的とする。
[Object of the invention] This invention was made in view of the above problems.
To provide an etching pattern inspection method that enables reliable and easy inspection without spending a lot of inspection time, for example, when inspecting the resolution of an etching pattern formed on each of a plurality of chips of a semiconductor wafer. With the goal.

〔発明の概要〕[Summary of the invention]

すなわちこの発明に係るエツチングパターン検査方法は
、被検査チップにレーザ光等の光エネルギを照射し、そ
の反射信号により得られる上記被検査チップのエツチン
グ・ぐターンに対応した波形信号を、所定のエツチング
パターンに対応した波形信号と比較して、それぞれのパ
ターンの相違を認識するようにするものである。
That is, the etching pattern inspection method according to the present invention irradiates a chip to be inspected with light energy such as a laser beam, and processes a waveform signal corresponding to the etching pattern of the chip to be inspected, which is obtained from a reflected signal, by a predetermined etching process. By comparing the waveform signals corresponding to the patterns, the differences between the respective patterns can be recognized.

〔発明の実施例〕[Embodiments of the invention]

以下図面によりこの発明の一実施例を説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図はこの検査方法により、例えば半導体チップに形
成されたてツチングパターンを検査する場合の検量過程
を示すもので、はじめに同図(A)に示すように所定の
エツチングパターン11が形成された例えばフォトマス
ク内のマスクチップ12に、破線矢印で示すようなレー
ザ光13等の光エネルギーを照射し、斜線矢印aで示す
ように平行走査する。次に、第1図CB)に示すように
上記マスクチップ12の所定のパ9− ン11に対応し
てフォトエツチングされパターン形成された半導体ウェ
ハ内の被検査テップ14を、上記と同様にレーザ光13
で平行走査する。
FIG. 1 shows the calibration process when inspecting, for example, a freshly etched pattern formed on a semiconductor chip using this inspection method. First, a predetermined etched pattern 11 is formed as shown in FIG. For example, a mask chip 12 in a photomask is irradiated with light energy such as a laser beam 13 as shown by a broken line arrow, and is scanned in parallel as shown by a diagonal arrow a. Next, as shown in FIG. 1CB), the test target 14 in the semiconductor wafer, which has been photoetched and patterned in correspondence with the predetermined pattern 11 of the mask chip 12, is laser-etched in the same manner as above. light 13
to scan in parallel.

そして、このようにレーザ光13で平行走査したことに
より得られる上記マスクチップ12および被検査ブーツ
ブ14からの反射信号を、それぞれ第2図(A)および
(B)に示すような、パルス波形信号に変換する。この
場合、その波形信号は、それぞれ上記2つのチップ12
および14に形成されたエツチングパターン11および
11aに正確に対応したパルス波形となるもので、この
第2図におけるそれぞれの波形信号の形状を比較してそ
の相違を認識し、マスクテップ12のエツチングパター
ン11と被検査チップ14に形成されたエツテングノや
ターンllaとの違いを判断する。
Then, the reflected signals from the mask chip 12 and the test boot 14 obtained by parallel scanning with the laser beam 13 are converted into pulse waveform signals as shown in FIGS. 2(A) and 2(B), respectively. Convert to In this case, the waveform signals are transmitted to the two chips 12, respectively.
The pulse waveforms correspond precisely to the etching patterns 11 and 11a formed in the mask step 12. By comparing the shapes of the respective waveform signals in FIG. The difference between this and the etching marks and turns lla formed on the chip 14 to be inspected is determined.

すなわち、第2図CA1で示したマスクチップ12の所
定のエツチングパターン11に対応する波形信号に対し
て、同図FB)で示した被検査チップ14のエツチング
パターンllaに対応する波形信号が、それぞれ同一波
形であれば、その被検査チップ14のパターンllaは
正確にフォトエツチングされ形成されていると判断する
ことができ、また、同一波形でなければ被検査テップ1
4のパターンllHには異常が生じてしすると判断する
ことができる。したがってこの実施例においては、被検
査チップ14にフォトエツチング形成された/セターン
llaを不良ノぞターンと判断することができるように
なる。
That is, for the waveform signal corresponding to the predetermined etching pattern 11 of the mask chip 12 shown in FIG. If the waveforms are the same, it can be determined that the pattern lla of the chip 14 to be inspected has been accurately photoetched, and if the waveforms are not the same, it can be determined that the pattern lla of the chip 14 to be inspected is
It can be determined that an abnormality has occurred in pattern llH of No. 4. Therefore, in this embodiment, it is possible to determine that the /set turn lla formed by photoetching on the chip 14 to be inspected is a defective turn.

尚、上記実施例では所定のエツチングパターン11が形
成されたモデルチップとしてマスクチップ12を用いる
ようにしたが、このモデルテップには、良品・母ターン
と判断された半導体テップを用いるようにしてもよい。
In the above embodiment, the mask chip 12 was used as the model chip on which the predetermined etching pattern 11 was formed, but it is also possible to use a semiconductor chip determined to be a good product/base turn as the model chip. good.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、例えば1000枚もの
半導体ウェハの複数のチップそれぞれに形成されたエツ
チングパターンの解像度を、8時間という所定時間内で
検査するような場合でも、目視検査により多くの時間を
費やす必要なく、確芙且つ簡単に検査することが可能と
なり、検査ミスの発生を防止できるようになる。
As described above, according to the present invention, even when inspecting the resolution of etching patterns formed on each of a plurality of chips of 1,000 semiconductor wafers within a predetermined time of 8 hours, visual inspection can It becomes possible to perform an inspection accurately and easily without spending time, and it becomes possible to prevent the occurrence of inspection errors.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例に係るエツチング−やター
ンの検査過程を説明するもので(AJはマスクチップ、
fB)は被検査チップを拡大して示す図、第2図(A)
および(B)はそれぞれ上記マスクチップおよび被検量
チップに対応する波形信号を示す図である。 11、lla・・・エツチングパターン、12・・・マ
スクチップ、13山レーザ光、14・・・被検査チップ
FIG. 1 explains the etching and turn inspection process according to an embodiment of the present invention (AJ is a mask chip,
fB) is an enlarged view of the chip to be tested, Figure 2 (A)
and (B) are diagrams showing waveform signals corresponding to the mask chip and the test amount chip, respectively. 11, lla... Etching pattern, 12... Mask chip, 13 peak laser beam, 14... Chip to be inspected.

Claims (1)

【特許請求の範囲】 半導体装置製造過程のフォトエツチング工程のマスクチ
ップまたは半導体チップに形成されたエッチ・フグ/4
’ターンの検査において、被検IEチップに光エネルギ
ーを照射する手段と、この照射手段により反射される上
記被検査チップのエツチングパターンに対応した反射信
号を波形信号に変換する手段と、この手段により変換さ
れた上記被検査チップの波形悄七ンb〔定のエツチング
パターンに対応した波形信号と比較し認識する手段とを
具備したことを特徴とするエツチングパターン検査方法
[Claims] Etch puffer formed on a mask chip or a semiconductor chip in a photoetching process in a semiconductor device manufacturing process/4
In the turn inspection, means for irradiating optical energy onto the IE chip to be tested; means for converting a reflected signal corresponding to the etching pattern of the chip to be tested reflected by the irradiation means into a waveform signal; An etching pattern inspection method comprising means for comparing and recognizing the converted waveform signal of the chip to be inspected with a waveform signal corresponding to a predetermined etching pattern.
JP58075014A 1983-04-28 1983-04-28 Etching pattern inspecting method Pending JPS59201435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58075014A JPS59201435A (en) 1983-04-28 1983-04-28 Etching pattern inspecting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58075014A JPS59201435A (en) 1983-04-28 1983-04-28 Etching pattern inspecting method

Publications (1)

Publication Number Publication Date
JPS59201435A true JPS59201435A (en) 1984-11-15

Family

ID=13563897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58075014A Pending JPS59201435A (en) 1983-04-28 1983-04-28 Etching pattern inspecting method

Country Status (1)

Country Link
JP (1) JPS59201435A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62263646A (en) * 1986-05-12 1987-11-16 Toshiba Corp Inspecting device for wafer
JPS642332A (en) * 1987-05-15 1989-01-06 Therma Wave Inc Method and device for testing desired area of workpiece by designating the area

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62263646A (en) * 1986-05-12 1987-11-16 Toshiba Corp Inspecting device for wafer
JPS642332A (en) * 1987-05-15 1989-01-06 Therma Wave Inc Method and device for testing desired area of workpiece by designating the area

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