JPS5920142B2 - Error detection/correction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error detection/correction method, and in particular to a method that is effective in detecting and correcting errors in a memory that has a modular configuration and is composed of a storage element with a multi-bit output. .

Conventionally, in order to correct errors using a 1-bit error correction or 2-bit error detection code, a syndrome is created using a parity generation matrix as shown in FIG. 2, and error positions are determined.

That is, as shown in FIG.
0 to C3='0011'' are obtained and added to the information D0 to D3 as shown in FIG.

FIG. 1c shows a syndrome created from the codes in FIG. 1, and the exclusive OR of the codes corresponding to ``1'' in FIG. 2 is performed. 50=D01D11D31C0 5,=D01D21D, 1C1...(1) 52=D11D21D31C2 53=D01D11D21D31C01C11C2 C
3 As a result, all 50 to 53 become ゜゛o'', and the original information codes D0 to D3 and Hamming codes C0 to C3
It is confirmed that there are no errors.

Next, as shown in FIG. 1d, if there is an error in the information code D2, syndrome S is determined by the above equation (1).

〜53, as shown in Figure 1e, ゛゛011
1'', this code is decoded from the parity generation matrix shown in FIG. 2, and it is determined that there is an error in D2. Therefore, as shown in FIG. 1f, the information code D2 is inverted to correct it. Through such methods, the reliability of communication devices and memory devices is improved. By the way, the memory IC of the main memory device is currently IC
In order to reduce the number of pins per case, a 1-bit configuration has been adopted, but with the development of highly integrated LSI technology, memory elements with multiple bit (b-bit) data output will become the mainstay of electronic computer systems in the future. It is thought to be used in memory devices and the like.

However, in such a storage element with a plurality of (b) bit outputs, if the element fails, there is a risk that an error will occur during the programming of the b bits output from the element. Therefore, in recent years, 1-bit error correction/single block error detection codes (hereinafter referred to as SEC-SbED codes) have been developed.

SingleErrOrCOrrectiOn-Sin
g′EBlOckErrOrDetectionOnCOd
e) or) SEC-DED-SbED code (SingleE
rrOrCOrrectiOn-DoubleErrO
rDetectiOnSing'EBlOckErrO
An error detection/correction method using rDetectionCode is being researched. An H matrix as shown in Fig. 3 has already been proposed as an effective code for multi-bit output storage elements (Fujiwara, Proceedings of the 1981 Institute of Electronics and Communication Engineers National Conference, P365, or S.M.
．． Reddy's "A Class Of Linear COd
esfOrErrOrCONtrOlfOrByte-
Per-CardOrganizedDigitalS
FTCS-7, 1977). FIG. 3 is an example of the H matrix of the SEC-S3ED code, with five syndromes S for seven blocks with 3-bit output.

-S4 is shown, and the check bits are the 3 bits on the left and the 2nd and 3rd bits from the right,
The remaining bits are information D. -Dl5. However, in the conventional H matrix shown in Fig. 3, cards with the same pattern cannot be produced because the matrix lacks modularity (repeatability). It is not suitable for

Further, as shown by C4 and C5 in FIG. 3, the check bits are not concentrated in a specific block but are mixed in the same block as the data bits, which complicates the circuit design. Furthermore, as a result of conventional research, SEC-D
The maximum code length of the ECR-B SbED code is n-b·2 bits, and the maximum code length R-b+1 of the SEC-SbED code is n-b(2-1) bits.

An object of the present invention is to have a modular configuration suitable for LSI implementation of encoding circuits and decoding circuits, and to concentrate check bits only in specific programs, in order to eliminate the conventional drawbacks as described above. Therefore, it is an object of the present invention to provide an error detection/correction system which simplifies circuit design and has the same number of check bits and the same or greater coded information length as the conventional one. The error detection/correction method of the present invention is (DO, Dl・
...Dk-1) is coded information consisting of blocks Di of b bits each, then receive the coded information and use the coded information according to the relational expression Cj = Hj, i-Di. Test check program Cj (j-0,1...r-
1, r〉2)
However, the unit matrix of BXb is set to 0, and the BXb matrix obtained by cyclically permuting 10 by q bits in the column direction is expressed as Iq(q
=0,1,2...Bb-1), and O<
The binary representation of the integer u such that u〈2 is (AO, al...A
b-1), then all column vectors are (AO, al
... Ab-1) t゛ [t... transposed] BXb matrix is Mu, and in Mu there are (AO, al...
Ab-1) has a weight of 1. ．． When we decide to exclude something q, HJ,! is I or Mu,
And H.

i, hll...Hr-,,1 has at least one I
(required to include q) and check block C
A code word consisting of coded information and coded information is received, and Sj=Hj, i. a syndrome generation circuit that creates a syndrome Sj according to Di+Cj; an error detection circuit that detects an error from the error syndrome; a syndrome decode circuit that creates a signal that indicates an error position from the error syndrome; The syndrome block S consists of an error correction circuit that corrects errors in received information. , Sl... If there is at least one syndrome block with a weight of "1" in Sr-1, it is corrected as a 1-bit error, and when other syndromes occur, it is detected as a multiple-bit error. do. Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 is a block diagram of the error detection/correction system of the present invention. The 1-bit error correction/single block error detection system shown in FIG. 4 includes a check block generation circuit 2 as an encoding circuit, a syndrome generation circuit 9 as a decoding circuit, and a syndrome decoding circuit 6.

1 is encoded information, 2 is check bit (check bit)
Block) generation circuit 3 is coded information consisting of coded information and check block.

The coded information is D. , D, ... When Dk-1 (
(where D is a b-bit block) The check block is obtained by the following equation (r is the number of check blocks). Cj-H
j, i. Di, (j=0,1...r) (2)H
j and i will be described later.

The number of check bits is R. b bit, Hj, i is 0,1
This is a BXb matrix whose elements are . This encoded information is passed through the storage array and channels into a potentially erroneous form, resulting in 12 received codewords.

Reference numeral 10 indicates check program time, 11 indicates encoded information, and 9 indicates a syndrome generation circuit that generates syndrome Sj from 10 and 11 according to the following equation.

Sj=Hj, i. Di+Cj, (j-0,1...r)
(3) Syndrome Sj is R. Needless to say, there are b bits.

Syndrome 7 includes error detection circuit 8 and syndrome. The signal is sent to a decoding circuit 6 and becomes an error position indication signal 5. Errors in the received coded information 11 are corrected in the error correction circuit 4 by the error position indication signal 5, and become correct information 3. 4 is constructed using a well-known technique consisting of a two-input exclusive 0R gate.

In the present invention, in the above error detection/correction method, the syndrome decoder circuit 6, the syndrome generation circuit 9,
Check. The bit generation circuit 2 is constructed to have a modularity (repeatability) of r.

In the code structure of the present invention, the number of check bits is a multiple of b, so each b bit is called a check block.

In the conventional method, the number of check bits can be set to any number above a certain value, but in the present invention, it is limited to a multiple of b.

However, since it is possible to check the same or greater coded information length with the same number of check bits, the number of check bits can be reduced compared to the conventional method. The SEC-SbED code used in the error detection/correction method of the present invention will be described below.

First, we will first explain the construction method of SED-SbED code, and then
A method of constructing C-DED-SbED codes and finally a method of providing modular construction to these codes will be described. First, the SEC-(DED)-SbED described here
The H matrix of the code is composed of BXb matrices Hl and J whose elements are 0 and 1.

The binary representation of u is {AO, al...Ab-,}, a{0
, 1}, then all column vectors are [AO, alt
...Ab-1], (t: transposed) is represented by a BXb matrix Mu.

Also, let Iq represent a matrix obtained by cyclically permuting the unit matrix of BXb q times in the column direction. In the error correction code of the present invention, Hi,j is 10, 11...Ib-1 and Mu
(u-0,...2b-L However, [AO, al...Ak
−, ] except those in which the weight of t is 1).

For example, in b-3, eight BXb matrices are used as Hi,j as shown in FIG. In general b value, I
There are b pieces of q, 26-b pieces of Mu, and Iq (2b for 5 Mu).
There are several types.

A method of configuring the SEC-SbED code will be explained. S.E.
In order to construct a C-SbED code, it is necessary to satisfy the following conditions when selecting Iq and Mu as Hi,j.

However, check. The number of blocks is assumed to be r (r>2). (a
) Hi, O, hi, l...Hi,, -, contains at least one 1q.

(b) Hi, O, hi, l...Hi, r-1 are all M.

(i.e., not blank). (c) Column vector of H matrix of constructed code (considered bit by bit)
are linearly independent of each other. From these facts, the maximum bit length n of the constructed code is given by the following equation.

However, the details of the derivation of the formula are omitted because they are not directly related to the details of the invention. Rn=B. Σ. RCl. (2b-b)r-
! bl-1L-12b. r-(2b-b)r...(
4) In the example of b-3, SECS3ED as shown in Figure 8
The sign is obtained.

SEC of the code obtained by this construction method Think about SbED ability.

First, 1-bit error correction capability (SEC) is guaranteed because the column vectors for each bit are all different from each other. The SbED capability is clear from the following. This is because a syndrome with a 1-bit error always occurs in b of weight ``1'' in r syndrome blocks.
There is at least one bit block, and on the other hand, a block error of 2 or more bits is either All6O' for each of the r syndrome blocks, or the weight is 2 or more, and the plotter with weight -1' is That's because there isn't. In addition,
In the H matrix of FIG. 8, check blocks are concentrated in the two leftmost blocks (CO-C5), and information D is located to the right of the third block from the left.

-D32 are arranged. SEC-DCD-SbED
The method of constructing the code will be explained.

In the SEC-DED-SbED code, the above SEC-S
It is constructed by extracting column vectors (considering each block) from the bED code.

The newly added restrictive conditions are as follows. (d) The weight in the column direction of each column vector is an integer weight.

Based on this limiting condition, it is easy to extract columns.

It should be noted that the weights within the block for each b bit are all constant. Since the H matrix is a parsimonious weight, DED capability is guaranteed. For a 2-bit error, the syndrome can be clearly distinguished from a 1-bit error with an even weight.

In order to be a SEC-DED-SbED code, when there are r BXb matrices Hi,j in the column vector direction,
Focusing on the parasiticity of the weights in the column direction of Hi, there must be a parasitic number of 'Hi' in the r number. There are J ways of dividing as described below. ~υ
' For example, when r=3, there are the following four ways.

Then, while paying attention to the linear independence of the column vectors,
In the part of Iq or Mu, u-(AO, al...
Ab-1) is an odd weight, and in the "even" part, U=(AO,al...Ab-1) is an even weight.

However, enter Iq in at least one of the "yori" characters.
An example of a SEC-DED-SbED code with b-3, r=3 is shown in FIG.

There are two types of even weights in b-1 Mu (zero matrix M).

). Also, among Mu, those with a weight of radial b-1 are 2
-There are b ways.

Therefore, for the above-mentioned parity vector with p pieces of parity, the type of column vector is given by the following equation.

However, '' is the number of Iq, and the other '' is Mu. Since D-1...≦(t), the total code bit length is given by the following equation.

When Mr=3, b=3, it is L-207 bits, and b-4
, r=2, L=64 bits.

Figure 9a is an example of r-3,b=3, Figure 10a is r-2
, b=4. However, FIG. 9b shows the configuration of FIG. 9a, FIG. 10b shows the configuration of FIG. 10a, and FIG. 10c shows FIG. 10a expressed in Mu and Iq. , I is 10, and the blank space represents a pigeon. Next, the structure of the SED-1ED) SbED code having a modular structure will be explained.

Here, a SEC-(DED)SbED code having a modular configuration suitable for LSI implementation of an encoding/decoding circuit will be described.

However, although the SEC-DED-SbED code will be explained as an example, the SEC-SbED code can be constructed in exactly the same manner. First, attention is paid to FIG. 9, which is SEC-DED S3E No. with r=3, b-3.

Looking at Figure 9, there are three 3x3 matrices for each block, but if the column vectors for each block are cyclically replaced by 3 bits in the row direction of the H matrices, other column vectors can be obtained. There are many.

For example, every 16 blocks from the beginning of Figure 9, a total of 46
Considering the blocks, it can be seen that a total of 48 blocks are obtained by simply cyclically permuting the 16 blocks from the beginning in the 3-bit and 6-bit row direction.
This cyclic nature is also observed in many of the remaining blocks. Such cyclicity is unique to the new code construction method proposed by the present invention.

Except for the 3 procs shown as "non-cyclic" in FIG. 9, the 66 procs used have a large cyclic degree of 3. What is shown as "acyclic" in Figure 9 is one that matches the original self when cyclic is added, and such an acyclic column vector can be easily deepened visually. It is possible. Further, the number of acyclic blocks is generally small; in the example of r-3,b=3 in FIG. 9, there are three blocks, and in the example of r-2 in FIG. 10, there are no acyclic blocks. Check in general. When the number of blocks is r, it is complicated to analytically derive the number of acyclic blocks for any b, and although we will not go into details in this example, the conclusion is that the code length can be determined as follows. Desired.

However, the degree of circulation is r times. The code bit length n in the case of the SEC-SbED code is as follows.

However, Σ indicates the sum of all divisors of r, and μ(
d) is the X-Bius function (MObiusFunctiOn)
and is defined by.

The values of μ(d) for d-1 to d-8 are shown as examples. GCD-(
D, b) is the greatest common divisor of d(5b).

Code bit length n in case of SEC-DED-SbED code
is as follows. Rrrl − − − n=−2ξ(d) {(2b)d+Bd−(2b−b)d
}(D,b)d:0dd゜゜゜゜From these formulas, the above SEC-SbED code, SEC-DED-Sb
The reduction in code length caused by making the ED code circular is slight.

Now, as mentioned above, in Fig. 10, the circularity is r-2, and in Fig. 9, except for some blocks, r = 3.
It was shown that it has a circularity of . In this way, in the code construction method of the present invention, when the number of check blocks is r, H
It is easy to configure the H matrix so that the matrix has r-cyclicity. By having cyclic nature,
It becomes possible to realize the entire function by using multiple pieces of the same gate logic. This is convenient for converting the circuit into an LSI. Hereinafter, a specific configuration of the error detection/correction system of the present invention will be disclosed using the embodiment shown in FIG.

Here, the circularity is 2. FIG. 5 shows the configuration of the check block generation circuit or syndrome generation circuit.

The circuit of FIG. 5 is configured according to the H matrix of FIG. 10. For example, it is clear that the partial sum P.

The gate that creates 20 (same configuration as the gate that creates 20 is fine,
PO and D. ~D27 to S. The gate that creates is P. and D2
It may have the same configuration as the gate that creates S4 from 8 to D55. From this, it can be seen that the cyclicity of 2 shown in FIG. 10 directly produces the modularity of 2 of the syndrome generation circuit 9.

The same is true when decoding syndromes.
The circuit for decoding the error syndrome occurring in the first eight blocks of FIG. 10 and the circuit decoding the error syndrome occurring in the remaining eight blocks may be exactly the same. FIG. 6 is a block diagram of the syndrome decoding circuit. As shown in FIG. 6, the syndrome input S of the circuit decodes the error of 8 blocks from the beginning. -S3
Put S4 to S7 in and S to S4 to S7. - By removing S3, the remaining 8 blocks can be used as decoding circuits. The circuits in FIGS. 5 and 6 and the gate configuration per repeated section are more specifically shown in FIGS. 11 and 1.
These are shown in Figure 2, respectively.

Here, A is AND gate, 0 is 0R gate, XOR
is an exclusive 0R gate. FIG. 13 shows an error detection circuit. In FIG. 13, 20 and 21 are partial parity sums, 13 is an XOR gate, 14 is an 0R gate, and 15
is an AND gate. As explained above, according to the present invention, for coded information having a plurality of multi-bit blocks Dl, Cj=Hj,
By adding an LDi check block, error detection and correction are performed, so the check bits are concentrated only in a specific plotter, simplifying circuit design, and allowing the encoding and decoding circuits to have a modular configuration. L
It becomes easier to apply to SI.

Furthermore, in the US-based SEC-DED-SbED code, for example, when the check bits are R-9 bits and B-3 bits, the code is 192 bits, but in the present invention, even if modularity 3 is given, the code is 198 bits. Since the code length is long, encoding is possible with a small number of check bits. Furthermore, compared to the prior art, in the present invention, the weights in the row direction are averaged, so that the check bit Cj
and syndrome Sj can be generated at high speed.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of a 1-bit error correction method in the case of a conventional single-output storage element, Fig. 2 is a diagram showing the parity generation matrix of Fig. 1, and Fig. 3 is a diagram showing a conventionally proposed multi-bit output storage. 4 is a schematic block diagram of the error detection/correction method of the present invention, and FIG.
The block diagram of the syndrome generation circuit shown in Figure 6 is
The block diagram of the syndrome decoding circuit shown in Fig. 7 is 3X in the SEC-DED-S3ED code of b-3.
FIG. 8 is a diagram showing an H matrix of SEC-S3ED code showing an embodiment of the present invention, and FIG. FIG. 10 is an explanatory diagram of the H matrix of the SEC-DED-S3ED code, and FIG.
11 is a detailed configuration diagram of the syndrome generation circuit (check bit generation circuit) in FIG. 5, and FIG. 12 is a detailed configuration diagram of the syndrome decoding circuit in FIG. 6. FIG. 13 is a detailed configuration diagram of the error detection circuit in FIG. 4. 1: Encoded information, 2: Check bit generation circuit, 3
: Encoding information, 4: Correction circuit, 5: Error indication signal, 6:
Syndrome decoding circuit, 7 resyndrome, 8:
Error detection circuit, 9: syndrome decoder, 10: check bit, 11: encoded information, 12: encoded information, 13: XOR circuit, 14: 0R circuit, 15: AN circuit, 20, 21: partial parity sum.

Claims (1)

[Claims] 1 Receive encoded information consisting of a plurality of blocks D_i of multiple (b) bits, and create a b×b matrix I^q obtained by cyclically permuting the b×b unit matrix by arbitrary (q) bits in the column direction, and an arbitrary The binary representation of an integer (0≦u<2^b) is (
a_0, a_1...a_b_-_1), all column vectors are (a_0, a_1...a_b_-_1
) as a matrix hi, j, and each matrix column includes at least one matrix I^q, and the encoded information is From C_j=h_j_,_i
A check block generation means for generating a check block represented by D_i, the check block C_j
a syndrome generating means that receives a code word consisting of the information to be encoded and generates a syndrome Sj from the code word according to S_j=h_j_,_iD_i+C_j; an error detecting means that detects an error from the syndrome Sj; syndrome decoding means for creating an error position indication signal from the error position indication signal; and error correction means for correcting an error in the received code word using the error position indication signal; An error detection/correction method characterized in that when a syndrome block with a weight of "1" exists, it is corrected as a 1-bit error, and when other syndromes exist, it is detected as a multiple-bit error.