JPS59198593A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain the reduction of noise generated on a power supply line by setting an operating timing of a main amplifier and/or a data output buffer with a time difference in response to the signal transfer time of the signal line connecting said main amplifier and/or the data output buffer from each memory mat so as to mitigate the peak value of the current flowing to the power supply line. CONSTITUTION:When the distance between the main amplifiers MA1, MA2 is short as memory arrays M1, M2, a timing signal phimal is applied to the main amplifiers MA1, MA2. On the other hand, when the distance of the main amplifiers MA3, MA4 is long as memory arrays M3, M4, a timing signal phima2 delayed by said time difference td from said timing signal phimal is applied to the main amplifiers MA3, MA4. Further, as the operating timing of input/output circuits 101-104, two kinds of timing signals phi01 and phi02 are used similarly as above. Since the main amplifiers MA1, MA2 and the main amplifiers MA3, MA4 are operated with a time difference td in reading 4-bit data D1-D4, the fluctuation of a potential Vss of, e.g., a ground wire of the circuit is reduced.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory device, for example,
MOSFET (insulated gate field effect transistor)
The present invention relates to a technique effective for a dynamic RAM (random access memory) for writing and reading information consisting of a plurality of bit nodes.

[Background technology]

For example, conventional dynamic RAM had a ×1 bit configuration, but with the expansion of applications, it has a ×4 bit configuration. Write multiple bit data signals such as x3 bits in parallel/
There is a need for diversification such as readout. The inventors of the present invention have revealed that the following problem occurs when reading multiple bits as described above.

That is, a relatively large current is passed through the main amplifier that amplifies the read signal from the memory array or the output sofa that drives a relatively large load at the timing of its operation. Therefore, x4. When transmitting a data signal such as x13 bits, 4 to 8 main amplifiers or output buffers operate simultaneously, so there is a large amount of noise (ground potential is high,
(The power supply voltage becomes low).

When such noise occurs, 1. For example, in a Guinamic RAM, the timing at which write data is input coincides with the high level of the data signal to be written.
This causes the reference voltage used to identify low levels to fluctuate greatly, resulting in malfunction.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device that can reduce noise generated in a power supply line.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, by setting the operating timing of the main amplifier and/or data output sofa with a time difference corresponding to the signal transmission time on the signal line connecting the main amplifier and/or data output sofa from each memory mat, the power supply line This method achieves noise reduction.

In a semiconductor memory device that reads at least a multi-bit signal, by shifting the operation timing of the output buffer, the peak value of the current flowing through the power supply line is alleviated, thereby reducing noise generated in the power supply line. .

〔Example〕

FIG. 1 shows the internal structure of a dynamic RAM integrated circuit (hereinafter referred to as IC) having a configuration of approximately 16K×4 bits.

The approximately 16-bit memory cells mentioned above each have 128 columns (rows) x 128 rows (columns) = 16°384 bits (
4 memory arrays with storage capacity of 16 bits)
(Memory mat) It is divided into M1 to M4 and arranged. The main blocks in this figure are drawn according to their actual geometrical arrangement.

128 decode output signals formed by a row decoder R-DCH based on address signals AXO-AXl are applied to the row-related address selection lines (word lines) of each memory array M1-M4.

Column decoder C-DCR receives address signals AYO~A
128 decoded output signals are sent out based on Yi. This column selection decode output signal is transmitted to the column switch circuit CW, which connects the data lines of each memory array M1-M4 to the common data line, thereby selecting a pair of complementary data lines. conduct.

The address buffer ADH receives multiplexed external address signals AXO-AXi and AYO-A.
Yi is processed and formed into a complementary pair address signal (an address signal corresponding to an external address signal and an address signal whose phase is inverted with respect to the address signal), and the row decoder R-DCR and column Send to decoder C-DCH. Although not particularly limited, the multiplexed complementary pair address signal is inputted to the row decoder R-DCR via the switch circuit SW, and then the switch circuit SW is opened, so that the row decoder R-DCR is processed and formed later. This is used to separate the signal from the column address signal. By doing this, the wiring for transmitting the complementary pair address signals can be shared, and the number of wirings and the area occupied can be approximately halved.

This also applies to address buffer circuits.

The sense amplifier SA is an amplifier circuit that senses the read signal from the memory cell appearing on the data line by the word line selection operation of each memory array M1 to M4.

Further, the signal passed through the column switch circuit cw is transmitted to the main amplifiers MA1 to MA4 arranged at the upper part of the figure by a common data line CD. In the read operation, the output signals of the main amplifiers MAI to MA4 are transmitted to the input/output circuits 01 to 104, respectively. In addition, in the write operation, the above input/output circuit 1
The write signals formed by I01 to I04 are directly transmitted to the common data line CD (not shown).

In this embodiment, the main amplifiers MAI to MA4,
Focusing on the fact that the wiring connecting each memory array M1 to M4, in other words, the wiring length of the common data line CD, is different,
The main amplifier operation timing signals φmal and φma2 are formed with a time itd corresponding to the signal propagation delay time until the read signal of one memory cell in each memory array Ml-M4 is transmitted to the main amplifiers Ml to M4. It is.

That is, as shown in the timing diagram of FIG. 2, the main amplifiers MAl and MA2 are
If the distance from the main amplifier MA1. MA2
is supplied with a timing signal φmal. On the other hand, memory array M3. Main amplifier MA3 like M4. MA4
If the distance from the main amplifier MA3. MA4
, the above-mentioned time difference td is determined from the above-mentioned timing signal φmal.
The timing signal φma2 is supplied with a delay of φma2.

Furthermore, two types of timing signals φo1 and φo2 are used for the operation timing of the input/output circuits IO1 to IO104, as described above.

In this embodiment, when reading 4-bit data D1 to D4, main amplifiers MAI and MA2 and main amplifier MA
3. Since MA4 operates with a difference of time td,
For example, fluctuations in the potential (VssO) of the grounding line of the circuit are divided into two peaks as shown in the figure, so the total current can be divided into two (averaged), thereby being reduced. Furthermore, the noise level generated by the input/output circuits 101 to 104, which start operating with a delay after waiting for the amplification operation of the main amplifier MA, is divided into two peaks and is averaged in the same manner as described above.

This also applies to noise generated on the power supply voltage supply line Vce side.

〔effect〕

(1) In this embodiment, the power supply line This has the effect of minimizing the noise generated in the process.

(2) The above +11 can reduce the noise generated in the power supply line, so when writing after reading, for example, when writing data input is determined, the power supply operation margin is expanded by stabilizing the reference voltage, etc. The effect is that it is possible to achieve the following.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the plurality of bits can be modified in various ways, such as 4.8 bits, as needed.

Further, when the main amplifier is provided close to each memory array, only the input/output circuits may be operated with a time difference as described above according to the difference in wiring length between the main amplifier and the input/output circuit.

[Application field]

Although the invention made by the present inventor is applied to a dynamic RAM, which is the field of application that forms the background of the invention, it is not limited thereto.
Even in the case of M (read-only memory), as mentioned above, multiple memory arrays and corresponding main amplifiers or output circuits are provided, and the layout must be such that a difference in signal propagation delay time occurs. It can be widely applied subject to the following conditions.

[Brief explanation of drawings]

FIG. 1 is an internal configuration block diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining its operation. M1-M4...Memory array, SA...Sense amplifier,
ADB: Address buffer, cw: Column switch, R-DCR: Row address decoder, C-DCR:
・Column address decoder.

Claims (1)

[Scope of Claims] 1. In a semiconductor storage device in which a memory array is arranged in a plurality of mats and stores data of a number of bits corresponding to the number of mats, a main amplifier and/or an output signal is formed with each of the memory mantles. A semiconductor memory device characterized in that the operation timing of the main amplifier and/or the data output sofa is set with a time difference corresponding to a signal propagation delay time in a signal line connecting the data output sofa. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a dynamic RAM.