JPS59197098A - Continuous word voice generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a continuous word speech generation device that generates speech consisting of a plurality of consecutive phoneme pieces.

[Prior art]

In general, games such as Iroha Calc and Hyakunin Isshu require readers with arithmetic skills. By the way, if you play the entire game without assigning arithmetic readers in a game like this,
One possible method is to record the phrases in advance on a magnetic tape using a tape recorder or the like and then play them all back, but in this case there is a problem that the playback order is fixed, making it less interesting.

[Object and structure of the invention]

This invention was made in view of the circumstances mentioned above.
The purpose is to provide a continuous word speech generating device that randomly generates one set of sounds from among a plurality of sets of sounds consisting of continuous phoneme pieces, such as the reading of Iroha Karuku.

To this end, the present invention provides a phoneme piece sound source device that generates all sounds for each phoneme month, a memory that stores a plurality of sets of phonetic word data consisting of continuous phoneme piece information, and a phoneme unit that stores a plurality of sets of phonetic word data consisting of continuous phoneme piece information. A selection circuit that randomly selects one set of speech word data, and a control circuit that sequentially sends each phoneme piece information of the selected set of phonetic word data are provided, and each phoneme piece information that is sequentially sent out is sent to the phoneme piece sound source device. By applying this, the sound source device generates all continuous sounds on one side of the phoneme.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and this embodiment is designed to randomly pronounce the pronunciations of any one of vehicle karuta, animal karuta, and iroha karuku. be. In the same figure, each phoneme of the name of iu vehicle (for example, in the case of train, [ki J, r Lj
, ``r''), and 2 is a vehicle calc memory that stores phonetic word data consisting of a plurality of phoneme piece information representing each of a plurality of vehicles, corresponding to each of a plurality of vehicles. 3 is an animal calc memory stored in the same way as calc memory 1; 3 is an Iroha calc memory that stores the audio word data of each phrase of Iroha calc in the same manner as the vehicle calc memory 1; 4 is a switch for selecting the pronunciation of the voice of the vehicle calc. , 5 is a switch to select the pronunciation of the voice of animal Calc, 6 is a switch to select the pronunciation of the voice of Iroha Calc, 1 is a switch to give a command to start pronunciation of a new set of Calc's voices, and repeat the pronunciation in order to pronounce and pronounce it. Command switch, 9
1 is a random address counter that generates a random address signal RA for randomly selecting one of a plurality of sets of voice word data stored in each memory 1 to 3, and 10 to 12 are selected by switches 4 to 6, respectively. A gate circuit 13 supplies a random address signal RA output from the random address counter 9 to the calc memories 1 to 3 of the selected type; A shift register outputs a sequential address signal SQA for sequentially sending out a plurality of phoneme piece information constituting spoken word data; 14 denotes phoneme pieces common to each other among the phoneme piece information sequentially output from memories 1 to 3; The OR gate group 15 which takes information as OR input is based on the phoneme information of the sounds "A" to "N" inputted from the OR gate group 14.
1γ is a switch 4 of a phoneme unit sound source device that generates audio signals of “A” to “N” and makes them sound from the audio system 16.
OR gates 19 and 20 which apply a logical sum signal of ON signals (yl'' signals) of 6 to 6 to a one-shot circuit 18 and generate a one-shot pulse WP1'c from the one-shot circuit 18 for resetting the random address counter 9; 21 is a one-shot circuit that generates one-shot pulses WP2 and WF2 of a predetermined pulse width when switches 7 and 8 are turned on; This is an OR gate that loads the 111 signal t to the stage.In addition, the one-shot circuit 1
The one-shot pulse WP2 outputted from the second address counter 9 is supplied to the random address counter 9 as a start signal.

In such a configuration, when producing sounds of each type of calc, the calc type is first selected by turning on one of the switches 4 to 6. For example, switch 4
When turned on, this on signal is given to the gate circuit 10, so that the random address signal RA output from the random address counter 9 is applied to the gate circuit 10.
The state given to the vehicle calc memory 1 via
The audio pronunciation related to the vehicle Calk is selected. At this time,
The ON signal of the switch 4 is also supplied as a trigger signal to the one-shot circuit 18 via the OR gate 17. Therefore, the one-shot pulse W from the one-shot circuit 18
PI occurs and random address counter 9 is reset]
・The output signal is a multi-bit random address signal HroJ (in decimal notation).

This makes it possible to read the spoken word data regarding the names of a plurality of vehicles stored in the vehicle calc memory 1 in advance. Therefore, when the sound generation command switch 7 is turned on, the one-shot circuit 19 generates a one-shot pulse WP2. This one-shot pulse Vv'P2 is given to the load signal input of the shift register 13 via the OR gate 21, and is also supplied to the random address counter 9 as a start signal. As will be described later, the random address counter 9 includes a random counter that generates a random current signal therein, a latch circuit that latches a random count signal at the timing of generation of the one-shot pulse WP2, and a latch circuit that converts the latched random count signal into a random address signal. It has a circuit that outputs the signal RA only when it has not been output as the signal RA before.

Therefore, when the one-shot pulse WP2 is generated by turning on the sound generation command switch T, this pulse W
At the generation timing of P2, the random count signal of the random counter is latched into the latch circuit.

If this latched random count signal has not been output before, this random count signal is output as a random address signal RA, and is supplied to the address signal input of the vehicle chart memory 1 via the gate circuit 10. As a result, one set of spoken word data stored at the address specified by the random address signal RA is selected from among the plurality of sets of spoken word data stored in the vehicle karuta memory 1.

On the other hand, the shift register 13 is always supplied with a clock signal φ2 of a predetermined period as a shift clock, but the one-shot pulse WP2 causes the input stage to receive a clock signal φ2 of %1.
When the ``sl'' signal is loaded, the sl'' signal is sequentially shifted toward the output stage at the generation period of the clock signal φ2. Each output signal of a plurality of stages from the input stage to the output stage of this shift register 13 is transmitted from memory 1 to
The sequential address signal SQA is applied in parallel to the lower address signal input of No. 3. Therefore, when the 1'' signal of the input stage is sequentially shifted to the right, the phoneme piece information constituting a set of speech word data selected by the random address signal RA is sequentially selected and output from the vehicle carta memory 1. be done.

The phoneme piece information sequentially outputted from the vehicle carta memory 1 in this way is inputted to the sound source section corresponding to each phoneme piece of the phoneme piece sound source device 15 via the OR gate group 14. For example, from Vehicle Carta Memory 1, r(J, rru) of "car", "
When each phoneme piece information of ``ma'' is output sequentially, each of these phoneme pieces information is input to the sound source section corresponding to each phoneme piece of r<J, rruJ, and ``maJ. In the sound source section, audio signals of "ku" JruJ and riJ are formed.

This audio signal is then output as audio from the audio system 16.

Here, when the repeat sound generation command switch 8 is turned on, a one-shot pulse WP3 is generated from the one-shot circuit 2o, but this one-shot pulse WPs is
1 to the load signal input of the shift register 13. Therefore, after the input stage of the shift register 13 is loaded with a signal power of 1" again, the clock signal φ2
It is shifted to the J@th order toward the output stage every time . As a result, the vehicle karuta memory 1 outputs the phoneme information of "ri", "ru", and "ma" again, and the sounds of t7<J, rj, Fil are pronounced again. . Therefore, by turning on the repeat sound command switch 8, the same continuous sound is repeatedly produced. can be done.

FIG. 2 is a circuit diagram showing the detailed configuration of the random address counter 9, in which a seven-stage shift register 90 and the exclusive output signal Q1 of the first stage of this shift register 9o and the output signal Q7 of the seventh stage are used. an exclusive OR signal 91 which forms a logical OR signal and feeds it back to the serial input terminal of the first stage;
1 of the clock pulse φ1 is used to sequentially shift the feedback signals from the exclusive OR 91 using the clock signal φl output from the exclusive OR 91 as a shift clock.
A random counter 93 is provided which generates a random count signal whose count value goes around once every 26 cycles. Also,
a latch circuit 95 that doubles the random count signal output from the random counter 93 by a one-shot pulse WP2 applied via an OR gate 94; a memory 96 that stores previously sent random address signals RA in the order of generation; a write address counter 91 for storing the random address signal RA sent out each time in the memory 96; a read address counter 98 for reading all the stored contents of the memory 96 every time a one-shot pulse WPz is applied; The random address signal MRA read from 96 is compared with the random count signal latched in the latch circuit 95, and if the two match, the matching signal EQ is passed through the OR gate 94 as a latch control signal of the latch circuit 95. A comparator 99 is provided which causes the latch circuit 95 to latch a new random count signal by supplying the same. Further, an AND gate 100 detects that the count value of the read address counter 98 has reached the maximum value (all bits are sl''), that is, that the read address of the memory 96 has reached the final address, and an output from the comparator 99. The signal EQ inverted by the inverter 101 and the output signal of the AND gate 100 are input, and the read address of the memory 96 becomes the final address, and the output signal of the AND gate 100 becomes 1''. If the output signal EQ of the inverter 101 is tarred at this point, the gate circuit 102 is opened and the random count signal latched by the latch circuit 95 is sent out as the random address signal RA. Incidentally, the coincidence signal EQ is sent to the read address counter 9 via the
If a signal having the same value as the random count signal latched in the latch circuit 95 is read out from the memory 96, the read address counter 98 is reset and restarted after ζ. It is configured as follows. The output word ('1'') of the AND gate 100 is also given as a stop signal to the read address counter 98, and when the read address of the memory 96 reaches the final address, the counting operation of the read address counter 98 is stopped. Further, the output signal ('1'' signal) of the AND gate 103 is also given as a trigger signal to the one-shot circuit 104, and the output signal of the AND gate 103 becomes 111. A one-shot pulse WP4 of a predetermined pulse width is generated when the signal becomes ++ times the signal, and the random count signal latched in the latch circuit 95 is written into the memory 96 by this one-shot pulse WP4. The write address counter 970 count value is updated after the delay time has elapsed.

In the above configuration, the random address counter 93 constantly outputs a random count signal whose count value changes randomly (discontinuously), but when the count value is, for example, "55" in decimal notation, a sound generation command is issued. When the switch T is turned on and the one-shot pulse WP2 is generated, a random count signal with a count value of "55" is latched into the latch circuit 95 by the one-shot pulse WP2. On the other hand, the read address counter 98 is stopped at the maximum count value, but is started after being reset by the generation of the one-shot pulse WP2. As a result, the read address counter 98 generates a read address signal 9 that sequentially specifies the first address to the last address of the memory 96, and accordingly, the stored contents are sequentially read from the memory B6.

The content read from the memory 96 is sequentially compared in a comparator 99 with a random address signal with a count value of "55" latched in the latch circuit 95.
When the read address is, for example, "i", the content read out matches the dumb/dumb address signal, the comparator 99 outputs a match signal EQ. This match No. 4i EQ is applied via OR gate 94 as a launch control signal to latch circuit 950 and as a start signal to read address counter 98. Therefore, the latch circuit 95 latches a random count signal with a new value at the timing of occurrence of the coincidence signal EQ, and the read address counter 98 is reset before its count value reaches the maximum value and then restarted. be done.

That is, if the random count signal launched in the latch circuit 95 has been previously sent as the random address signal RA, and the same random count signal is stored in the memory 96, a new signal is sent to the launch circuit 95. The random count signal is latched, and the read address counter 98 is restarted after its count value is returned to the initial value. Therefore, in such a case, the count value of the read address counter 98 does not reach the maximum value, so the output signal of the AND gate 103 remains the ant θ'' signal, and the gate circuit 102 does not open. Sending of a random address signal RA that has been sent once is prohibited.

However, if the match signal EQ is not output from the comparator 99 before the count value of the read address counter 98 reaches the maximum value, the AND gate 100 outputs the Jl
When the + signal is generated, gate circuit 102 opens, and the random count signal latched in latch circuit 95 is sent out as random address signal RA, and is supplied to gate circuits 10 to 12 in FIG. At the same time, a one-shot pulse WP4 is generated from the one-shot circuit 104, and this one-shot pulse WP4 is given as a write control signal to the memory 96, so that the random count signal latched in the latch circuit 95 is transferred to the write address counter 97. Memory 9 with count signal indicated
Written to address 6. Thereafter, the equal signal delayed by a predetermined time by the one-shot pulse WP4 total delay circuit 105 is given as a count signal to the address counter 97, and the count value of the counter 97 is updated. Preparations are made for the imposition operation.

In this case, memory 96 and read address counter 9
7 is cleared or reset by the one-shot pulse "'vVP+" output from the one-shot circuit 1B when the Karuta type is selected by the switches 4 to 6. Therefore, in such a circuit, after the start of the game
Since only the dumb address signal RA that has never been sent out is sent out, the same voice will not be sounded multiple times. Further, since the random address signal RA to be sent out changes randomly depending on the operation timing of the sound generation command switch 7, the order in which the plural sets of continuous word sounds are produced is also random, making the game more interesting.

Although this embodiment uses the Karuta game as an example, various other applications are possible, such as when arithmetic test questions are pronounced.

〔Effect of the invention〕

As explained above, the present invention includes a phoneme piece sound source device that generates sounds for each phoneme month, a memory that stores a plurality of sets of phonetic word data consisting of continuous phoneme piece information, and a plurality of sets of phonetic word data in this memory. A selection circuit that randomly selects one set of phoneme data and a control circuit that sequentially sends each phoneme piece information of the selected set of phonetic word data are provided, and each phoneme piece information that is sequentially sent out is connected to the phoneme piece sound source. By supplying this to the device, the sound source device generates continuous sounds for each phoneme month.

For this reason, it is possible to randomly generate one set of sounds out of multiple sets of sounds consisting of consecutive phoneme pieces, such as the readings of Iroha Karuta, and even one person can enjoy games such as Iroha Karuta. Other benefits include being able to practice answering exam questions on your own.

[Brief explanation of drawings]

FIG. 1 is an overall circuit diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram showing a detailed example of a random address counter. 1-3---@Memory, 4-, 6, 11 references ◆ Switch,
7... Sound command switch, 9... Random address counter, 10-12 orders... Gate circuit, 13...
...Shift register, 14...Or gate group, 1
5... Phoneme unit sound source device, 16... Audio system. Patent applicant: Nippon Musical Instruments Manufacturing Co., Ltd. Agent Kazuki Yamakawa (and 1 other person)

Claims (1)

[Claims] A phoneme piece sound source device that generates sounds for each phoneme month, a memory that stores a plurality of sets of phonetic word data consisting of continuous phoneme piece information, and one of the plurality of sets of phonetic word data in this memory.
A continuous system comprising a selection circuit that randomly selects all sets, and a control circuit that sequentially sends out each phoneme piece information of the selected set of phonetic word data and generates a sound for each phoneme month from the phoneme piece sound source device. Word speech generator.