JPS5919336A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5919336A JPS5919336A JP57127584A JP12758482A JPS5919336A JP S5919336 A JPS5919336 A JP S5919336A JP 57127584 A JP57127584 A JP 57127584A JP 12758482 A JP12758482 A JP 12758482A JP S5919336 A JPS5919336 A JP S5919336A
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- semiconductor device
- current
- control electrode
- inductance
- plate
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6644—Packaging aspects of high-frequency amplifiers
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/30107—Inductance
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は高速度で大電流のスイッチングが行える半導体
装置に関し特にその構造の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device capable of high-speed, large-current switching, and particularly to improvements in its structure.
近年各種電力機器の高効率制御に大電力用半導体デバイ
スが使われるようになっているが、通常そのスイッチン
グ速度がそれ程速くないため例えばスイッチング損失が
大きく機器の熱設計が困難であり小型化が難しいとか、
制御周波数が可聴周波数領域にあシ機器の発生する音が
作業者に不快感を与えるなどの欠点を有している。一方
、静電誘導トランジスタ（以後ＳＩＴと称す）、静電誘
導サイリスタ（以後５ＩＴｈと称す）、バイポーラトラ
ンジスタ及びＭＯＳＦＥＴなどの半導体デバイスの高周
波化、大電力化の流れは激しい。例えば、５ＩＴｈやバ
イポーラモードＳＩＴ （以後ＢＳＩＴと称す）はター
ンオン及びターンオフがきわめて速い速度で行えるとい
う特徴を持っており動作周波数を可聴周波数領域より十
分高い周波数にしてもスイッチング損失が殆んど問題に
ならないという優れた特徴を有している。例えば数１０
ＯＡの電流を０，１μＢｅｅ程度かそれ以下の速度でタ
ーンオン及びターンオフできるような能力をデバイス自
身としては持っている。In recent years, high-power semiconductor devices have been used for high-efficiency control of various power equipment, but their switching speeds are usually not that fast, resulting in large switching losses, making it difficult to thermally design the equipment, and making it difficult to miniaturize them. And,
The control frequency is in the audible frequency range, which has the disadvantage that the sound generated by the foot equipment may cause discomfort to the operator. On the other hand, there is a strong trend toward higher frequencies and higher power semiconductor devices such as static induction transistors (hereinafter referred to as SIT), static induction thyristors (hereinafter referred to as 5ITh), bipolar transistors, and MOSFETs. For example, 5ITh and bipolar mode SIT (hereinafter referred to as BSIT) have the characteristic that turn-on and turn-off can be performed at extremely high speeds, and switching loss is almost no problem even if the operating frequency is set sufficiently higher than the audio frequency range. It has the excellent feature of not being For example, number 10
The device itself has the ability to turn on and turn off the OA current at a speed of about 0.1 μBee or less.
ところで、半導体デバイスを実際に使用する時には、・
ぞッケーノに封入して使用するのが通常である。第１図
に、従来のセラミックシール平型・ぞッケーノに半導体
デバイスをマウントした装置の分解断面図を示す。この
装置は、図示のように、５ＩＴｈやＢＳＩＴなどの半導
体デバイス１、モリブデン板２ａ、２ｂ、銅などの金属
導体ブロック（第一の導体および第二の導体）３ａ、３
ｂｓ フランジ４ａ＋４ｂ、溶接板５ａ、５ｔ＋、セラ
ミック製ケース６、封止・ぐイブ兼制御電極取出し穴７
、および制御電極リード８から構成されている。この・
ぞッケーノは通常円筒形である。By the way, when actually using semiconductor devices,
It is usually used by enclosing it in a zokkeno. FIG. 1 shows an exploded cross-sectional view of a device in which a semiconductor device is mounted on a conventional flat ceramic seal. As shown in the figure, this device includes a semiconductor device 1 such as 5ITh or BSIT, molybdenum plates 2a, 2b, and metal conductor blocks (first conductor and second conductor) 3a, 3 made of copper or the like.
bs flange 4a+4b, welding plate 5a, 5t+, ceramic case 6, sealing/guive and control electrode extraction hole 7
, and a control electrode lead 8. this·
Zocceno is usually cylindrical.
ｌ・ランリスク、サイリスタの制御電極となるペース及
びゲートの取出しを行なうリード８は、これまで細いワ
イヤによって行なわれていた。したがって線状制御電極
リード８のインピーダンスが高速動作時には高くなり速
度制限の要因となっていた。Leads 8 for taking out the l-run risk, the pace and gate that serve as control electrodes of the thyristor have so far been made of thin wires. Therefore, the impedance of the linear control electrode lead 8 becomes high during high-speed operation, which becomes a factor limiting the speed.
半導体デバイス（サイリスクあるいはトランジスタ）を
高速スイッチングさせる場合、半導体デバイスのケ゛−
ト電極あるいはベース電極に対し、ターンオン時におい
ては高速に電流を供給し所定の電圧に到達せしめ、逆に
ターンオフ時においては高速に電流を吸引し所定の電圧
に到達せしめなければならないが、制御電極シー１８が
線状の場合は、それの持つインピーダンスのだめに半導
体装置の外部より制御電極リード端に与える信号が半導
体デバイスの制御電極に到達するのに遅れ時間が生じ、
かつインダクタンス成分のためオーバーシー−１−を起
す場合もありこれは波形の乱れの原因となる。とりわけ
大電流をスイッチングするサイリスクおよびトランジス
タをターンオフさせる時には制御電極より大きな電流を
吸引しなければならないが上記の傾向は顕著に現われて
高速動作の妨げとなる。５ＩＴｈやＢＳＩＴでは導通時
にチャネル部に電子とホールが大量に注入されているた
め、一方のキャリヤを制御電極で引き抜く必要がある。When switching a semiconductor device (silisk or transistor) at high speed,
During turn-on, current must be supplied to the control electrode or base electrode at high speed to reach a predetermined voltage, and conversely, when turn-off, current must be drawn at high speed to reach a predetermined voltage. If the seam 18 is linear, there will be a delay time for a signal applied to the control electrode lead end from outside the semiconductor device to reach the control electrode of the semiconductor device due to its impedance.
In addition, the inductance component may cause oversee-1, which causes waveform disturbance. In particular, when switching a large current and turning off a transistor, a larger current than the control electrode must be drawn, and the above-mentioned tendency becomes noticeable and hinders high-speed operation. In 5ITh and BSIT, a large amount of electrons and holes are injected into the channel part when conducting, so it is necessary to extract one of the carriers with a control electrode.
ターンオフの速度を速くしようとすればする程、瞬時的
に制御電極に流れる電流は大きくなる。The faster the turn-off speed is attempted, the greater the current that instantaneously flows through the control electrode.
次に、５ＩＴｈを例にとり上記の事情を説明する。Next, the above situation will be explained using 5ITh as an example.
５ＩＴｈのターンオフ時間ｔ。ｆｆは、略々で与えられ
る。但し、τ は実効キャリヤ寿命、ｆｆ
■Ａはアノード電流、■。Ｐは遮断時のケゞ−トピーク
電流である。■ＣＰが犬きくなる程ｔ。ｆｆは短かくな
る。外部マで含めて５ＩＴｈのタートインピーダンスを
ｚｇとすれば、■ＧＰＺｇはケゞ−トに加えられる逆ゲ
ートバイアスＶ。Ｋより大きくはできない。■ＣＰ・Ｚ
ｇ＞ＶｏＫとなれば、その部分は電流が遮断できず、過
渡状態が長い遮断になる。２が小さい程、小さな■。Ｋ
で大きな■。Ｐを流すことができ高速の遮断が行える。5ITh turn-off time t. ff is approximately given. However, τ is the effective carrier lifetime, ff ■A is the anode current, ■. P is the peak current at the time of interruption. ■CP is so dog-like. ff becomes shorter. If the start impedance of 5ITh including the external magnet is zg, then GPZg is the reverse gate bias V applied to the gate. It cannot be greater than K. ■CP・Z
If g>VoK, the current cannot be interrupted in that part, and the transient state is interrupted for a long time. The smaller 2 is, the smaller ■. K
So big ■. P can flow and high-speed shutoff can be performed.
デ・ぐイス自身の制御電極抵抗とパッケージの制御電極
リードのインピーダンスの和が低いことが必然的に要求
される。抵抗成分はもとより特に高速大電流のスイッチ
ングでは、インダクタンス成分の小さいことが要求され
る。It is necessarily required that the sum of the control electrode resistance of De Guis itself and the impedance of the control electrode lead of the package is low. Not only the resistance component but also the inductance component is required to be small, especially in high-speed, large-current switching.
インダクタンスＬに、時間変化のある電流が流れだとき
の降下電圧はＬ ｄｒ （ｔ ：電流、ｔ：時間）ｔ
（５）
である。例えば、Ｌ＝］ＯｎＨのインダクタンスに１０
０Ａの電流を０．１μ８ｅｅの時間で流しだとするとそ
の降下電圧はＩＯＶにもなる。半導体デバイスの制御電
極に加えられる電圧は通常高々数１０Ｖ程度である。し
たがって、わずかｌ ＯｎＨ程度のインダクタンスでも
電流の絶対値が大きく、その変化速度が速いときには、
非常に大きな電圧降下を生じるわけである。即ち、半導
体デバイスを駆動するだめの駆動回路はこの電圧降下分
だけ、半導体デバイス自身の制御に要する電圧よシ余割
に供給しなければならないことになる。When a time-varying current flows through the inductance L, the voltage drop is L dr (t: current, t: time) t (5). For example, L=]10 for the inductance of OnH.
If a current of 0A is passed for a time of 0.1μ8ee, the voltage drop will be IOV. The voltage applied to the control electrode of a semiconductor device is usually on the order of several tens of volts at most. Therefore, even if the inductance is only about 1 OnH, the absolute value of the current is large and its rate of change is fast.
This results in a very large voltage drop. In other words, the drive circuit for driving the semiconductor device must supply this voltage drop, which is more than the voltage required to control the semiconductor device itself.
今、ここで制御電極リードの自己インダクタンスを考え
てみると、直径２ ｒ ＋長さｔの線が有する自己イン
ダクタンスしは
で与えられる。２ｒ＝１閣、Ａ＝、５０ｍｍとすると、
Ｌは４３ ｎＨにもなシ到底高速大電流のスイッチング
は行えないことになる。このように自己インダクタンス
のみを考えた集中定数の概念では高速大型（６）
流のスイッチングは取扱えず、分布定数回路として伝送
線路構成を考えなければならない。Now, considering the self-inductance of the control electrode lead, it is given by the self-inductance ratio of a wire with diameter 2 r + length t. If 2r=1 kaku, A=, 50mm,
If L is even 43 nH, high-speed, large-current switching cannot be performed. In this way, the concept of lumped constants that considers only self-inductance cannot handle switching of high-speed, large (6) currents, and the transmission line configuration must be considered as a distributed constant circuit.
本発明は上記のような点に鑑み、制御電極リードを板状
にし所望のインダクタンス（Ｉ）と抵抗（８）を得易く
し、高速動作が行える半導体装置を提供しようとするも
のである。In view of the above-mentioned points, the present invention aims to provide a semiconductor device in which the control electrode lead is made into a plate shape so that desired inductance (I) and resistance (8) can be easily obtained, and which can operate at high speed.
以下、図面を参照しながら本発明を説明する。The present invention will be described below with reference to the drawings.
第２図に本発明の制御電極リードを板状にしてインダク
タンス成分を減少させた半導体装置の一実施例の分解断
面図（ａ）と分解上面図（ｂ）を示す。FIG. 2 shows an exploded sectional view (a) and an exploded top view (b) of an embodiment of a semiconductor device in which the control electrode lead of the present invention is made into a plate shape to reduce an inductance component.
この装置はザイリスタ、トランジスタ等の半導体デバイ
ス１１、モリブデン板１２ａ、１２ｂ。This device includes a semiconductor device 11 such as a Zyristor or a transistor, and molybdenum plates 12a and 12b.
銅などの導体ブロック１３ａ、１３ｂ、フランク１、４
ａ 、 １４ ｂ 、溶接板１５ａ、１５ｂ、セラミ
ック等の絶縁体のケース１６、封止ノｅイデ１７、ケゝ
−ト電極板状リード１８、およびボンディングワイヤリ
ード（あるいはリボンリード）１９等によって構成され
ている。デート電極板状リード１８は第２図（ｂ）に示
すように、四角形に切り抜かれた部分２０を有し、その
切り抜かれた部分２０に対応して半導体デバイス１１が
配置され、半導体デバイス１１の制御電極部と上記部分
２０の周囲にある４つのｒンデイングワイヤリード結合
部との間が多数の平行なボンディングワイヤリード１９
によシミ気的に結合されている。Conductor blocks 13a, 13b such as copper, flanks 1, 4
a, 14b, welding plates 15a, 15b, a case 16 made of an insulator such as ceramic, a sealing node 17, a plate electrode lead 18, a bonding wire lead (or ribbon lead) 19, etc. has been done. As shown in FIG. 2(b), the date electrode plate-shaped lead 18 has a rectangular cutout portion 20, and the semiconductor device 11 is disposed corresponding to the cutout portion 20. A large number of parallel bonding wire leads 19 are connected between the control electrode section and the four bonding wire lead coupling sections around the section 20.
The stains are closely combined.
このような構成を有する・ぐソケーノは通常広い導体板
上にマウントされる。しだがって、制御電極リード部も
、アノードやドレインの電流引き出し電極部も伝送線路
的な構成になる。このように伝送線路構成になると自己
インダクタンスは殆んど効果を持たず相互インダクタン
スが効果を持つようになる。 ′
従来の線状制御電極リードと本発明の板状制御電極リー
ドとの伝送線路的な比較を次に述べる。A device with such a configuration is usually mounted on a wide conductor plate. Therefore, both the control electrode lead portion and the anode and drain current extraction electrode portions have a transmission line-like configuration. In such a transmission line configuration, self-inductance has almost no effect, and mutual inductance has an effect. ' A comparison of transmission lines between the conventional linear control electrode lead and the plate-shaped control electrode lead of the present invention will be described below.
直径２ｒの線が導体板上に距離りだけ離れである時の、
インダクタンスＬ及びキャパシタンスＣは、いずれも単
位長当り空気中では
である。幅Ｗ１間隔りの平行平板であればμ０Ｄ
Ｌ＝ −（Ｈ／ｍ） （４）εｏＷ
Ｃ＝−
角周波数ω、透磁率μ、伝導率σ、を考慮すると角周波
数ωの増大とともに増加する。When wires with a diameter of 2r are placed a distance apart on a conductor plate,
Inductance L and capacitance C are both per unit length in air. In the case of parallel flat plates with a width of W1, μ0D L=−(H/m) (4)εoW C=− Considering the angular frequency ω, magnetic permeability μ, and conductivity σ, it increases as the angular frequency ω increases.
ｒ＝０．５ｍｍ＋ Ｄ＝５ｍｍｒＷ＝５０ｍｍとしたと
き、式（３）はＬ＝１．２０Ｘ１０−６Ｈ／ｍ 、 Ｃ
＝９．２８Ｘ１０−１２Ｆ／ｍ式（４）は
Ｌ＝１．２５６Ｘ１０−’ ）Ｌ／ｍ 、 Ｃ＝８．８
５Ｘ１０−” Ｆ／ｍとなる。ｆ ＝ Ｉ ＭＨｚとし
たときの銅を考えた抵抗は、線の場合で８．３２Ｘ１０
’Ω／ｍ ＋平板の場合で５．２２Ｘ１０ ０７ｍとな
る。When r=0.5mm+D=5mmrW=50mm, equation (3) is L=1.20X10-6H/m, C
=9.28X10-12F/m Formula (4) is L=1.256X10-')L/m, C=8.8
5X10-" F/m. When f = I MHz, the resistance considering copper is 8.32X10 in the case of a wire.
In the case of 'Ω/m + flat plate, it becomes 5.22X10 07m.
で得られるから
ｚｏ中、Ｉ′Ｆ（１−ｊ−！ｌ！−）（５）ωＬ
と近似できる。線の場合
（９）
Ｚｏ中３６０（ｔ−ｊｏ、ｏｌｌ） （Ｑｌ
（６）平板の場合
Ｚｏキ３７７（１−ｊｏ、００６６）（０）
（７）となる。Since it is obtained by , it can be approximated as I'F(1-j-!l!-)(5)ωL in zo. For lines (9) 360 in Zo (t-jo, oll) (Ql
(6) For flat plate Zoki 377 (1-jo, 0066) (0)
(7) becomes.
平板の構造のものの方がインピーダンスが線のものより
約１桁小さく、かつリアクタンス分も小さいわけである
。大電力デバイスで特に大電流のデバイスを使用すると
きＫは、デバイスの入力インピーダンス、出力インピー
ダンスともに小さくなるので入出力回路のインピーダン
スも小さい方が望ましいわけである。とりわけ大電流の
スイッチングを５ＩＴｈ ＋ＢＳＩＴなどの半導体デバ
イスで高速に行う場合にはターンオフ時に大きなケゝ−
ト電流を吸引する必要があるから、本発明による制御電
極リードのインピーダンスの低減の効果は大きい。The impedance of the flat plate structure is about one order of magnitude smaller than that of the wire structure, and the reactance is also smaller. When using a high-power device, especially a high-current device, both the input impedance and output impedance of the device are small, so it is desirable that the impedance of the input/output circuit is also small. In particular, when switching large currents at high speed with semiconductor devices such as 5ITh+BSIT, a large case is required at turn-off.
Since it is necessary to attract current from the control electrode lead, the effect of reducing the impedance of the control electrode lead according to the present invention is significant.
第２図の実施例は、ケゝ−ト電極板状リードが両側に出
ている例であるが、通常回路を構成するときには、半導
体デバイスの片側にケ°−ト制御回路を設け、その反対
側にドレインあるいはアノード（１０）
の出力取出し回路を構成することになるからケゞ−ト制
御電極は片側に取り出されているだけで十分なことが多
い。その例を第３図および第４図に示す。第２図の実施
例と同じ部分には同じ符号を用いている。いずれの構成
においても、ケゝ−ト電流及びドレインもしくはアノー
ド電流が一点に集中して流れるのではなく、拡って流れ
るようになされている。たとえ広い銅板を設けていても
、デバイスとのつなぎの部分に細い部分があると電流が
一ケ所に集中して流れることになり結局大きなインダク
タンスを持つことになって、速い電流変化にｚ」シて大
きな電圧降下を生ずることになる。The embodiment shown in Fig. 2 is an example in which the plate-shaped gate electrode leads are protruding from both sides, but when configuring a normal circuit, the gate control circuit is provided on one side of the semiconductor device, and the gate control circuit is provided on the opposite side. Since the drain or anode (10) output extraction circuit is formed on the side, it is often sufficient to have the gate control electrode taken out on one side. Examples are shown in FIGS. 3 and 4. The same parts as in the embodiment of FIG. 2 are given the same reference numerals. In either configuration, the gate current and the drain or anode current do not flow concentrated at one point, but rather spread out. Even if a wide copper plate is provided, if there is a thin part where it connects to the device, the current will concentrate in one place and end up having a large inductance, causing rapid current changes. This will result in a large voltage drop.
本発明の効果を示す例として、高周波用コンデンサとし
て市販されている耐圧２，０ＯＯＶ、１０μＦのコンデ
ンサ（６０Ｘ１００Ｘ１５０鵡３容積、端子が上部に２
個設けられている）を用いて行った実験例を次に説明す
る。本発明に基づく工夫を施した構造の半導体デバイス
Ｔを用いて第５図の高周波大電流のスイッチング回路を
構成した。この半導体デバイスは２００Ａの電流がオン
、オフできるものである。実験は電流スイッチングを観
測しようとするものであるためＲＬ＝Ｏ、ＲＭ−０，０
１Ωとしである。As an example showing the effects of the present invention, a capacitor with a withstand voltage of 2,000 V and 10 μF (60 x 100
An example of an experiment conducted using the following will be described below. A high-frequency, large-current switching circuit shown in FIG. 5 was constructed using a semiconductor device T having a structure based on the present invention. This semiconductor device can turn on and off a current of 200A. Since the experiment is to observe current switching, RL=O, RM-0,0
It is 1Ω.
先ス第５図の回路において、コンデンザＣＤトＣｇに前
記の高周波用コンデンサを用い、この端子には幅２ｃｍ
の網状の線で片側約１０Ｃｒｎずつ全体で２０Ｃ１ｎの
配線を施した。この回路構成で得られる電流のスイッチ
ング波形は第６図（、）のようなものであった。即ち立
上り、立下りともに遅くて、しかも電流が殆んど流れな
いという結果になった。In the circuit shown in FIG.
Wiring was performed using a net-like wire of about 10 Crn on each side and a total of 20 C1n. The current switching waveform obtained with this circuit configuration was as shown in FIG. 6(,). That is, both the rise and fall were slow, and the result was that almost no current flowed.
このような結果になったのはコンデンサに配線した幅の
広いリード線にインダクタンスによる電圧降下が生じて
し壕っているからである。This result is due to the voltage drop caused by inductance in the wide lead wire connected to the capacitor.
次に、両側にリードの出ている容積の小さなコンデンサ
を１０ケ並列にならべて、１０μＦを構成した。リード
のインダクタンスが減少すると同時に電流が細い部分に
集中して流れることがなくなるため実効的なインダクタ
ンスはさらに減少している。その時の電流波形は第６図
（ｂ）のようになる２００Ａの電流スイッチングが０１
５μＳｅｅ以下のスイッチング時間で達成されている。Next, 10 small-capacity capacitors with leads on both sides were arranged in parallel to form a 10 μF capacitor. At the same time as the lead inductance decreases, the effective inductance further decreases because the current no longer flows concentrated in a narrow portion. The current waveform at that time is as shown in Figure 6(b).The current switching of 200A is 01
This is achieved with a switching time of 5μSee or less.
このように本発明により電流を分散させインダクタンス
を低下せしめた効果は本実験結果に顕著に現われている
。また本実験結果は高速大電流のスイッチングが行える
半導体デ・ぐイスができても回路の構成方法及び使用す
るコンデンサや抵抗等の回路を構成する素子の構造が大
電流高速のスイッチングに適したものでなければ、半導
体デ／Ｊイスの高速性を活かすことができないことをも
示している。As described above, the effect of dispersing the current and lowering the inductance according to the present invention is clearly seen in the results of this experiment. The results of this experiment also show that even if a semiconductor device capable of high-speed, large-current switching is created, the circuit construction method and the structure of the elements that make up the circuit, such as the capacitors and resistors used, are suitable for high-current, high-speed switching. This also shows that otherwise, the high speed of semiconductor devices/J devices cannot be utilized.
本発明の半導体装置は、回路構成に配慮すれば数１０Ｏ
Ａといっだ大電流がきわめて高速にスイッチングできる
ことになシ、大電力の制御が効率よく行え、しかもその
動作周波数が容易に可聴周波数領域を超えた領域に持ち
込めるため作業者に不快感を与えることもなく、スイッ
チング損失も小さくでき実装設計を容易にし、その工業
的価値はきわめて大きい。The semiconductor device of the present invention can be realized by several tens of Ω if the circuit configuration is taken into account.
The fact that large currents such as A can be switched at extremely high speeds means that large amounts of power can be controlled efficiently, and the operating frequency can easily exceed the audible frequency range, causing discomfort to workers. Therefore, the switching loss can be reduced and the mounting design can be simplified, and its industrial value is extremely large.
第１図は従来のセラミックシール平形・ぐツケー（１３
）
ノを用いた半導体装置の分解断面図である。
第２図は本発明の半導体装置の一実施例で、同図（、）
は分解断面図、同図（ｂ）は分解上面図である。
第３図および第４図はそれぞれ本発明の半導体装置の他
の実施例を示すもので、（ａ）は分解断面図、（ｂ）は
分解」−面図である。
第５図は本発明の半導体装置の特性を調べるために用い
た大電流スイッチング測定回路である。
第６図は第５図の回路構成で得られる電流のスイッチン
グ波形を示すもので、（ａ）は高周波コンデンサ１個の
ときの波形、（ｂ）は１０個並列にしたときの波形であ
る。
１１・・・半導体デバイス、１２ａ、１２ｂ・・・モリ
ブデン板、１３ａ、１３ｂ・・・銅などの金属導体ブロ
ック、１４ａ 、 １４．ｂ−フランツ、１’５ａ、１
５ｂ・・・溶接板、１６・・・セラミック等の絶縁体の
ケース、１７・・・封止パイプ、１８・・・ケ゛−ト電
極板状リード、１９・・・ボンディングワイヤリード。
（１４）
ｊ１３［！ｆ
（ａ）
第 ５ 図
Ｃｃ 、−−］Ｒ。
第６図
（０）
骨
（ｂ）
ｍ−２１，１ｓｅｃ−−−−
手続補正書（自発）
昭和５８年２月２８１ＥＩ
特許庁長官 若 杉 和 夫 殿
り′事件の表示 特願昭５７−１２７５８４号３、補
正をする者
事件との関係 出願人
住 所 愛知県愛知郡長久手町大字長鍬字横道４１
番地の１名 称 （３６０）株式会社豊田中央研究所
代表者 小 松 登４、代理
人〒１０５
５、補正により増加する発明の数
６、補正の対象 明細書の発明の詳細な説明の欄７
、補正の内容
明細書第８頁第１５行から第１０頁第７行１での１直径
２ｒの線が・・・・・・・わけである。」を次のとおり
訂正する。
「直径２ｒの線が空気中で広い導体板上に平行に距離り
だけ離れである時の特性インピーダンス２゜は
である。幅Ｗの板状導体が空気中で広い導体板上に平行
に距＃Ｄだけ離れであるときの特性インピーダンス２゜
は近似的に
ｒ ＝ ０．５” 、 Ｄ ＝ ５＋ｍ 、 Ｗ ＝
５Ｑｔｕｍとしたとき、線の場合式（３）よりＺｏ中
１８０（Ω）となり、平板の場合式（４）よシＺ ＝ｉ
＝ ３０（Ω）となる。即ち、平板の構造のものの方が
インピーダンスが線のものよりかなシ小さくできるわけ
である。」以 上
２−Figure 1 shows the conventional ceramic seal flat type
) is an exploded cross-sectional view of a semiconductor device using a semiconductor device. Figure 2 shows an embodiment of the semiconductor device of the present invention.
is an exploded cross-sectional view, and FIG. 3(b) is an exploded top view. 3 and 4 respectively show other embodiments of the semiconductor device of the present invention, in which (a) is an exploded sectional view and (b) is an exploded cross-sectional view. FIG. 5 shows a large current switching measurement circuit used to examine the characteristics of the semiconductor device of the present invention. FIG. 6 shows the current switching waveforms obtained with the circuit configuration of FIG. 5, where (a) is the waveform when one high-frequency capacitor is used, and (b) is the waveform when 10 high-frequency capacitors are connected in parallel. 11... Semiconductor device, 12a, 12b... Molybdenum plate, 13a, 13b... Metal conductor block such as copper, 14a, 14. b-Franz, 1'5a, 1
5b... Welding plate, 16... Case made of insulator such as ceramic, 17... Sealing pipe, 18... Kate electrode plate lead, 19... Bonding wire lead. (14) j13[! f (a) Figure 5Cc, --]R. Figure 6 (0) Bone (b) m-21,1sec--- Procedural amendment (voluntary) February 1981 281EI Commissioner of the Patent Office Wakasugi Kazuo Tonori' Case Indication Patent application 1982-127584 No. 3. Relationship with the case of the person making the amendment Applicant address: 41 Nagakugi Yokomichi, Nagakute-machi, Aichi-gun, Aichi Prefecture
Name of address (360) Toyota Central Research Institute Co., Ltd. Representative Noboru Komatsu 4, Agent 〒105 5, Number of inventions increased by amendment 6, Subject of amendment Column 7 for detailed explanation of the invention in the specification
, a line with a diameter of 2r from page 8, line 15 to page 10, line 7, 1 of the specification of contents of the amendment is... ” is corrected as follows. "The characteristic impedance 2° when a wire with a diameter 2r is placed parallel to a wide conductor plate in the air and separated by a distance is .When a plate-like conductor with a width W is placed parallel to a wide conductor plate in the air and separated by a distance, the characteristic impedance 2° is. The characteristic impedance 2° when separated by #D is approximately r = 0.5", D = 5 + m, W =
When 5 Qtum, in the case of a wire, it is 180 (Ω) in Zo according to equation (3), and in the case of a flat plate, according to equation (4), Z = i
= 30 (Ω). In other words, the impedance of a flat plate structure can be made much smaller than that of a wire structure. ” Above 2-
Claims (1)
と第二の導体を有し、かつこれらの導体間を電気的に分
離する筒状絶縁体の中間に前記半導体デバイス基板の制
御電極部に接続された第三の導体を有する平型の半導体
装置において、第三の導体が前記半導体デバイス基板の
一方の幅あるいは直径と略々間しかもしくはそれ以上の
幅を有する少くとも１つの結合部をもつ板状であるとと
もに、第三の導体の前記結合部と半導体デバイスの制御
電極部との間を多数の平行なポンディングワイヤまたは
リボンのリードによ多結合したことを特徴とする半導体
装置。A control electrode portion of the semiconductor device substrate is located between a cylindrical insulator that has a first conductor and a second conductor facing each other with the semiconductor device substrate in between, and electrically isolates these conductors. a flat semiconductor device having a third conductor connected to at least one bonding portion in which the third conductor has a width approximately equal to or greater than the width or diameter of one of the semiconductor device substrates; A semiconductor device characterized in that it is plate-shaped and has a plurality of parallel bonding wires or ribbon leads connected between the coupling portion of the third conductor and the control electrode portion of the semiconductor device. .
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57127584A JPS5919336A (en) | 1982-07-23 | 1982-07-23 | Semiconductor device |
| US06/516,543 US4692789A (en) | 1982-07-23 | 1983-07-22 | Semiconductor apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57127584A JPS5919336A (en) | 1982-07-23 | 1982-07-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5919336A true JPS5919336A (en) | 1984-01-31 |
| JPH0212021B2 JPH0212021B2 (en) | 1990-03-16 |
Family
ID=14963678
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57127584A Granted JPS5919336A (en) | 1982-07-23 | 1982-07-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5919336A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4989067A (en) * | 1989-07-03 | 1991-01-29 | General Electric Company | Hybrid interconnection structure |
| US5477130A (en) * | 1993-07-07 | 1995-12-19 | Sanyo Electric Co., Ltd. | Battery pack with short circuit protection |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5395583A (en) * | 1977-02-01 | 1978-08-21 | Toshiba Corp | Mesa type semiconductor device |
-
1982
- 1982-07-23 JP JP57127584A patent/JPS5919336A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5395583A (en) * | 1977-02-01 | 1978-08-21 | Toshiba Corp | Mesa type semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4989067A (en) * | 1989-07-03 | 1991-01-29 | General Electric Company | Hybrid interconnection structure |
| US5477130A (en) * | 1993-07-07 | 1995-12-19 | Sanyo Electric Co., Ltd. | Battery pack with short circuit protection |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0212021B2 (en) | 1990-03-16 |
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